From 3bd8b12b2feb0942b87b86270f2c7d2e79831937 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sat, 6 Sep 2014 18:40:36 +0000 Subject: [PATCH] set interrupt and level to same values MiNT driver expects --- BaS_gcc/include/interrupts.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/BaS_gcc/include/interrupts.h b/BaS_gcc/include/interrupts.h index e6e0d8d..43bbbd8 100644 --- a/BaS_gcc/include/interrupts.h +++ b/BaS_gcc/include/interrupts.h @@ -79,20 +79,20 @@ #define INT_SOURCE_GPT0 62 // GPT0 timer interrupt -#define FEC0_INTC_LVL 1 /* interrupt level for FEC0 */ -#define FEC0_INTC_PRI 2 /* interrupt priority for FEC0 */ +#define FEC0_INTC_LVL 5 /* interrupt level for FEC0 */ +#define FEC0_INTC_PRI 1 /* interrupt priority for FEC0 */ -#define FEC1_INTC_LVL 1 /* interrupt level for FEC1 */ -#define FEC1_INTC_PRI 2 /* interrupt priority for FEC1 */ +#define FEC1_INTC_LVL 5 /* interrupt level for FEC1 */ +#define FEC1_INTC_PRI 0 /* interrupt priority for FEC1 */ #define FEC_INTC_LVL(x) ((x == 0) ? FEC0_INTC_LVL : FEC1_INTC_LVL) #define FEC_INTC_PRI(x) ((x == 0) ? FEC0_INTC_PRI : FEC1_INTC_PRI) #define FEC0RX_DMA_PRI 5 -#define FEC1RX_DMA_PRI 5 +#define FEC1RX_DMA_PRI 3 #define FECRX_DMA_PRI(x) ((x == 0) ? FEC0RX_DMA_PRI : FEC1RX_DMA_PRI) #define FEC0TX_DMA_PRI 6 -#define FEC1TX_DMA_PRI 6 +#define FEC1TX_DMA_PRI 4 #define FECTX_DMA_PRI(x) ((x == 0) ? FEC0TX_DMA_PRI : FEC1TX_DMA_PRI) extern int register_interrupt_handler(uint8_t source, uint8_t level, uint8_t priority, uint8_t intr, void (*handler)(void));