now gets accepted by Modelsim

vhdl/rtl/vhdl/WF_FDC1772_IP/wf1772ip_control.vhd

@@ -1286,7 +1286,8 @@ begin
 			if CMD_STATE = T1_STEP then
 				case DDEn is
 					when '1' => CNT := x"80"; --Start counter for FM step pulse.
-                    when '0' => CNT := x"40"; --Start counter for MFM step pulse.
+          when '0' => CNT := x"40"; --Start counter for MFM step pulse.
+        when others => CNT := x"80";
 				end case;
 			elsif CNT > x"00" then
 				CNT := CNT - 1; -- Count 63 or 127 CLK cycles ...

vhdl/rtl/vhdl/WF_FDC1772_IP/wf1772ip_digital_pll.vhd

@@ -219,6 +219,7 @@ begin
 				ADDER_MSBs <= std_logic_vector(ADDER_DATA(11 downto 9));
 			when "10" => -- FM mode using DD disks, results in 4us inspection period:
 				ADDER_MSBs <= std_logic_vector(ADDER_DATA(12 downto 10));
+			when others => ADDER_MSBs <= std_logic_vector(ADDER_DATA(11 downto 9));
 		end case;
 	end process ADDER;
 
@@ -315,6 +316,7 @@ begin
 							when "101" => FREQ_AMOUNT := "1010";
 							when "110" => FREQ_AMOUNT := "1011";
 							when "111" => FREQ_AMOUNT := "1100";
+							when others => FREQ_AMOUNT := "0100";
 						end case;
 					when 1 =>
 						case ADDER_MSBs is
@@ -326,6 +328,7 @@ begin
 							when "101" => FREQ_AMOUNT := "1001";
 							when "110" => FREQ_AMOUNT := "1010";
 							when "111" => FREQ_AMOUNT := "1011";
+							when others => FREQ_AMOUNT := "0011";
 						end case;
 					when others =>
 						FREQ_AMOUNT := "0000";
@@ -371,6 +374,7 @@ begin
 					when "101" => PHASE_AMOUNT := "101000";
 					when "110" => PHASE_AMOUNT := "101100";
 					when "111" => PHASE_AMOUNT := "110000";
+					when others => PHASE_AMOUNT := "010000";
 				end case;
 			elsif RD_PULSE = '1' and DDEn = '1' and HDTYPE = '1' then -- FM mode, double density
 				case ADDER_MSBs is -- Multiplier: 2.
@@ -382,6 +386,7 @@ begin
 					when "101" => PHASE_AMOUNT := "100100";
 					when "110" => PHASE_AMOUNT := "100110";
 					when "111" => PHASE_AMOUNT := "101000";
+					when others => PHASE_AMOUNT := "001000";
 				end case;
             elsif RD_PULSE = '1' and DDEn = '0' and HDTYPE = '0' then -- MFM mode, single density
 				case ADDER_MSBs is -- Multiplier: 2.
@@ -393,6 +398,7 @@ begin
 					when "101" => PHASE_AMOUNT := "100011";
 					when "110" => PHASE_AMOUNT := "100100";
 					when "111" => PHASE_AMOUNT := "100110";
+					when others => PHASE_AMOUNT := "000110";
 				end case;
 			elsif RD_PULSE = '1' and DDEn = '0' and HDTYPE = '1' then -- MFM mode, double density.
 				case ADDER_MSBs is -- Multiplier: 1.
@@ -404,6 +410,7 @@ begin
 					when "101" => PHASE_AMOUNT := "100010";
 					when "110" => PHASE_AMOUNT := "100011";
 					when "111" => PHASE_AMOUNT := "100100";
+					when others => PHASE_AMOUNT := "000100";
 				end case;
 			else -- Modify phase amount register:
                 if PHASE_AMOUNT(4 downto 0) > x"0" then

vhdl/rtl/vhdl/WF_FDC1772_IP/wf1772ip_transceiver.vhd

@@ -253,6 +253,7 @@ begin
 					else
 						FM_In <= '1';
 					end if;
+				when OTHERS => FM_In <= '0';
 			end case;
 		end if;
 	end process FM_ENCODER;
@@ -445,6 +446,7 @@ begin
 					else
 						MFM_In <= '1';
 					end if;
+				when others => MFM_In <= '0';
 			end case;
 		end if;
 	end process MFM_WR_OUT;

vhdl/rtl/vhdl/WF_MFP68901_IP/wf68901ip_timers.vhd

@@ -306,6 +306,7 @@ begin
 				when "010" => PRESCALE := x"09"; -- Prescaler = 10.
 				when "001" => PRESCALE := x"03"; -- Prescaler = 4.
 				when "000" => PRESCALE := x"00"; -- Timer stopped or event count mode.
+				when others => PRESCALE := x"00";
 			end case;
 			A_CNTSTRB <= '1';
 		end if;
@@ -329,6 +330,7 @@ begin
 				when "010" => PRESCALE := x"09"; -- Prescaler = 10.
 				when "001" => PRESCALE := x"03"; -- Prescaler = 4.
 				when "000" => PRESCALE := x"00"; -- Timer stopped or event count mode.
+				when others => PRESCALE := x"00";
 			end case;
 			B_CNTSTRB <= '1';
 		end if;
@@ -352,6 +354,7 @@ begin
 				when "010" => PRESCALE := x"09"; -- Prescaler = 10.
 				when "001" => PRESCALE := x"03"; -- Prescaler = 4.
 				when "000" => PRESCALE := x"00"; -- Timer stopped.
+				when others => PRESCALE := x"00";
 			end case;
 			C_CNTSTRB <= '1';
 		end if;
@@ -375,6 +378,7 @@ begin
 				when "010" => PRESCALE := x"09"; -- Prescaler = 10.
 				when "001" => PRESCALE := x"03"; -- Prescaler = 4.
 				when "000" => PRESCALE := x"00"; -- Timer stopped.
+				when others => PRESCALE := x"00";
 			end case;
 			D_CNTSTRB <= '1';
 		end if;
@@ -420,6 +424,7 @@ begin
 							TAO_I <= not TAO_I; -- Toggle the timer A output pin.
 							TIMER_A_INT <= '1';
 						end if;
+				  when others => TAO_I <= '0';
 				end case;					
 			end if;
 		end if;
@@ -465,6 +470,7 @@ begin
 							TBO_I <= not TBO_I; -- Toggle the timer B output pin.
 							TIMER_B_INT <= '1';
 						end if;
+					when others => TBO_I <= '0';
 				end case;					
 			end if;
 		end if;

vhdl/rtl/vhdl/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd

@@ -184,6 +184,7 @@ begin
 				when "01" => LOOPBACK <= '0'; SD_LEVEL <= '0'; SDOUT_EN <= '1';
 				when "10" => LOOPBACK <= '0'; SD_LEVEL <= '1'; SDOUT_EN <= '1';
 				when "11" => LOOPBACK <= '1'; SD_LEVEL <= '1'; SDOUT_EN <= '1';
+				when others => LOOPBACK <= '0'; SD_LEVEL <= '0'; SDOUT_EN <= '0';
 			end case;			
 		end if;
 	end process SOUT_CONFIG;

vhdl/rtl/vhdl/WF_MFP68901_IP/wf68901ip_usart_tx.vhd

@@ -197,10 +197,11 @@ begin
 			elsif TR_STATE = LOAD_SHFT then
 				-- Load 'normal' data if there is no break condition:
 				case CL is
-					when "11" => SHIFT_REG <= "000" & TX_DATA(4 downto 0); -- 5 datastd_logics.
+					when "11" => SHIFT_REG <= "000" & TX_DATA(4 downto 0); -- 5 databits.
-					when "10" => SHIFT_REG <= "00" & TX_DATA(5 downto 0); -- 6 datastd_logics.
+					when "10" => SHIFT_REG <= "00" & TX_DATA(5 downto 0); -- 6 databits
-					when "01" => SHIFT_REG <= '0' & TX_DATA(6 downto 0); -- 7 datastd_logics.
+					when "01" => SHIFT_REG <= '0' & TX_DATA(6 downto 0); -- 7 databits
-					when "00" => SHIFT_REG <= TX_DATA; -- 8 datastd_logics.
+					when "00" => SHIFT_REG <= TX_DATA; -- 8 databits
+					when others => SHIFT_REG <= x"00";
 				end case;
 			elsif TR_STATE = SHIFTOUT and CLK_STRB = '1' then
 				SHIFT_REG <= '0' & SHIFT_REG(7 downto 1); -- Shift right.

vhdl/rtl/vhdl/WF_SND2149_IP/wf2149ip_top_soc.vhd

@@ -149,7 +149,8 @@ begin
 		BUSCYCLE <= INACTIVE	when "000" | "010" | "101",
 					ADDRESS 	when "001" | "100" | "111",
 					R_READ 		when "011",
-					R_WRITE 	when "110";
+					R_WRITE 	when "110",
+					INACTIVE when others;
 
 	ADDRESSLATCH: process(RESETn, SYS_CLK)
 	-- This process is responsible to store the desired register