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USB chip registers seem to be visible now

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This commit is contained in:
Markus Fröschle
2013-11-09 17:35:49 +00:00
parent e82cd3dd69
commit 37dc24315a
3 changed files with 24 additions and 11 deletions
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4
BaS_gcc/.gdbinit
View File

@@ -1,7 +1,7 @@
#set disassemble-next-line on #set disassemble-next-line on
define tr define tr
# target remote | m68k-bdm-gdbserver pipe /dev/bdmcf3 target remote | m68k-bdm-gdbserver pipe /dev/bdmcf3
target remote | m68k-bdm-gdbserver pipe /dev/tblcf3 #target remote | m68k-bdm-gdbserver pipe /dev/tblcf3
monitor bdm-reset monitor bdm-reset
end end
define tbtr define tbtr

6
BaS_gcc/sources/ohci-hcd.c
View File

@@ -70,6 +70,7 @@
* e.g. PCI controllers need this * e.g. PCI controllers need this
*/ */
#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
#ifdef CONFIG_SYS_OHCI_SWAP_REG_ACCESS #ifdef CONFIG_SYS_OHCI_SWAP_REG_ACCESS
#define readl(a) swpl(*((volatile uint32_t *)(a))) #define readl(a) swpl(*((volatile uint32_t *)(a)))
#define writel(a, b) (*((volatile uint32_t *)(b)) = swpl((volatile uint32_t)a)) #define writel(a, b) (*((volatile uint32_t *)(b)) = swpl((volatile uint32_t)a))
@@ -1642,6 +1643,7 @@ static int hc_reset(ohci_t *ohci)
} }
xprintf("control: %x\r\n", readl(&ohci->regs->control)); xprintf("control: %x\r\n", readl(&ohci->regs->control));
ohci_dump_status(ohci);
if (readl(&ohci->regs->control) & OHCI_CTRL_IR) if (readl(&ohci->regs->control) & OHCI_CTRL_IR)
{ {
/* SMM owns the HC */ /* SMM owns the HC */
@@ -1663,7 +1665,7 @@ static int hc_reset(ohci_t *ohci)
/* Reset USB (needed by some controllers) */ /* Reset USB (needed by some controllers) */
ohci->hc_control = 0; ohci->hc_control = 0;
writel(ohci->hc_control, &ohci->regs->control); writel(ohci->hc_control, &ohci->regs->control);
wait(50 * 1000); wait(50);
/* HC Reset requires max 10 us delay */ /* HC Reset requires max 10 us delay */
writel(OHCI_HCR, &ohci->regs->cmdstatus); writel(OHCI_HCR, &ohci->regs->cmdstatus);
while ((readl(&ohci->regs->cmdstatus) & OHCI_HCR) != 0) while ((readl(&ohci->regs->cmdstatus) & OHCI_HCR) != 0)
@@ -1673,7 +1675,7 @@ static int hc_reset(ohci_t *ohci)
err("USB HC reset timed out!"); err("USB HC reset timed out!");
return -1; return -1;
} }
wait(1 * 1000); wait(10);
} }
return 0; return 0;
} }

25
BaS_gcc/sources/pci.c
View File

@@ -300,6 +300,7 @@ static void pci_device_config(uint16_t bus, uint16_t device, uint16_t function)
int16_t index = - 1; int16_t index = - 1;
struct pci_rd *descriptors; struct pci_rd *descriptors;
int i; int i;
uint32_t value;
static uint32_t mem_address = PCI_MEMORY_OFFSET; static uint32_t mem_address = PCI_MEMORY_OFFSET;
static uint32_t io_address = PCI_IO_OFFSET; static uint32_t io_address = PCI_IO_OFFSET;
@@ -319,9 +320,6 @@ static void pci_device_config(uint16_t bus, uint16_t device, uint16_t function)
descriptors = resource_descriptors[index]; descriptors = resource_descriptors[index];
for (i = 0; i < 6; i++) /* for all bars */ for (i = 0; i < 6; i++) /* for all bars */
{ {
uint32_t value;
/* /*
* read BAR[i] value * read BAR[i] value
*/ */
@@ -348,6 +346,7 @@ static void pci_device_config(uint16_t bus, uint16_t device, uint16_t function)
{ {
/* adjust base address to card's alignment requirements */ /* adjust base address to card's alignment requirements */
int size = ~(address & 0xfffffff0) + 1; int size = ~(address & 0xfffffff0) + 1;
xprintf("device 0x%x: BAR[%d] requests %d kBytes of memory\r\n", handle, i, size / 1024);
/* calculate a valid map adress with alignment requirements */ /* calculate a valid map adress with alignment requirements */
mem_address = (mem_address + size - 1) & ~(size - 1); mem_address = (mem_address + size - 1) & ~(size - 1);
@@ -366,7 +365,7 @@ static void pci_device_config(uint16_t bus, uint16_t device, uint16_t function)
rd->flags = 0 | FLG_8BIT | FLG_16BIT | FLG_32BIT | ORD_MOTOROLA; rd->flags = 0 | FLG_8BIT | FLG_16BIT | FLG_32BIT | ORD_MOTOROLA;
rd->start = mem_address; rd->start = mem_address;
rd->length = size; rd->length = size;
rd->offset = 0; rd->offset = PCI_MEMORY_OFFSET;
rd->dmaoffset = 0; rd->dmaoffset = 0;
/* adjust memory adress for next turn */ /* adjust memory adress for next turn */
@@ -378,6 +377,7 @@ static void pci_device_config(uint16_t bus, uint16_t device, uint16_t function)
else if (IS_PCI_IO_BAR(value)) /* same as above for I/O resources */ else if (IS_PCI_IO_BAR(value)) /* same as above for I/O resources */
{ {
int size = ~(address & 0xfffffffc) + 1; int size = ~(address & 0xfffffffc) + 1;
xprintf("device 0x%x: BAR[%d] requests %d bytes of memory\r\n", handle, i, size);
io_address = (io_address + size - 1) & ~(size - 1); io_address = (io_address + size - 1) & ~(size - 1);
pci_write_config_longword(handle, PCIBAR0 + i, swpl(io_address)); pci_write_config_longword(handle, PCIBAR0 + i, swpl(io_address));
@@ -389,7 +389,7 @@ static void pci_device_config(uint16_t bus, uint16_t device, uint16_t function)
rd->next = sizeof(struct pci_rd); rd->next = sizeof(struct pci_rd);
rd->flags = FLG_IO | FLG_8BIT | FLG_16BIT | FLG_32BIT | 1; rd->flags = FLG_IO | FLG_8BIT | FLG_16BIT | FLG_32BIT | 1;
rd->start = io_address; rd->start = io_address;
rd->offset = PCI_MEMORY_OFFSET; rd->offset = PCI_IO_OFFSET;
rd->length = size; rd->length = size;
rd->dmaoffset = PCI_MEMORY_OFFSET; rd->dmaoffset = PCI_MEMORY_OFFSET;
@@ -402,6 +402,16 @@ static void pci_device_config(uint16_t bus, uint16_t device, uint16_t function)
/* mark end of resource chain */ /* mark end of resource chain */
if (barnum > 0) if (barnum > 0)
descriptors[barnum - 1].flags |= FLG_LAST; descriptors[barnum - 1].flags |= FLG_LAST;
/*
* enable device finally
*/
value = swpl(pci_read_config_longword(handle, PCICSR));
value |= 0xffff035f;
pci_write_config_longword(handle, PCICSR, swpl(value));
value = swpl(pci_read_config_longword(handle, PCICSR));
xprintf("device 0x%02x PCICSR = 0x%08x\r\n", handle, value);
} }
/* /*
@@ -441,6 +451,7 @@ void pci_scan(void)
PCI_DEVICE_FROM_HANDLE(handle), PCI_DEVICE_FROM_HANDLE(handle),
PCI_FUNCTION_FROM_HANDLE(handle)); PCI_FUNCTION_FROM_HANDLE(handle));
} }
handle = pci_find_device(0x0, 0xFFFF, ++index); handle = pci_find_device(0x0, 0xFFFF, ++index);
} }
xprintf("\r\n...finished\r\n"); xprintf("\r\n...finished\r\n");
@@ -513,8 +524,8 @@ void init_pci(void)
*/ */
/* initiator window 0 base / translation adress register */ /* initiator window 0 base / translation adress register */
MCF_PCI_PCIIW0BTAR = PCI_MEMORY_OFFSET | (((PCI_MEMORY_SIZE - 1) >> 8) & 0xffff0000) | MCF_PCI_PCIIW0BTAR = PCI_MEMORY_OFFSET | (((PCI_MEMORY_SIZE - 1) >> 8) & 0xffff0000);
PCI_MEMORY_OFFSET >> 16; /* | PCI_MEMORY_OFFSET >> 16; */
/* initiator window 1 base / translation adress register */ /* initiator window 1 base / translation adress register */
MCF_PCI_PCIIW1BTAR = (PCI_IO_OFFSET | ((PCI_IO_SIZE - 1) >> 8)) & 0xffff0000; MCF_PCI_PCIIW1BTAR = (PCI_IO_OFFSET | ((PCI_IO_SIZE - 1) >> 8)) & 0xffff0000;