moved IRQ service handler for PSC3 interrupt to the BaS ISR dispatcher
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@@ -185,27 +185,27 @@
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.equ MCD_TT_FLAGS_RL, 0x1
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.equ MCD_TT_FLAGS_RL, 0x1
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.equ MCD_TT_FLAGS_SP, 0x4
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.equ MCD_TT_FLAGS_SP, 0x4
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.equ DMA_ALWAYS, 0
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.equ DMA_ALWAYS, 0
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//---------------------------------------------------
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/*********************************************************************
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/*
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*
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*
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* General Purpose Timers (GPT)
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* General Purpose Timers (GPT)
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*
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*
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*********************************************************************/
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*/
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/* Register read/write macros */
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/* Register read/write macros */
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#define MCF_GPT0_GMS __MBAR+0x800
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#define MCF_GPT0_GMS __MBAR+0x800
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/*********************************************************************
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/*
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*
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*
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* Slice Timers (SLT)
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* Slice Timers (SLT)
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*
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*
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*********************************************************************/
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*/
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#define MCF_SLT0_SCNT __MBAR+0x908
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#define MCF_SLT0_SCNT __MBAR+0x908
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/**********************************************************/
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/*
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// macros
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* macros
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/**********************************************************/
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*/
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.altmacro
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.altmacro
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.macro irq vector,int_mask,clr_int
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.macro irq vector,int_mask,clr_int
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//move.w #0x2700,sr // disable interrupt
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//move.w #0x2700,sr // disable interrupt
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@@ -292,7 +292,7 @@ init_vec_loop:
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move.l a1,0x11c(a0)
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move.l a1,0x11c(a0)
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// install PSC vectors (used for PIC communication on the FireBee)
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// install PSC vectors (used for PIC communication on the FireBee)
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lea handler_psc3(pc),a1
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lea _lowlevel_isr_handler(pc),a1
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// PSC3 interrupt source = 32
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// PSC3 interrupt source = 32
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move.l a1,(INT_SOURCE_PSC3 + 64) * 4(a0)
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move.l a1,(INT_SOURCE_PSC3 + 64) * 4(a0)
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@@ -541,7 +541,7 @@ irq7text:
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irq5: // irq5 is tied to PCI INTC# and PCI INTD# on the M5484LITE
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irq5: // irq5 is tied to PCI INTC# and PCI INTD# on the M5484LITE
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irq 0x74,5,0x20
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irq 0x74,5,0x20
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irq6: // MFP interrupt from FPGA
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irq6: // MFP interrupt from FPGA
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move.w #0x2700,sr // disable interrupt
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move.w #0x2700,sr // disable interrupt
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subq.l #8,a7
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subq.l #8,a7
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movem.l d0/a5,(a7) // save registers
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movem.l d0/a5,(a7) // save registers
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@@ -817,41 +817,6 @@ irq7:
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move.l (sp)+,a0
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move.l (sp)+,a0
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rts // Forward to the Access Error handler
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rts // Forward to the Access Error handler
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/*
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* psc3 com PIC MCF
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*/
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handler_psc3:
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move.w #0x2700,sr // disable interrupt
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lea -20(a7),a7
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movem.l d0-d2/a0/a3,(a7)
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lea MCF_PSC3_PSCRB_8BIT,a3
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move.b (a3),d1
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cmp.b #2,d1 // anforderung rtc daten?
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bne psc3_fertig
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lea MCF_PSC0_PSCTB_8BIT,a0 // ++ vr
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mchar move.l,'\P,'\I,'C,' ,(a0)
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mchar move.l,'I,'N,'T,'\ ,(a0)
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mchar move.l,'R,'T,'C,'!,(a0)
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mchar move.l,0x0d,0x0a,0,0,(a0)
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lea 0xffff8961,a0
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lea MCF_PSC3_PSCTB_8BIT,a3
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clr.l d1
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moveq #64,d2
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move.b #0x82,(a3) // header: rtcd mcf->pic
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loop_sr2:
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move.b d1,(a0)
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move.b 2(a0),d0
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move.b d0,(a3)
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addq.l #1,d1
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cmp.b d1,d2
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bne loop_sr2
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psc3_fertig:
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movem.l (a7),d0-d2/a0/a3 // restore saved registers
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lea 20(a7),a7
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RTE
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/*
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/*
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* general purpose timer 0 (GPT0): video change, later also others. GPT0 is used as
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* general purpose timer 0 (GPT0): video change, later also others. GPT0 is used as
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* input trigger. It is connected to the TIN0 signal of the FPGA and triggers everytime
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* input trigger. It is connected to the TIN0 signal of the FPGA and triggers everytime
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@@ -996,17 +961,17 @@ video_chg_end:
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_lowlevel_isr_handler:
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_lowlevel_isr_handler:
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move.w #0x2700,sr
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move.w #0x2700,sr
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lea -5 * 4(sp),sp // make room for
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link a6,#-4 * 4 // make room for
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movem.l d0-d1/a0-a2,(sp) // gcc scratch registers and save them,
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movem.l d0-d1/a0-a1,(sp) // gcc scratch registers and save them,
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// other registers will be handled by gcc itself
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// other registers will be handled by gcc itself
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move.w 5 * 4(sp),d0 // fetch vector number from stack
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move.w 4(a6),d0 // fetch vector number from stack
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lsr.l #2,d0 // move it in place
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lsr.l #2,d0 // move it in place
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andi.l #0x000000ff,d0 // mask it out
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andi.l #0xff,d0 // mask it out
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move.l d0,-(sp) // push it
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move.l d0,-(sp) // push it
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jsr _isr_execute_handler // call the C handler
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jsr _isr_execute_handler // call the C handler
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addq.l #4,sp // adjust stack
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addq.l #4,sp // adjust stack
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movem.l (sp),d0-d1/a0-a2 // restore registers
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movem.l (sp),d0-d1/a0-a1 // restore registers
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lea 5 * 4(sp),sp
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unlk a6
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rte
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rte
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@@ -209,7 +209,7 @@ bool isr_execute_handler(int vector)
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/*
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/*
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* PIC interrupt handler for Firebee
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* PIC interrupt handler for Firebee
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*/
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*/
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void pic_interrupt_handler(void)
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int pic_interrupt_handler(void *arg1, void *arg2)
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{
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{
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uint8_t rcv_byte;
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uint8_t rcv_byte;
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@@ -229,6 +229,7 @@ void pic_interrupt_handler(void)
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MCF_PSC3_PSCTB_8BIT = *rtc_data;
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MCF_PSC3_PSCTB_8BIT = *rtc_data;
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} while (index++ < 64);
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} while (index++ < 64);
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}
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}
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return 1;
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}
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}
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extern int32_t video_sbt;
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extern int32_t video_sbt;
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