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merged latest fixes from R_0_8_6 branch

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This commit is contained in:
Markus Fröschle
2014-12-29 14:44:55 +00:00
parent 8cb34bfe15
commit 320230ce31
1 changed files with 269 additions and 381 deletions
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268
BaS_gcc/sys/sysinit.c
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@@ -30,6 +30,7 @@
#include "startcf.h" #include "startcf.h"
#include "cache.h" #include "cache.h"
#include "sysinit.h" #include "sysinit.h"
#include "pci.h"
#include "bas_printf.h" #include "bas_printf.h"
#include "bas_string.h" #include "bas_string.h"
#include "bas_types.h" #include "bas_types.h"
@@ -46,18 +47,13 @@
#error "unknown machine" #error "unknown machine"
#endif /* MACHINE_M5484LITE */ #endif /* MACHINE_M5484LITE */
#
#include "dma.h" #include "dma.h"
#include "mod_devicetable.h" #include "mod_devicetable.h"
#include "pci_ids.h" #include "pci_ids.h"
#include "driver_mem.h" #include "driver_mem.h"
#include "usb.h" #include "usb.h"
#include "video.h"
#define DEBUG_SYSINIT
#ifdef DEBUG_SYSINIT
#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
#else
#define dbg(format, arg...) do { ; } while (0)
#endif /* DEBUG_SYSINIT */
#define UNUSED(x) (void)(x) /* Unused variable */ #define UNUSED(x) (void)(x) /* Unused variable */
@@ -248,7 +244,7 @@ void init_serial(void)
MCF_PSC0_PSCOPSET = 0x01; MCF_PSC0_PSCOPSET = 0x01;
MCF_PSC0_PSCCR = 0x05; MCF_PSC0_PSCCR = 0x05;
#if defined(MACHINE_FIREBEE) /* PSC3 is not connected to anything on the LITE board */ #ifdef MACHINE_FIREBEE /* PSC3 is not connected to anything on the LITE board */
/* PSC3: PIC */ /* PSC3: PIC */
MCF_PSC3_PSCSICR = 0; // UART MCF_PSC3_PSCSICR = 0; // UART
MCF_PSC3_PSCCSR = 0xDD; MCF_PSC3_PSCCSR = 0xDD;
@@ -426,24 +422,24 @@ void init_fbcs()
| MCF_FBCS_CSCR_AA; /* AA */ | MCF_FBCS_CSCR_AA; /* AA */
MCF_FBCS1_CSMR = MCF_FBCS_CSMR_BAM_1M | MCF_FBCS_CSMR_V; MCF_FBCS1_CSMR = MCF_FBCS_CSMR_BAM_1M | MCF_FBCS_CSMR_V;
MCF_FBCS2_CSAR = 0xF0000000; // NEUER I/O ADRESS-BEREICH MCF_FBCS2_CSAR = 0xF0000000; /* Firebee new I/O address range */
MCF_FBCS2_CSCR = MCF_FBCS_CSCR_PS_32 // 32BIT PORT MCF_FBCS2_CSCR = MCF_FBCS_CSCR_PS_32 /* 32BIT PORT */
| MCF_FBCS_CSCR_WS(8) // DEFAULT 4WS | MCF_FBCS_CSCR_WS(8) /* DEFAULT 4WS */
| MCF_FBCS_CSCR_AA; // AA | MCF_FBCS_CSCR_AA; /* AA */
MCF_FBCS2_CSMR = (MCF_FBCS_CSMR_BAM_128M // F000'0000-F7FF'FFFF MCF_FBCS2_CSMR = (MCF_FBCS_CSMR_BAM_128M /* F000'0000-F7FF'FFFF */
| MCF_FBCS_CSMR_V); | MCF_FBCS_CSMR_V);
MCF_FBCS3_CSAR = 0xF8000000; // NEUER I/O ADRESS-BEREICH MCF_FBCS3_CSAR = 0xF8000000; /* Firebee new I/O address range */
MCF_FBCS3_CSCR = MCF_FBCS_CSCR_PS_16 // 16BIT PORT MCF_FBCS3_CSCR = MCF_FBCS_CSCR_PS_16 /* 16BIT PORT */
| MCF_FBCS_CSCR_AA; // AA | MCF_FBCS_CSCR_AA; // AA
MCF_FBCS3_CSMR = (MCF_FBCS_CSMR_BAM_64M // F800'0000-FBFF'FFFF MCF_FBCS3_CSMR = (MCF_FBCS_CSMR_BAM_64M /* F800'0000-FBFF'FFFF */
| MCF_FBCS_CSMR_V); | MCF_FBCS_CSMR_V);
MCF_FBCS4_CSAR = 0x40000000; // VIDEO RAM BEREICH, #FB_CS3 WIRD NICHT BENÜTZT, DECODE DIREKT AUF DEM FPGA MCF_FBCS4_CSAR = 0x40000000; /* video ram area, FB_CS3 not used, decoded on FPGA */
MCF_FBCS4_CSCR = MCF_FBCS_CSCR_PS_32 // 32BIT PORT MCF_FBCS4_CSCR = MCF_FBCS_CSCR_PS_32 /* 32BIT PORT */
| MCF_FBCS_CSCR_BSTR // BURST READ ENABLE | MCF_FBCS_CSCR_BSTR /* burst read enable */
| MCF_FBCS_CSCR_BSTW; // BURST WRITE ENABLE | MCF_FBCS_CSCR_BSTW; /* burst write enable */
MCF_FBCS4_CSMR = MCF_FBCS_CSMR_BAM_1G // 4000'0000-7FFF'FFFF MCF_FBCS4_CSMR = MCF_FBCS_CSMR_BAM_1G /* 4000'0000-7FFF'FFFF */
| MCF_FBCS_CSMR_V; | MCF_FBCS_CSMR_V;
#elif MACHINE_M5484LITE #elif MACHINE_M5484LITE
/* disable other FBCS for now */ /* disable other FBCS for now */
@@ -484,123 +480,12 @@ void wait_pll(void)
} while ((* (volatile int16_t *) 0xf0000800 < 0) && MCF_SLT0_SCNT > trgt); } while ((* (volatile int16_t *) 0xf0000800 < 0) && MCF_SLT0_SCNT > trgt);
} }
static volatile uint8_t *pll_base = (volatile uint8_t *) 0xf0000600;
volatile uint8_t *pll_base = (volatile uint8_t *) 0xf0000600;
//#define _OLD_CODE_ /* use old PLL initialization code */
#ifndef _OLD_CODE_
/*
* the altpll_reconfig component is connected to the Bus as follows:
*
* 9 bit data:
* 876543210 (this _is_ actually the last part of the address written or read!)
* | || |
* | |+--+- counter_type
* +-+----- counter_param
*
* 9 bit data
* 876543210
* +-------+- data_in
*
* counter_type selects which counter should be affected by data_in:
* 0000 - N
* 0001 - M
* 0010 - CP/LF (charge pump/loop filter)
* 0011 - VCO (voltage controlled oscillator)
* 0100 - C0
* 0101 - C1
* 0110 - C2
* 0111 - C3
* 1000 - C4
*
* counter_param selects which part of the selected counter_type is set/read and how many
* bits are used/valid:
*
* for counter_type N, M, C0-C4:
* 000 - high count, 8 bit
* 001 - low count, 8 bit
* 100 - bypass, 1 bit
* 101 - mode (odd/even division), 1 bit
*
* for counter_type CP/LF:
* 101 - charge pump unused, 5 bit
* 000 - charge pump current, 3 bit
* 100 - loop filter unused, 1 bit
* 001 - loop filter resistor, 5 bit
* 010 - loop filter capacitance, 2 bit
*
* for counter_type VCO:
* 000 - VCO post scale, 1 bit
*/
#define PLL_COUNTER_TYPE_N 0
#define PLL_COUNTER_TYPE_M 1
#define PLL_COUNTER_TYPE_CPLF 2
#define PLL_COUNTER_TYPE_VCO 3
#define PLL_COUNTER_TYPE_C0 4
#define PLL_COUNTER_TYPE_C1 5
#define PLL_COUNTER_TYPE_C2 6
#define PLL_COUNTER_TYPE_C3 7
#define PLL_COUNTER_TYPE_C4 8
#define PLL_COUNTER_PARAM_HC 0
#define PLL_COUNTER_PARAM_LC 1
#define PLL_COUNTER_PARAM_BP 4
#define PLL_COUNTER_PARAM_MODE 5
#define PLL_COUNTER_PARAM_CP_U 5
#define PLL_COUNTER_PARAM_CP_C 0
#define PLL_COUNTER_PARAM_LF_U 4
#define PLL_COUNTER_PARAM_LF_R 1
#define PLL_COUNTER_PARAM_LF_C 2
#define PLL_COUNTER_PARAM_VCO_PS 0
void pll_write(int type, int param, int data)
{
wait_pll();
* (volatile uint16_t *) (pll_base + ((param << 6) | (type << 2))) = data;
}
struct pll_init
{
int type;
int param;
int data;
};
struct pll_init pll_values[] =
{
{ PLL_COUNTER_TYPE_CPLF, PLL_COUNTER_PARAM_LF_R, 27 }, /* loopfilter R */
{ PLL_COUNTER_TYPE_CPLF, PLL_COUNTER_PARAM_LF_C, 1 }, /* charge pump 1 */
{ PLL_COUNTER_TYPE_N, PLL_COUNTER_PARAM_HC, 12 }, /* N counter high */
{ PLL_COUNTER_TYPE_N, PLL_COUNTER_PARAM_LC, 12 }, /* N counter low */
{ PLL_COUNTER_TYPE_C1, PLL_COUNTER_PARAM_BP, 1 }, /* c1 bypass */
{ PLL_COUNTER_TYPE_C2, PLL_COUNTER_PARAM_BP, 1 }, /* c2 bypass */
{ PLL_COUNTER_TYPE_C3, PLL_COUNTER_PARAM_BP, 1 }, /* c3 bypass */
{ PLL_COUNTER_TYPE_C0, PLL_COUNTER_PARAM_HC, 1 }, /* c0 high */
{ PLL_COUNTER_TYPE_C0, PLL_COUNTER_PARAM_LC, 1 }, /* c0 low */
{ PLL_COUNTER_TYPE_M, PLL_COUNTER_PARAM_MODE, 1 }, /* M odd division */
{ PLL_COUNTER_TYPE_M, PLL_COUNTER_PARAM_LC, 1 }, /* M low = 1 */
{ PLL_COUNTER_TYPE_M, PLL_COUNTER_PARAM_HC, 145 } /* M high = 145 = 146 MHz */
};
int num_pll_values = sizeof(pll_values) / sizeof(struct pll_init);
#endif /* _OLD_CODE_ */
void init_pll(void) void init_pll(void)
{ {
int i;
xprintf("FPGA PLL initialization: "); xprintf("FPGA PLL initialization: ");
#ifndef _OLD_CODE_
for (i = 0; i < num_pll_values; i++)
{
pll_write(pll_values[i].type, pll_values[i].param, pll_values[i].data);
}
#else /* _OLD_CODE_ */
wait_pll(); wait_pll();
* (volatile uint16_t *) (pll_base + 0x48) = 27; /* loopfilter r */ * (volatile uint16_t *) (pll_base + 0x48) = 27; /* loopfilter r */
@@ -638,7 +523,6 @@ void init_pll(void)
* (volatile uint16_t *) (pll_base + 0x04) = 145; /* M high = 145 = 146 MHz */ * (volatile uint16_t *) (pll_base + 0x04) = 145; /* M high = 145 = 146 MHz */
wait_pll(); wait_pll();
#endif /* _OLD_CODE_ */
* (volatile uint8_t *) 0xf0000800 = 0; /* set */ * (volatile uint8_t *) 0xf0000800 = 0; /* set */
@@ -646,7 +530,7 @@ void init_pll(void)
} }
#define NOP() __asm__ __volatile__("nop\n\t" : : : "memory")
/* /*
* INIT VIDEO DDR RAM * INIT VIDEO DDR RAM
*/ */
@@ -678,7 +562,7 @@ void init_video_ddr(void) {
_VRAM = 0000070022; /* load MR dll on */ _VRAM = 0000070022; /* load MR dll on */
NOP(); NOP();
* (uint32_t *) 0xf0000400 = 0x01070002; /* fifo on, refresh on, ddrcs and cke on, video dac on */ * (uint32_t *) 0xf0000400 = 0x01070002; /* fifo on, refresh on, ddrcs und cke on, video dac on */
xprintf("finished\r\n"); xprintf("finished\r\n");
} }
@@ -700,33 +584,29 @@ void init_usb(void)
do do
{ {
handle = pci_find_classcode(PCI_CLASS_SERIAL_USB, index++); handle = pci_find_device(0x0000, 0xffff, index++);
if (handle > 0) if (handle > 0)
{ {
uint32_t id = 0; uint32_t id = 0;
uint32_t pci_class = 0; uint32_t class = 0;
dbg("PCI device handle = %x\r\n", handle);
id = pci_read_config_longword(handle, PCIIDR); id = pci_read_config_longword(handle, PCIIDR);
pci_class = pci_read_config_longword(handle, PCIREV); class = pci_read_config_longword(handle, PCIREV);
if (PCI_CLASS_CODE(pci_class) == PCI_CLASS_SERIAL_USB) if (PCI_CLASS_CODE(class) == PCI_CLASS_SERIAL_USB)
{ {
xprintf("serial USB found at bus=0x%x, dev=0x%x, fnc=0x%x (0x%x)\r\n", xprintf("serial USB found at bus=0x%x, dev=0x%x, fnc=0x%x (0x%x)\r\n",
PCI_BUS_FROM_HANDLE(handle), PCI_BUS_FROM_HANDLE(handle),
PCI_DEVICE_FROM_HANDLE(handle), PCI_DEVICE_FROM_HANDLE(handle),
PCI_FUNCTION_FROM_HANDLE(handle), PCI_FUNCTION_FROM_HANDLE(handle),
handle); handle);
if (PCI_SUBCLASS(class) == PCI_CLASS_SERIAL_USB_EHCI)
if (PCI_SUBCLASS(pci_class) == PCI_CLASS_SERIAL_USB_EHCI)
{ {
board = ehci_usb_pci_table; board = ehci_usb_pci_table;
while (board->vendor) while (board->vendor)
{ {
if ((board->vendor == PCI_VENDOR_ID(id)) && board->device == PCI_DEVICE_ID(id)) if ((board->vendor == PCI_VENDOR_ID(id)) && board->device == PCI_DEVICE_ID(id))
{ {
dbg("match. trying to init board\r\n");
if (usb_init(handle, board) >= 0) if (usb_init(handle, board) >= 0)
{ {
usb_found++; usb_found++;
@@ -735,20 +615,16 @@ void init_usb(void)
board++; board++;
} }
} }
if (PCI_SUBCLASS(class) == PCI_CLASS_SERIAL_USB_OHCI)
if (PCI_SUBCLASS(pci_class) == PCI_CLASS_SERIAL_USB_OHCI)
{ {
board = ohci_usb_pci_table; board = ohci_usb_pci_table;
while (board->vendor) while (board->vendor)
{ {
if ((board->vendor == PCI_VENDOR_ID(id)) && board->device == PCI_DEVICE_ID(id)) if ((board->vendor == PCI_VENDOR_ID(id)) && board->device == PCI_DEVICE_ID(id))
{ {
if (usb_init(handle, board) >= 0) if (usb_init(handle, board) >= 0)
{
usb_found++; usb_found++;
} }
}
board++; board++;
} }
} }
@@ -756,7 +632,7 @@ void init_usb(void)
} }
} while (handle >= 0); } while (handle >= 0);
xprintf("finished (found %d USB host controller(s))\r\n", usb_found); xprintf("finished (found %d USB controller(s))\r\n", usb_found);
} }
static bool i2c_transfer_finished(void) static bool i2c_transfer_finished(void)
@@ -769,7 +645,7 @@ static bool i2c_transfer_finished(void)
static void wait_i2c_transfer_finished(void) static void wait_i2c_transfer_finished(void)
{ {
waitfor(100000, i2c_transfer_finished); /* wait until interrupt bit has been set */ waitfor(10000, i2c_transfer_finished); /* wait until interrupt bit has been set */
MCF_I2C_I2SR &= ~MCF_I2C_I2SR_IIF; /* clear interrupt bit (byte transfer finished */ MCF_I2C_I2SR &= ~MCF_I2C_I2SR_IIF; /* clear interrupt bit (byte transfer finished */
} }
@@ -814,7 +690,7 @@ void dvi_on(void)
wait_i2c_transfer_finished(); wait_i2c_transfer_finished();
if (MCF_I2C_I2SR & MCF_I2C_I2SR_RXAK) /* next try if no acknowledge */ if (MCF_I2C_I2SR & MCF_I2C_I2SR_RXAK) /* next try if no acknowledge */
continue; goto try_again;
MCF_I2C_I2DR = 0x00; /* send data: SUB ADRESS 0 */ MCF_I2C_I2DR = 0x00; /* send data: SUB ADRESS 0 */
wait_i2c_transfer_finished(); wait_i2c_transfer_finished();
@@ -824,12 +700,11 @@ void dvi_on(void)
wait_i2c_transfer_finished(); wait_i2c_transfer_finished();
if (MCF_I2C_I2SR & MCF_I2C_I2SR_RXAK) /* next try if no acknowledge */ if (MCF_I2C_I2SR & MCF_I2C_I2SR_RXAK) /* next try if no acknowledge */
continue; goto try_again;
#ifdef _NOT_USED_ #ifdef _NOT_USED_
MCH_I2C_I2CR &= ~MCF_I2C_I2CR_MTX; /* FIXME: not clear where this came from ... */ MCH_I2C_I2CR &= ~MCF_I2C_I2CR_MTX; /* FIXME: not clear where this came from ... */
#endif /* _NOT_USED_ */ #endif /* _NOT_USED_ */
MCF_I2C_I2CR &= 0xef; /* ... this actually disables the I2C module... */ MCF_I2C_I2CR &= 0xef; /* ... this actually disables the I2C module... */
dummyByte = MCF_I2C_I2DR; /* dummy read */ dummyByte = MCF_I2C_I2DR; /* dummy read */
@@ -842,63 +717,63 @@ void dvi_on(void)
MCF_I2C_I2CR = MCF_I2C_I2CR_IEN; /* stop */ MCF_I2C_I2CR = MCF_I2C_I2CR_IEN; /* stop */
dummyByte = MCF_I2C_I2DR; /* dummy read */ dummyByte = MCF_I2C_I2DR; // dummy read
if (receivedByte != 0x4c) if (receivedByte != 0x4c)
continue; goto try_again;
MCF_I2C_I2CR = 0x0; /* stop */ MCF_I2C_I2CR = 0x0; // stop
MCF_I2C_I2SR = 0x0; /* clear sr */ MCF_I2C_I2SR = 0x0; // clear sr
waitfor(10000, i2c_bus_free); waitfor(10000, i2c_bus_free);
MCF_I2C_I2CR = 0xb0; /* on tx master */ MCF_I2C_I2CR = 0xb0; // on tx master
MCF_I2C_I2DR = 0x7A; MCF_I2C_I2DR = 0x7A;
wait_i2c_transfer_finished(); wait_i2c_transfer_finished();
if (MCF_I2C_I2SR & MCF_I2C_I2SR_RXAK) if (MCF_I2C_I2SR & MCF_I2C_I2SR_RXAK)
continue; goto try_again;
MCF_I2C_I2DR = 0x08; /* SUB ADRESS 8 */ MCF_I2C_I2DR = 0x08; // SUB ADRESS 8
wait_i2c_transfer_finished(); wait_i2c_transfer_finished();
MCF_I2C_I2DR = 0xbf; /* ctl1: power on, T:M:D:S: enable */ MCF_I2C_I2DR = 0xbf; // ctl1: power on, T:M:D:S: enable
wait_i2c_transfer_finished(); wait_i2c_transfer_finished();
MCF_I2C_I2CR = 0x80; /* stop */ MCF_I2C_I2CR = 0x80; // stop
dummyByte = MCF_I2C_I2DR; /* dummy read */ dummyByte = MCF_I2C_I2DR; // dummy read
MCF_I2C_I2SR = 0x0; /* clear sr */ MCF_I2C_I2SR = 0x0; // clear sr
waitfor(10000, i2c_bus_free); waitfor(10000, i2c_bus_free);
MCF_I2C_I2CR = 0xb0; MCF_I2C_I2CR = 0xb0;
MCF_I2C_I2DR = 0x7a; MCF_I2C_I2DR = 0x7A;
wait_i2c_transfer_finished(); wait_i2c_transfer_finished();
if (MCF_I2C_I2SR & MCF_I2C_I2SR_RXAK) if (MCF_I2C_I2SR & MCF_I2C_I2SR_RXAK)
continue; goto try_again;
MCF_I2C_I2DR = 0x08; /* SUB ADRESS 8 */ MCF_I2C_I2DR = 0x08; // SUB ADRESS 8
wait_i2c_transfer_finished(); wait_i2c_transfer_finished();
MCF_I2C_I2CR |= 0x4; /* repeat start */ MCF_I2C_I2CR |= 0x4; // repeat start
MCF_I2C_I2DR = 0x7b; /* begin read */ MCF_I2C_I2DR = 0x7b; // beginn read
wait_i2c_transfer_finished(); wait_i2c_transfer_finished();
if (MCF_I2C_I2SR & MCF_I2C_I2SR_RXAK) if (MCF_I2C_I2SR & MCF_I2C_I2SR_RXAK)
continue; goto try_again;
MCF_I2C_I2CR &= 0xef; /* switch to rx */ MCF_I2C_I2CR &= 0xef; // switch to rx
dummyByte = MCF_I2C_I2DR; /* dummy read */ dummyByte = MCF_I2C_I2DR; // dummy read
wait_i2c_transfer_finished(); wait_i2c_transfer_finished();
MCF_I2C_I2CR |= 0x08; /* txak=1 */ MCF_I2C_I2CR |= 0x08; // txak=1
wait(50); wait(50);
@@ -906,9 +781,11 @@ void dvi_on(void)
wait_i2c_transfer_finished(); wait_i2c_transfer_finished();
MCF_I2C_I2CR = 0x80; /* stop */ MCF_I2C_I2CR = 0x80; // stop
dummyByte = MCF_I2C_I2DR; /* dummy read */ dummyByte = MCF_I2C_I2DR; // dummy read
try_again:
num_tries++; num_tries++;
} while ((receivedByte != 0xbf) && (num_tries < 10)); } while ((receivedByte != 0xbf) && (num_tries < 10));
@@ -920,7 +797,8 @@ void dvi_on(void)
{ {
xprintf("finished\r\n"); xprintf("finished\r\n");
} }
UNUSED(dummyByte); /* Avoid warning */ UNUSED(dummyByte);
// Avoid warning
} }
@@ -994,31 +872,27 @@ livo:
MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME
MCF_PSC2_PSCTB_AC97 = 0x16000000; //SLOT1:WR REG AUX VOLUME adr 0x16 MCF_PSC2_PSCTB_AC97 = 0x16000000; //SLOT1:WR REG AUX VOLUME adr 0x16
MCF_PSC2_PSCTB_AC97 = 0x06060000; //SLOT1:VOLUME MCF_PSC2_PSCTB_AC97 = 0x06060000; //SLOT1:VOLUME
for (i = 3; i < 13; i++) for (i = 3; i < 13; i++) {
{
MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0 MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0
} }
// line in VOLUME +12dB // line in VOLUME +12dB
MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME
MCF_PSC2_PSCTB_AC97 = 0x10000000; //SLOT1:WR REG MASTER VOLUME adr 0x02 MCF_PSC2_PSCTB_AC97 = 0x10000000; //SLOT1:WR REG MASTER VOLUME adr 0x02
for (i = 2; i < 13; i++) for (i = 2; i < 13; i++) {
{
MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0 MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0
} }
// cd in VOLUME 0dB // cd in VOLUME 0dB
MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME
MCF_PSC2_PSCTB_AC97 = 0x12000000; //SLOT1:WR REG MASTER VOLUME adr 0x02 MCF_PSC2_PSCTB_AC97 = 0x12000000; //SLOT1:WR REG MASTER VOLUME adr 0x02
for (i = 2; i < 13; i++) for (i = 2; i < 13; i++) {
{
MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0 MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0
} }
// mono out VOLUME 0dB // mono out VOLUME 0dB
MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME
MCF_PSC2_PSCTB_AC97 = 0x06000000; //SLOT1:WR REG MASTER VOLUME adr 0x02 MCF_PSC2_PSCTB_AC97 = 0x06000000; //SLOT1:WR REG MASTER VOLUME adr 0x02
MCF_PSC2_PSCTB_AC97 = 0x00000000; //SLOT1:WR REG MASTER VOLUME adr 0x02 MCF_PSC2_PSCTB_AC97 = 0x00000000; //SLOT1:WR REG MASTER VOLUME adr 0x02
for (i = 3; i < 13; i++) for (i = 3; i < 13; i++) {
{
MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0 MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0
} }
MCF_PSC2_PSCTFCR |= MCF_PSC_PSCTFCR_WFR; //set EOF MCF_PSC2_PSCTFCR |= MCF_PSC_PSCTFCR_WFR; //set EOF
@@ -1064,6 +938,8 @@ void clear_bss_segment(void)
void initialize_hardware(void) void initialize_hardware(void)
{ {
bool coldboot = true;
/* Test for FireTOS switch: DIP switch #5 up */ /* Test for FireTOS switch: DIP switch #5 up */
#ifdef MACHINE_FIREBEE #ifdef MACHINE_FIREBEE
if (!(DIP_SWITCH & (1 << 6))) { if (!(DIP_SWITCH & (1 << 6))) {
@@ -1107,9 +983,6 @@ void initialize_hardware(void)
#endif #endif
, MAJOR_VERSION, MINOR_VERSION, __DATE__, __TIME__); , MAJOR_VERSION, MINOR_VERSION, __DATE__, __TIME__);
extern char *rom_header;
xprintf("running from %p\r\n\r\n", &rom_header);
/* /*
* Determine cause(s) of Reset * Determine cause(s) of Reset
*/ */
@@ -1182,13 +1055,19 @@ void initialize_hardware(void)
init_slt(); init_slt();
init_fbcs(); init_fbcs();
init_ddram(); coldboot = init_ddram();
/* /*
* install (preliminary) exception vectors * install (preliminary) exception vectors
*/ */
setup_vectors(); setup_vectors();
#ifdef _NOT_USED_
/* make sure the handlers are called */
__asm__ __volatile__("dc.w 0xafff"); /* should trigger a line-A exception */
#endif /* _NOT_USED_ */
/* /*
* save the planet (and reduce case heat): disable clocks of unused SOC modules * save the planet (and reduce case heat): disable clocks of unused SOC modules
*/ */
@@ -1222,6 +1101,8 @@ void initialize_hardware(void)
} }
#if MACHINE_FIREBEE #if MACHINE_FIREBEE
if (coldboot) /* does not work with BDM */
;
fpga_configured = init_fpga(); fpga_configured = init_fpga();
init_pll(); init_pll();
@@ -1230,6 +1111,13 @@ void initialize_hardware(void)
#endif /* MACHINE_FIREBEE */ #endif /* MACHINE_FIREBEE */
driver_mem_init(); driver_mem_init();
init_pci();
video_init();
/* do not try to init USB for now on the Firebee, it hangs the machine */
#ifndef MACHINE_FIREBEE
//init_usb();
#endif
#if MACHINE_FIREBEE #if MACHINE_FIREBEE
init_ac97(); init_ac97();