reactivated delay chain
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@@ -17,7 +17,7 @@
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-- CREATED "Mon Jan 11 09:20:56 2016"
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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LIBRARY work;
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@@ -1929,7 +1929,7 @@ BEGIN
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PORT MAP
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(
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wren_a => ST_CLUT_WR(1),
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wren_b => SYNTHESIZED_WIRE_55,
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wren_b => '0',
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clock_a => MAIN_CLK,
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clock_b => pixel_clk_i,
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address_a => FB_ADR(4 DOWNTO 1),
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@@ -1945,7 +1945,7 @@ BEGIN
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PORT MAP
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(
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wren_a => ST_CLUT_WR(1),
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wren_b => SYNTHESIZED_WIRE_56,
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wren_b => '0',
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clock_a => MAIN_CLK,
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clock_b => pixel_clk_i,
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address_a => FB_ADR(4 DOWNTO 1),
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@@ -1961,7 +1961,7 @@ BEGIN
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PORT MAP
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(
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wren_a => ST_CLUT_WR(0),
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wren_b => SYNTHESIZED_WIRE_57,
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wren_b => '0',
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clock_a => MAIN_CLK,
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clock_b => pixel_clk_i,
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address_a => FB_ADR(4 DOWNTO 1),
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