SD card module works. Disk and FATFS read work.
TODO: adapt SPI clock to SD card type for faster transfer
This commit is contained in:
Markus Fröschle
@@ -1,6 +1,7 @@
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#include <stdint.h>
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#include <bas_types.h>
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#include <sd_card.h>
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#include <bas_printf.h>
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#include "sysinit.h"
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/*
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@@ -44,8 +45,8 @@
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#define SSPxCR0 SSP1CR0
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#define SSPxCR1 SSP1CR1
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#define SSPxCPSR SSP1CPSR
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#define CS_LOW() {FIO0CLR0 = _BV(6);} /* Set P0.6 low */
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#define CS_HIGH() {FIO0SET0 = _BV(6);} /* Set P0.6 high */
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#define CS_HIGH() { dspi_fifo_val &= ~MCF_DSPI_DTFR_CS5; }
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#define CS_LOW() { dspi_fifo_val |= MCF_DSPI_DTFR_CS5; }
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#define PCSSPx PCSSP1
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#define PCLKSSPx PCLK_SSP1
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#endif
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@@ -110,15 +111,25 @@ static uint8_t CardType; /* Card type flags */
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/* Send/Receive data to the MMC (Platform dependent) */
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/*-----------------------------------------------------------------------*/
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static uint32_t dspi_fifo_val = /* CONT disable continous chip select */
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/* CTAS use DCTAR0 for clock and attributes */
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MCF_DSPI_DTFR_EOQ; /* current transfer is last in queue */
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/* Exchange a byte */
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static uint8_t xchg_spi(uint8_t byte)
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{
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* (volatile uint8_t *) (&MCF_DSPI_DTFR + 3) = byte;
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uint32_t fifo = dspi_fifo_val | byte;
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uint8_t res;
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//while (! (MCF_DSPI_DSR & MCF_DSPI_DSR_TCF)); /* wait until DSPI transfer complete */
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MCF_DSPI_DTFR = fifo;
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while (! (MCF_DSPI_DSR & MCF_DSPI_DSR_TCF)); /* wait until DSPI transfer complete */
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MCF_DSPI_DSR = 0xffffffff; /* clear DSPI status register */
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return * (volatile uint8_t *) (&MCF_DSPI_DRFR + 3);
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fifo = MCF_DSPI_DRFR;
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res = fifo & 0xff;
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return res;
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}
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@@ -154,10 +165,11 @@ static void xmit_spi_multi(const uint8_t *buff, uint32_t btx)
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static uint32_t card_ready(void)
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{
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static uint32_t counter = 0;
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uint8_t d;
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d = xchg_spi(0xff);
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return (d != 0xff);
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return (d == 0xff);
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}
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/*
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@@ -166,7 +178,7 @@ static uint32_t card_ready(void)
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* wt: timeout in ms
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* returns 1: ready, 0: timeout
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*/
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static int wait_ready (uint32_t wt)
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static int wait_ready(uint32_t wt)
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{
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return waitfor(wt, card_ready);
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}
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@@ -178,7 +190,7 @@ static int wait_ready (uint32_t wt)
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*/
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static void deselect(void)
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{
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MCF_DSPI_DTFR = MCF_DSPI_DTFR_EOQ | ~MCF_DSPI_DTFR_CS5;
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CS_HIGH();
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xchg_spi(0xFF); /* Dummy clock (force DO hi-z for multiple slave SPI) */
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MCF_DSPI_DSR = 0xffffffff; /* clear status register */
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}
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@@ -191,10 +203,12 @@ static void deselect(void)
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static int select(void) /* 1:OK, 0:Timeout */
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{
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MCF_DSPI_DTFR = MCF_DSPI_DTFR_EOQ | MCF_DSPI_DTFR_CS5;
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CS_LOW();
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xchg_spi(0xFF); /* Dummy clock (force DO enabled) */
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if (wait_ready(500)) return 1; /* OK */
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if (wait_ready(5000000))
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return 1; /* OK */
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deselect();
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return 0; /* Timeout */
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}
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@@ -204,28 +218,42 @@ static int select(void) /* 1:OK, 0:Timeout */
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/*
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* Control SPI module (Platform dependent)
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*/
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static void power_on (void) /* Enable SSP module and attach it to I/O pads */
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{
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spi_init();
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#ifdef _NOT_USED_
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__set_PCONP(PCSSPx, 1); /* Enable SSP module */
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__set_PCLKSEL(PCLKSSPx, PCLKDIV_SSP); /* Select PCLK frequency for SSP */
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SSPxCR0 = 0x0007; /* Set mode: SPI mode 0, 8-bit */
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SSPxCR1 = 0x2; /* Enable SSP with Master */
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#if SSP_CH == 0
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__set_PINSEL(0, 15, 2); /* Attach SCK0 to I/O pad */
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__set_PINSEL(0, 16, 2); /* Attach MISO0 to I/O pad */
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__set_PINSEL(0, 17, 2); /* Attach MOSI0 to I/O pad */
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FIO0DIR |= _BV(18)|_BV(17)|_BV(15); /* Set SCK0, MOSI0 and CS# as output */
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#elif SSP_CH == 1
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__set_PINSEL(0, 7, 2); /* Attach SCK1 to I/O pad */
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__set_PINSEL(0, 8, 2); /* Attach MISO1 to I/O pad */
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__set_PINSEL(0, 9, 2); /* Attach MOSI1 to I/O pad */
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FIO0DIR |= _BV(9)|_BV(7)|_BV(6); /* Set SCK1, MOSI1 and CS# as output */
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#endif
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MCF_PAD_PAR_DSPI = 0x1fff; /* configure all DSPI GPIO pins for DSPI usage */
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/*
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* FIXME: really necessary or just an oversight
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* that PAD_PAR_DSPI is only 16 bit?
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*/
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// MCF_PAD_PAR_TIMER = 0xff; leave off for now
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/*
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* initialize DSPI module configuration register
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*/
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MCF_DSPI_DMCR = MCF_DSPI_DMCR_MSTR | /* FireBee is DSPI master*/
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MCF_DSPI_DMCR_CSIS5 | /* CS5 inactive state high */
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MCF_DSPI_DMCR_CSIS3 | /* CS3 inactive state high */
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MCF_DSPI_DMCR_CSIS2 | /* CS2 inactive state high */
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MCF_DSPI_DMCR_DTXF | /* disable transmit FIFO */
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MCF_DSPI_DMCR_DRXF | /* disable receive FIFO */
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MCF_DSPI_DMCR_CTXF | /* clear transmit FIFO */
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MCF_DSPI_DMCR_CRXF; /* clear receive FIFO */
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/* initialize DSPI clock and transfer attributes register 0 */
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MCF_DSPI_DCTAR0 = MCF_DSPI_DCTAR_TRSZ(0b111) | /* transfer size = 8 bit */
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MCF_DSPI_DCTAR_PCSSCK(0b01) | /* 3 clock DSPICS to DSPISCK delay prescaler */
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MCF_DSPI_DCTAR_PASC_3CLK | /* 3 clock DSPISCK to DSPICS negation prescaler */
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MCF_DSPI_DCTAR_PDT_3CLK | /* 3 clock delay between DSPICS assertions prescaler */
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MCF_DSPI_DCTAR_PBR_3CLK | /* 3 clock prescaler */
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MCF_DSPI_DCTAR_ASC(0b1001) | /* 1024 */
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MCF_DSPI_DCTAR_DT(0b1001) | /* 1024 */
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MCF_DSPI_DCTAR_BR(0b0111);
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CS_HIGH(); /* Set CS# high */
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#endif /* _NOT_USED_ */
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/* card should now be initialized as MMC */
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wait(10 * 1000); /* 10ms */
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}
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