more Radeon work.
Get PLL info from BIOS emulator
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@@ -360,7 +360,6 @@ static int radeon_map_ROM(struct radeonfb_info *rinfo)
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temp = inreg(MPP_TB_CONFIG);
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dbg("temp=%d\r\n", temp);
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temp &= 0x00ffffffu;
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temp |= 0x04 << 24;
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OUTREG(MPP_TB_CONFIG, temp);
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@@ -1669,15 +1668,24 @@ int radeonfb_set_par(struct fb_info *info)
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struct radeonfb_info *rinfo = info->par;
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struct fb_var_screeninfo *mode = &info->var;
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struct radeon_regs *newmode;
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int hTotal, vTotal, hSyncStart, hSyncEnd, vSyncStart, vSyncEnd;
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int hTotal;
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int vTotal;
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int hSyncStart;
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int hSyncEnd;
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int vSyncStart;
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int vSyncEnd;
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// FIXME: int hSyncPol; this is not used anywhere
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// FIXME: int vSyncPol; this is not used anywhere
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// FIXME: int cSync; this is not used anywhere
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static uint8_t hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5};
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static uint8_t hsync_fudge_fp[] = {2, 2, 0, 0, 5, 5};
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uint32_t sync, h_sync_pol, v_sync_pol, dotClock, pixClock;
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static uint8_t hsync_adj_tab[] = { 0, 0x12, 9, 9, 6, 5 };
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static uint8_t hsync_fudge_fp[] = { 2, 2, 0, 0, 5, 5 };
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uint32_t sync;
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uint32_t h_sync_pol;
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uint32_t v_sync_pol;
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uint32_t dotClock;
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uint32_t pixClock;
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int i;
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int freq;
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int format = 0;
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@@ -1686,14 +1694,20 @@ int radeonfb_set_par(struct fb_info *info)
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int hsync_fudge;
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// int bytpp; FIXME: this doesn't seem to be used anywhere
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int hsync_wid, vsync_wid;
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int hsync_wid;
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int vsync_wid;
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int primary_mon = PRIMARY_MONITOR(rinfo);
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int depth = var_to_depth(mode);
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int use_rmx = 0;
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dbg("depth=%d\r\n", depth);
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newmode = (struct radeon_regs *) driver_mem_alloc(sizeof(struct radeon_regs));
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if (!newmode)
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return -1; //-ENOMEM;
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{
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err("driver_mem_alloc() failed (ret=%p)\r\n", newmode);
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return -1;
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}
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/*
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* We always want engine to be idle on a mode switch, even
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@@ -1701,6 +1715,8 @@ int radeonfb_set_par(struct fb_info *info)
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*/
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radeon_engine_idle();
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dbg("xres=%d yres=%d\r\n", mode->xres, mode->yres);
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hSyncStart = mode->xres + mode->right_margin;
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hSyncEnd = hSyncStart + mode->hsync_len;
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hTotal = hSyncEnd + mode->left_margin;
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@@ -1709,7 +1725,11 @@ int radeonfb_set_par(struct fb_info *info)
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vSyncEnd = vSyncStart + mode->vsync_len;
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vTotal = vSyncEnd + mode->upper_margin;
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dbg("pixel clock = %d\r\n", mode->pixclock);
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pixClock = mode->pixclock;
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dbg("sync = %d\r\n", mode->sync);
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sync = mode->sync;
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h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
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@@ -1746,6 +1766,9 @@ int radeonfb_set_par(struct fb_info *info)
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dotClock = 1000000000 / pixClock;
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freq = dotClock / 10; /* x100 */
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dbg("dotClock=%ld, freq = %ld\r\n", dotClock, freq);
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hsync_wid = (hSyncEnd - hSyncStart) / 8;
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if (hsync_wid == 0)
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@@ -1753,6 +1776,8 @@ int radeonfb_set_par(struct fb_info *info)
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else if (hsync_wid > 0x3f) /* max */
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hsync_wid = 0x3f;
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dbg("hsync_wid=%d\r\n", hsync_wid);
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if (mode->vmode & FB_VMODE_DOUBLE)
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{
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vSyncStart <<= 1;
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@@ -1766,18 +1791,21 @@ int radeonfb_set_par(struct fb_info *info)
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else if (vsync_wid > 0x1f) /* max */
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vsync_wid = 0x1f;
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dbg("vsync_wid=%d\r\n", vsync_wid);
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// FIXME: this doesn't seem to be used anywhere hSyncPol = mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
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// FIXME: this doesn't seem to be used anywhere vSyncPol = mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
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// FIXME: this doesn't seem to be used anywhere cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
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format = radeon_get_dstbpp(depth);
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dbg("format=%d\r\n", format);
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// FIXME: this doesn't seem to be used anywhere bytpp = mode->bits_per_pixel >> 3;
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if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD))
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hsync_fudge = hsync_fudge_fp[format-1];
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hsync_fudge = hsync_fudge_fp[format - 1];
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else
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hsync_fudge = hsync_adj_tab[format-1];
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hsync_fudge = hsync_adj_tab[format - 1];
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if (mode->vmode & FB_VMODE_DOUBLE)
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hsync_fudge = 0; /* todo: need adjust */
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@@ -1961,7 +1989,7 @@ int radeonfb_set_par(struct fb_info *info)
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}
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/* Update fix */
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info->fix.line_length = rinfo->pitch*64;
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info->fix.line_length = rinfo->pitch * 64;
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info->fix.visual = rinfo->depth == 8 ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
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driver_mem_free(newmode);
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