From 282c631601d518dbf335e1058c4abadad6ff16dd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 17 Aug 2014 08:43:43 +0000 Subject: [PATCH] added false_path to CLK_MAIN --- vhdl/backend/Altera/Firebee/firebee.sdc | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/vhdl/backend/Altera/Firebee/firebee.sdc b/vhdl/backend/Altera/Firebee/firebee.sdc index 19d1240..3aca7ce 100755 --- a/vhdl/backend/Altera/Firebee/firebee.sdc +++ b/vhdl/backend/Altera/Firebee/firebee.sdc @@ -835,9 +835,8 @@ set_output_delay -add_delay -max -clock [get_clocks {CLK_33M}] 5.000 [get_ports # Set False Path #************************************************************** -set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_re9:dffpipe19|dffe20a*}] -set_false_path -from [get_registers {*dcfifo*rdptr_g[*]}] -to [get_registers {*dcfifo*ws_dgrp*}] - +set_false_path -from [get_clocks {CLK_MAIN*wire_pll1_clk[0]}] -to [get_clocks {CLK_33M,altpll3:I_PLL3|altpll:altpll_component|altpll_66t2:auto_generated|clk[2],altpll4:I_PLL4|altpll:altpll_component|altpll4_altpll:auto_generated|wire_pll1_clk[0]}] +set_false_path -from [get_clocks {CLK_MAIN}] -to [get_clocks {CLK_MAIN}] #************************************************************** # Set Multicycle Path