diff --git a/BaS_gcc/sources/sysinit.c b/BaS_gcc/sources/sysinit.c
index 43ca3b9..349ce59 100644
--- a/BaS_gcc/sources/sysinit.c
+++ b/BaS_gcc/sources/sysinit.c
@@ -246,13 +246,44 @@ void init_ddram(void)
 	 */
 	if (!(MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)) {
 		/* Basic configuration and initialization */
+
+		/*
+		 * SB_E (Bits 9-8):  10	<=> 7.6 mA (SDCKE)
+		 * SB_C (Bits 7-6):	 10 <=> 7.6 mA (SDRAM Clocks)
+		 * SB_A (Bits 5-4):	 10 <=> 7.6 mA (RAS, CAS, SDWE, SDADDR[12:0], and SDBA)
+		 * SB_S (Bits 3-2):  10 <=> 7.6 mA (SDRDQS)
+		 * SB_D (Bits 1-0):	 10 <=> 7.6 mA (SDRDQS)
+		 *
+		 * -> lowest setting the Coldfire SDRAM controller allows
+		 */
 		MCF_SDRAMC_SDRAMDS = 0x000002AA;/* SDRAMDS configuration */
+
 		MCF_SDRAMC_CS0CFG = 0x0000001A;	/* SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF) */
 		MCF_SDRAMC_CS1CFG = 0x0800001A;	/* SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF) */
 		MCF_SDRAMC_CS2CFG = 0x1000001A;	/* SDRAM CS2 configuration (128Mbytes 1000_0000 - 07FF_FFFF) */
 		MCF_SDRAMC_CS3CFG = 0x1800001A;	/* SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF) */
+
+		/*
+		 *
+		 */
+		MCF_SDRAMC_SDCFG1 = MCF_SDRAMC_SDCFG1_WTLAT(3)	/* Write latency */
+				| MCF_SDRAMC_SDCFG1_REF2ACT(8)			/* Refresh to Active Delay */
+				| MCF_SDRAMC_SDCFG1_PRE2ACT(2)			/* Precharge to Active Delay */
+				| MCF_SDRAMC_SDCFG1_ACT2RW(2)			/* Active to Read/Write Delay */
+				| MCF_SDRAMC_SDCFG1_RDLAT(6)			/* Read CAS latency */
+				| MCF_SDRAMC_SDCFG1_SWT2RD(3)			/* Single Write to Read/Write/Precharge delay */
+				| MCF_SDRAMC_SDCFG1_SRD2RW(7);			/* Single Read to Read/Write/Precharge delay */
+
+		MCF_SDRAMC_SDCFG2 = MCF_SDRAMC_SDCFG2_BL(7)		/* Burst Length */
+				| MCF_SDRAMC_SDCFG2_BRD2WT(7)			/* Burst Read to Write delay */
+				| MCF_SDRAMC_SDCFG2_BWT2RW(6)			/* Burst Write to Read/Write/Precharge delay */
+				| MCF_SDRAMC_SDCFG2_BRD2PRE(4);			/* Burst Read to Read/Precharge delay */
+
+#ifdef _NOT_USED_
 		MCF_SDRAMC_SDCFG1 = 0x73622830;	/* SDCFG1 */
 		MCF_SDRAMC_SDCFG2 = 0x46770000;	/* SDCFG2 */
+#endif /* _NOT_USED_ */
+
 		MCF_SDRAMC_SDCR = 0xE10D0002;	/* SDCR + IPALL */
 		MCF_SDRAMC_SDMR = 0x40010000;	/* SDMR (write to LEMR) */
 		MCF_SDRAMC_SDMR = 0x048D0000;	/* SDRM (write to LMR) */