further extended testbench.
Need to fix difference between clock ticks and TIME in original code
This commit is contained in:
Markus Fröschle
@@ -1,26 +1,11 @@
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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LIBRARY work;
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PACKAGE ddr2_ram_model_pkg IS
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CONSTANT DM_BITS : INTEGER := 2;
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CONSTANT BA_BITS : INTEGER := 2;
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CONSTANT MEM_BITS : INTEGER := 10; -- number of write data bursts can be stored in memory. The default is 2 ** 10 = 1024
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CONSTANT AP : INTEGER := 10; -- the address bit that controls auto-precharge and precharge-all
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CONSTANT ADDR_BITS : INTEGER := 13;
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CONSTANT DQ_BITS : INTEGER := 2;
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CONSTANT DQS_BITS : INTEGER := 2;
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CONSTANT TDLLK : INTEGER := 200;
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CONSTANT BUS_DELAY : TIME := 0 ps;
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CONSTANT BANKS : INTEGER := TO_INTEGER(SHIFT_LEFT(TO_UNSIGNED(1, 32), BA_BITS));
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CONSTANT ROW_BITS : INTEGER := 13;
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CONSTANT COL_BITS : INTEGER := 10;
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CONSTANT BL_BITS : INTEGER := 3; -- the number of bits required to count to MAX_BL
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CONSTANT BL_MAX : INTEGER := 8;
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CONSTANT BO_BITS : INTEGER := 2; -- the number of burst order bits
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CONSTANT MAX_BITS : INTEGER := BA_BITS + ROW_BITS + COL_BITS - BL_BITS;
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-- DDR2 RAM timing constants
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CONSTANT TMRD : TIME := 2 ps; -- load mode register command cycle time
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CONSTANT TRFC_MIN : TIME := 105000 ps; -- refresh to refresh command minimum value
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@@ -31,36 +16,38 @@ PACKAGE ddr2_ram_model_pkg IS
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CONSTANT TRAS_MIN : TIME := 40000 ps; -- minimum active to precharge command time
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CONSTANT TRAS_MAX : TIME := 70000000 ps; -- maximum active to precharge command time
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CONSTANT TRRD : TIME := 10000 ps; -- tRRD: active bank to active bank command time
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CONSTANT TFAW : INTEGER := 45000;
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CONSTANT RANDOM_SEED : INTEGER := 711689044; -- seed value for random generator
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COMPONENT ddr2_ram_model IS
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GENERIC
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(
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DEBUG : STD_LOGIC := '1';
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DM_BITS : INTEGER := 2;
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BA_BITS : INTEGER := 2;
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ADDR_BITS : INTEGER := 13;
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DQ_BITS : INTEGER := 2;
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DQS_BITS : INTEGER := 2
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VERBOSE : BOOLEAN := TRUE; -- define if you want additional debug output
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BA_BITS : INTEGER := 2; -- number of banks
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ADDR_BITS : INTEGER := 13; -- number of address bits
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DM_BITS : INTEGER := 2; -- number of data mask bits
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DQ_BITS : INTEGER := 16; -- number of data bits
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DQS_BITS : INTEGER := 2 -- number of data strobes
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);
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PORT
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(
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ck : IN STD_LOGIC;
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ck_n : IN STD_LOGIC;
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cke : IN STD_LOGIC;
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cs_n : IN STD_LOGIC;
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ras_n : IN STD_LOGIC;
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cas_n : IN STD_LOGIC;
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we_n : IN STD_LOGIC;
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dm_rdqs : INOUT STD_LOGIC_VECTOR (DM_BITS - 1 DOWNTO 0);
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ba : IN STD_LOGIC_VECTOR (BA_BITS - 1 DOWNTO 0);
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addr : IN STD_LOGIC_VECTOR (ADDR_BITS - 1 DOWNTO 0);
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dq : INOUT STD_LOGIC_VECTOR (DQ_BITS - 1 DOWNTO 0);
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dqs : INOUT STD_LOGIC_VECTOR (DQS_BITS - 1 DOWNTO 0);
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dqs_n : INOUT STD_LOGIC_VECTOR (DQS_BITS - 1 DOWNTO 0);
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rdqs_n : OUT STD_LOGIC_VECTOR (DQS_BITS - 1 DOWNTO 0);
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odt : IN STD_LOGIC
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ck : IN STD_LOGIC;
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ck_n : IN STD_LOGIC;
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cke : IN STD_LOGIC;
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cs_n : IN STD_LOGIC;
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ras_n : IN STD_LOGIC;
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cas_n : IN STD_LOGIC;
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we_n : IN STD_LOGIC;
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dm_rdqs : INOUT STD_LOGIC_VECTOR (DM_BITS - 1 DOWNTO 0);
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ba : IN STD_LOGIC_VECTOR (BA_BITS - 1 DOWNTO 0);
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addr : IN STD_LOGIC_VECTOR (ADDR_BITS - 1 DOWNTO 0);
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dq : INOUT STD_LOGIC_VECTOR (DQ_BITS - 1 DOWNTO 0);
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dqs : INOUT STD_LOGIC_VECTOR (DQS_BITS - 1 DOWNTO 0);
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dqs_n : INOUT STD_LOGIC_VECTOR (DQS_BITS - 1 DOWNTO 0);
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rdqs_n : OUT STD_LOGIC_VECTOR (DQS_BITS - 1 DOWNTO 0);
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odt : IN STD_LOGIC
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);
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END COMPONENT;
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END PACKAGE;
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@@ -71,8 +58,8 @@ END PACKAGE BODY ddr2_ram_model_pkg;
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---------------------------------------------------------------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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LIBRARY work;
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USE work.ddr2_ram_model_pkg.ALL;
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@@ -80,12 +67,13 @@ LIBRARY work;
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ENTITY ddr2_ram_model IS
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GENERIC
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(
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DEBUG : STD_LOGIC := '1';
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BA_BITS : INTEGER := 2;
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ADDR_BITS : INTEGER := 13;
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DM_BITS : INTEGER := 2;
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DQ_BITS : INTEGER := 16;
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DQS_BITS : INTEGER := 2
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VERBOSE : BOOLEAN := TRUE; -- define if you want additional debug output
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BA_BITS : INTEGER := 2; -- number of banks
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ADDR_BITS : INTEGER := 13; -- number of address bits
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DM_BITS : INTEGER := 2; -- number of data mask bits
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DQ_BITS : INTEGER := 8; -- number of data bits
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DQS_BITS : INTEGER := 2 -- number of data strobes
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);
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PORT
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(
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@@ -108,14 +96,26 @@ ENTITY ddr2_ram_model IS
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END ENTITY ddr2_ram_model;
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ARCHITECTURE rtl OF ddr2_ram_model IS
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-- DDR2 RAM size constants
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CONSTANT MEM_BITS : INTEGER := 10; -- number of write data bursts can be stored in memory. The default is 2 ** 10 = 1024
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CONSTANT AP : INTEGER := 10; -- the address bit that controls auto-precharge and precharge-all
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CONSTANT TDLLK : INTEGER := 200;
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CONSTANT BUS_DELAY : TIME := 0 ps;
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CONSTANT BANKS : INTEGER := TO_INTEGER(SHIFT_LEFT(TO_UNSIGNED(1, 32), BA_BITS));
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CONSTANT ROW_BITS : INTEGER := 13;
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CONSTANT COL_BITS : INTEGER := 10;
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CONSTANT BL_BITS : INTEGER := 3; -- the number of bits required to count to MAX_BL
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CONSTANT BL_MAX : INTEGER := 8;
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CONSTANT BO_BITS : INTEGER := 2; -- the number of burst order bits
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CONSTANT MAX_BITS : INTEGER := BA_BITS + ROW_BITS + COL_BITS - BL_BITS;
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CONSTANT DQ_PER_DQS : INTEGER := DQ_BITS / DQS_BITS;
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CONSTANT MAX_SIZE : INTEGER := TO_INTEGER(SHIFT_LEFT(TO_UNSIGNED(1, 32), BA_BITS + ROW_BITS + COL_BITS - BL_BITS));
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CONSTANT MEM_SIZE : INTEGER := TO_INTEGER(SHIFT_LEFT(TO_UNSIGNED(1, 32), MEM_BITS));
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CONSTANT AL_MAX : INTEGER := 6;
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CONSTANT CL_MAX : INTEGER := 7;
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CONSTANT MAX_PIPE : INTEGER := 2 * (AL_MAX + CL_MAX);
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CONSTANT TFAW : INTEGER := 45000;
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CONSTANT TDLLK : INTEGER := 200;
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TYPE time_array_t IS ARRAY (NATURAL RANGE <>) OF TIME;
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@@ -163,7 +163,7 @@ ARCHITECTURE rtl OF ddr2_ram_model IS
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SIGNAL read_latency : INTEGER;
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SIGNAL write_latency : INTEGER;
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TYPE cmd_type_t IS (LOAD_MODE, REFRESH, PRECHARGE, ACTIVATE, WRITE, READ, NOP, PWR_DOWN, SELF_REF);
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TYPE cmd_type_t IS (LOAD_MODE, REFRESH, PRECHARGE, ACTIVATE, WRITE_CMD, READ, NOP, PWR_DOWN, SELF_REF);
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TYPE cmd_type_encoding_array_t IS ARRAY(cmd_type_t) OF STD_LOGIC_VECTOR(3 DOWNTO 0);
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CONSTANT cmd_type_encoding : cmd_type_encoding_array_t :=
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(
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@@ -204,7 +204,7 @@ ARCHITECTURE rtl OF ddr2_ram_model IS
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-- cmd timers/counters
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SIGNAL ref_cntr : INTEGER;
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SIGNAL ck_cntr : TIME;
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SIGNAL ck_cntr : INTEGER;
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SIGNAL ck_load_mode : TIME;
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SIGNAL ck_write : INTEGER;
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SIGNAL ck_read : INTEGER;
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@@ -552,7 +552,7 @@ BEGIN
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REPORT("ERROR: 2**BO_BITS cannot be greater than BL_MAX parameter");
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END IF;
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seed <= RANDOM_SEED;
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ck_cntr <= 0 ps;
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ck_cntr <= 0;
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WAIT;
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END PROCESS;
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@@ -634,7 +634,7 @@ BEGIN
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END PROCESS; -- reset
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err : PROCESS
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PROCEDURE chk_err (
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PROCEDURE chk_err(
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samebank : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
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bank : IN STD_LOGIC_VECTOR (BA_BITS - 1 DOWNTO 0);
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fromcmd : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
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@@ -649,21 +649,27 @@ BEGIN
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WHEN "1" & cmd_type_encoding(LOAD_MODE) & "0---" =>
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IF ck_cntr - ck_load_mode < TMRD THEN
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REPORT("at time " & TIME'IMAGE(NOW) & " ERROR: tMRD violation during " & cmd_string(TO_INTEGER(UNSIGNED(cmd))));
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END IF;
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END IF;
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WHEN "1" & cmd_type_encoding(LOAD_MODE) & "100-" =>
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IF ck_cntr - ck_load_mode < TMRD THEN
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REPORT("at time " & TIME'IMAGE(NOW) & " INFO: Load Mode to Reset Condition");
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END IF;
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WHEN "1" & cmd_type_encoding(REFRESH) & "0---" =>
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IF NOW - tm_refresh < TRFC_MIN THEN
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REPORT("tRFC violation during " & cmd_string(TO_INTEGER(UNSIGNED(cmd))));
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END IF;
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WHEN "1" & cmd_type_encoding(REFRESH) & cmd_type_encoding(PWR_DOWN) => -- 1 tCK_avg
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WHEN "1" & cmd_type_encoding(REFRESH) & cmd_type_encoding(PWR_DOWN) =>
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-- 1 tCK_avg
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WHEN "1" & cmd_type_encoding(REFRESH) & cmd_type_encoding(SELF_REF) =>
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IF NOW - tm_refresh < TRFC_MIN THEN
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REPORT("at time " & TIME'IMAGE(NOW) & "INFO: Refresh to Reset condition");
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END IF;
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init_done <= '0';
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WHEN "1" & cmd_type_encoding(PRECHARGE) & "000-" =>
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IF NOW - tm_precharge_all < TRPA THEN
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REPORT("at time " & TIME'IMAGE(NOW) & " ERROR: tRPA violation during " & cmd_string(TO_INTEGER(UNSIGNED(cmd))));
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@@ -671,14 +677,16 @@ BEGIN
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IF NOW - tm_precharge < TRP THEN
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REPORT("at time " & TIME'IMAGE(NOW) & " ERROR: tRP violation during " & cmd_string(TO_INTEGER(UNSIGNED(cmd))));
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END IF;
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WHEN "1" & cmd_type_encoding(PRECHARGE) & cmd_type_encoding(PRECHARGE) =>
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IF DEBUG = '1' AND NOW - tm_precharge_all < TRPA THEN
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IF VERBOSE = TRUE AND NOW - tm_precharge_all < TRPA THEN
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REPORT("at time " & TIME'IMAGE(NOW) & " INFO: Precharge All interruption during " & cmd_string(TO_INTEGER(UNSIGNED(cmd))));
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END IF;
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IF DEBUG = '1' AND NOW - tm_bank_precharge(TO_INTEGER(UNSIGNED(bank))) < TRP THEN
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IF VERBOSE = TRUE AND NOW - tm_bank_precharge(TO_INTEGER(UNSIGNED(bank))) < TRP THEN
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REPORT("at time " & TIME'IMAGE(NOW) & " INFO: Precharge Bank " & INTEGER'IMAGE(TO_INTEGER(UNSIGNED(bank))) & " interruption during "
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& cmd_string(TO_INTEGER(UNSIGNED(cmd))));
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END IF;
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WHEN "1" & cmd_type_encoding(PRECHARGE) & cmd_type_encoding(ACTIVATE) =>
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IF NOW - tm_precharge_all < TRPA THEN
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REPORT("at time " & TIME'IMAGE(NOW) & " ERROR: tRPA violation during " & cmd_string(TO_INTEGER(UNSIGNED(cmd))));
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@@ -687,17 +695,21 @@ BEGIN
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REPORT("at time " & TIME'IMAGE(NOW) & " tRP violation during " & cmd_string(TO_INTEGER(UNSIGNED(cmd))) & " to bank "
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& INTEGER'IMAGE(TO_INTEGER(UNSIGNED(bank))));
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END IF;
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WHEN "1" & cmd_type_encoding(PRECHARGE) & cmd_type_encoding(PWR_DOWN) =>
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-- 1 tCK, can be concurrent with auto precharge
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WHEN "1" & cmd_type_encoding(PRECHARGE) & cmd_type_encoding(SELF_REF) =>
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IF NOW - tm_precharge_all < TRPA OR NOW - tm_precharge < TRP THEN
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REPORT("at time " & TIME'IMAGE(NOW) & " INFO: Precharge to reset condition");
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init_done <= '0';
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END IF;
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WHEN "1" & cmd_type_encoding(ACTIVATE) & cmd_type_encoding(REFRESH) =>
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IF NOW - tm_activate < TRC THEN
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REPORT("at time " & TIME'IMAGE(NOW) & " ERROR: tRC violation during " & cmd_string(TO_INTEGER(UNSIGNED(cmd))));
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END IF;
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WHEN "1" & cmd_type_encoding(ACTIVATE) & cmd_type_encoding(PRECHARGE) =>
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IF NOW - tm_bank_activate(TO_INTEGER(UNSIGNED(bank))) > TRAS_MAX AND active_bank(TO_INTEGER(UNSIGNED(bank))) = '1' THEN
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REPORT("at time " & TIME'IMAGE(NOW) & " ERROR: tRAS maximum violation during " & cmd_string(TO_INTEGER(UNSIGNED(cmd))) &
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@@ -707,12 +719,46 @@ BEGIN
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REPORT("at time " & TIME'IMAGE(NOW) & " ERROR: tRAS minimum violation during " & cmd_string(TO_INTEGER(UNSIGNED(cmd))) &
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" to bank " & INTEGER'IMAGE(TO_INTEGER(UNSIGNED(bank))));
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END IF;
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WHEN "1" & cmd_type_encoding(ACTIVATE) & cmd_type_encoding(ACTIVATE) =>
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IF NOW - tm_activate < TRRD THEN
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REPORT("at time " & TIME'IMAGE(NOW) & " ERROR: tRRD violation during " & cmd_string(TO_INTEGER(UNSIGNED(cmd))) &
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" to bank " & INTEGER'IMAGE(TO_INTEGER(UNSIGNED(bank))));
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END IF;
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WHEN "1" & cmd_type_encoding(ACTIVATE) & cmd_type_encoding(ACTIVATE) =>
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IF NOW - tm_bank_activate(TO_INTEGER(UNSIGNED(bank))) < TRC THEN
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REPORT("at time " & TIME'IMAGE(NOW) & " ERROR: tRC violation during " & cmd_string(TO_INTEGER(UNSIGNED(cmd))) & " to bank " &
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INTEGER'IMAGE(TO_INTEGER(UNSIGNED(bank))));
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END IF;
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WHEN "1" & cmd_type_encoding(ACTIVATE) & "010-" =>
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-- tRCD is checked outside this task
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WHEN "1" & cmd_type_encoding(ACTIVATE) & cmd_type_encoding(PWR_DOWN) =>
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-- 1 tCK
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WHEN "1" & cmd_type_encoding(WRITE_CMD) & cmd_type_encoding(PRECHARGE) =>
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IF ck_cntr - ck_bank_write(TO_INTEGER(UNSIGNED(bank)))
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<= write_latency + TO_INTEGER(UNSIGNED(burst_length)) + 2 OR
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NOW - tm_bank_write_end(TO_INTEGER(UNSIGNED(bank))) < TWR THEN
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REPORT("at time " & TIME'IMAGE(NOW) & " ERROR: tWR violation during " & cmd_string(TO_INTEGER(UNSIGNED(cmd))) & " to bank " & INTEGER'IMAGE(TO_INTEGER(UNSIGNED(bank))));
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END IF;
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WHEN "1" & cmd_type_enconding(WRITE_CMD) & cmd_type_encoding(WRITE_CMD) =>
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IF ck_cntr - ck_write < TCCD THEN
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REPORT("at time " & TIME'IMAGE(NOW) & " ERROR: tCCD violation during " & cmd_string(TO_INTEGER(UNSIGNED(cmd))) & " to bank " & INTEGER'IMAGE(TO_INTEGER(bank)));
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END IF;
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WHEN "1" & cmd_type_encoding(WRITE_CMD) & cmd_type_encoding(READ) =>
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IF ck_load_mode < ck_write AND ck_cntr - ck_write < write_latency + burst_length / 2 + 2 - additive_latency THEN
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REPORT("at time " & TIME'IMAGE(NOW) & " ERROR: tWTR violation during " & cmd_string(TO_INTEGER(UNSIGNED(cmd))) & " to bank " & INTEGER'IMAGE(TO_INTEGER(bank)));
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END IF;
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WHEN "1" & cmd_type_encoding(WRITE_CMD) & cmd_type_encoding(PWR_DOWN) =>
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WHEN OTHERS => -- do nothing
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END CASE?;
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END;
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BEGIN
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Block a user