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XL bus master priorities were the wrong way round

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This commit is contained in:
Markus Fröschle
2013-11-13 12:46:00 +00:00
parent d1bdb72005
commit 16ff2be32f
1 changed files with 3 additions and 3 deletions
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6
BaS_gcc/sources/pci.c
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@@ -693,7 +693,7 @@ void init_xlbus_arbiter(void)
MCF_XLB_XARB_BUSTO = 0xffffff; MCF_XLB_XARB_BUSTO = 0xffffff;
/* /*
* set arbitration priorities for XLBUS masters * set arbitration priorities for XL bus masters
* *
* M0 = ColdFire core * M0 = ColdFire core
* M2 = Multichannel DMA * M2 = Multichannel DMA
@@ -703,9 +703,9 @@ void init_xlbus_arbiter(void)
MCF_XLB_XARB_PRIEN = MCF_XLB_XARB_PRIEN_M0 | /* activate programmed priority for Coldfire core */ MCF_XLB_XARB_PRIEN = MCF_XLB_XARB_PRIEN_M0 | /* activate programmed priority for Coldfire core */
MCF_XLB_XARB_PRIEN_M2 | /* activate programmed priority for Multichannel DMA */ MCF_XLB_XARB_PRIEN_M2 | /* activate programmed priority for Multichannel DMA */
MCF_XLB_XARB_PRIEN_M3; /* activate programmed priority for PCI target interface */ MCF_XLB_XARB_PRIEN_M3; /* activate programmed priority for PCI target interface */
MCF_XLB_XARB_PRI = MCF_XLB_XARB_PRI_M0P(3) | /* Coldfire core gets lowest */ MCF_XLB_XARB_PRI = MCF_XLB_XARB_PRI_M0P(7) | /* Coldfire core gets lowest */
MCF_XLB_XARB_PRI_M2P(5) | /* Multichannel DMA mid priority */ MCF_XLB_XARB_PRI_M2P(5) | /* Multichannel DMA mid priority */
MCF_XLB_XARB_PRI_M3P(7); /* PCI target interface is highest priority */ MCF_XLB_XARB_PRI_M3P(3); /* PCI target interface is highest priority */
} }