disable most of the debug output
This commit is contained in:
Markus Fröschle
@@ -12,7 +12,7 @@
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#define FBIOPUT_VSCREENINFO 0x4601
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#define FBIOGET_FSCREENINFO 0x4602
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#define FBIOPAN_DISPLAY 0x4606
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#define FBIOBLANK 0x4611 /* arg: 0 or vesa level + 1 */
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#define FBIOBLANK 0x4611 /* arg: 0 or vesa level + 1 */
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#define FBIO_ALLOC 0x4613
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#define FBIO_FREE 0x4614
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@@ -77,103 +77,104 @@ struct mode_option {
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extern struct mode_option resolution; /* fVDI */
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#define FB_TYPE_PACKED_PIXELS 0 /* Packed Pixels */
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#define FB_TYPE_PLANES 1 /* Non interleaved planes */
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#define FB_TYPE_INTERLEAVED_PLANES 2 /* Interleaved planes */
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#define FB_TYPE_TEXT 3 /* Text/attributes */
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#define FB_TYPE_VGA_PLANES 4 /* EGA/VGA planes */
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#define FB_TYPE_PACKED_PIXELS 0 /* Packed Pixels */
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#define FB_TYPE_PLANES 1 /* Non interleaved planes */
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#define FB_TYPE_INTERLEAVED_PLANES 2 /* Interleaved planes */
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#define FB_TYPE_TEXT 3 /* Text/attributes */
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#define FB_TYPE_VGA_PLANES 4 /* EGA/VGA planes */
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#define FB_AUX_TEXT_MDA 0 /* Monochrome text */
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#define FB_AUX_TEXT_CGA 1 /* CGA/EGA/VGA Color text */
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#define FB_AUX_TEXT_S3_MMIO 2 /* S3 MMIO fasttext */
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#define FB_AUX_TEXT_MGA_STEP16 3 /* MGA Millenium I: text, attr, 14 reserved bytes */
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#define FB_AUX_TEXT_MGA_STEP8 4 /* other MGAs: text, attr, 6 reserved bytes */
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#define FB_AUX_TEXT_MDA 0 /* Monochrome text */
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#define FB_AUX_TEXT_CGA 1 /* CGA/EGA/VGA Color text */
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#define FB_AUX_TEXT_S3_MMIO 2 /* S3 MMIO fasttext */
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#define FB_AUX_TEXT_MGA_STEP16 3 /* MGA Millenium I: text, attr, 14 reserved bytes */
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#define FB_AUX_TEXT_MGA_STEP8 4 /* other MGAs: text, attr, 6 reserved bytes */
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#define FB_AUX_VGA_PLANES_VGA4 0 /* 16 color planes (EGA/VGA) */
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#define FB_AUX_VGA_PLANES_CFB4 1 /* CFB4 in planes (VGA) */
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#define FB_AUX_VGA_PLANES_CFB8 2 /* CFB8 in planes (VGA) */
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#define FB_AUX_VGA_PLANES_VGA4 0 /* 16 color planes (EGA/VGA) */
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#define FB_AUX_VGA_PLANES_CFB4 1 /* CFB4 in planes (VGA) */
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#define FB_AUX_VGA_PLANES_CFB8 2 /* CFB8 in planes (VGA) */
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#define FB_VISUAL_MONO01 0 /* Monochr. 1=Black 0=White */
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#define FB_VISUAL_MONO10 1 /* Monochr. 1=White 0=Black */
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#define FB_VISUAL_TRUECOLOR 2 /* True color */
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#define FB_VISUAL_PSEUDOCOLOR 3 /* Pseudo color (like atari) */
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#define FB_VISUAL_DIRECTCOLOR 4 /* Direct color */
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#define FB_VISUAL_STATIC_PSEUDOCOLOR 5 /* Pseudo color readonly */
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#define FB_VISUAL_MONO01 0 /* Monochr. 1=Black 0=White */
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#define FB_VISUAL_MONO10 1 /* Monochr. 1=White 0=Black */
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#define FB_VISUAL_TRUECOLOR 2 /* True color */
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#define FB_VISUAL_PSEUDOCOLOR 3 /* Pseudo color (like atari) */
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#define FB_VISUAL_DIRECTCOLOR 4 /* Direct color */
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#define FB_VISUAL_STATIC_PSEUDOCOLOR 5 /* Pseudo color readonly */
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#define FB_ACCEL_NONE 0 /* no hardware accelerator */
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#define FB_ACCEL_ATARIBLITT 1 /* Atari Blitter */
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#define FB_ACCEL_AMIGABLITT 2 /* Amiga Blitter */
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#define FB_ACCEL_S3_TRIO64 3 /* Cybervision64 (S3 Trio64) */
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#define FB_ACCEL_NCR_77C32BLT 4 /* RetinaZ3 (NCR 77C32BLT) */
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#define FB_ACCEL_S3_VIRGE 5 /* Cybervision64/3D (S3 ViRGE) */
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#define FB_ACCEL_ATI_MACH64GX 6 /* ATI Mach 64GX family */
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#define FB_ACCEL_DEC_TGA 7 /* DEC 21030 TGA */
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#define FB_ACCEL_ATI_MACH64CT 8 /* ATI Mach 64CT family */
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#define FB_ACCEL_ATI_MACH64VT 9 /* ATI Mach 64CT family VT class */
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#define FB_ACCEL_ATI_MACH64GT 10 /* ATI Mach 64CT family GT class */
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#define FB_ACCEL_SUN_CREATOR 11 /* Sun Creator/Creator3D */
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#define FB_ACCEL_SUN_CGSIX 12 /* Sun cg6 */
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#define FB_ACCEL_SUN_LEO 13 /* Sun leo/zx */
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#define FB_ACCEL_IMS_TWINTURBO 14 /* IMS Twin Turbo */
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#define FB_ACCEL_3DLABS_PERMEDIA2 15 /* 3Dlabs Permedia 2 */
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#define FB_ACCEL_MATROX_MGA2064W 16 /* Matrox MGA2064W (Millenium) */
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#define FB_ACCEL_MATROX_MGA1064SG 17 /* Matrox MGA1064SG (Mystique) */
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#define FB_ACCEL_MATROX_MGA2164W 18 /* Matrox MGA2164W (Millenium II) */
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#define FB_ACCEL_MATROX_MGA2164W_AGP 19 /* Matrox MGA2164W (Millenium II) */
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#define FB_ACCEL_MATROX_MGAG100 20 /* Matrox G100 (Productiva G100) */
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#define FB_ACCEL_MATROX_MGAG200 21 /* Matrox G200 (Myst, Mill, ...) */
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#define FB_ACCEL_SUN_CG14 22 /* Sun cgfourteen */
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#define FB_ACCEL_SUN_BWTWO 23 /* Sun bwtwo */
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#define FB_ACCEL_SUN_CGTHREE 24 /* Sun cgthree */
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#define FB_ACCEL_SUN_TCX 25 /* Sun tcx */
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#define FB_ACCEL_MATROX_MGAG400 26 /* Matrox G400 */
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#define FB_ACCEL_NV3 27 /* nVidia RIVA 128 */
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#define FB_ACCEL_NV4 28 /* nVidia RIVA TNT */
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#define FB_ACCEL_NV5 29 /* nVidia RIVA TNT2 */
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#define FB_ACCEL_CT_6555x 30 /* C&T 6555x */
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#define FB_ACCEL_3DFX_BANSHEE 31 /* 3Dfx Banshee */
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#define FB_ACCEL_ATI_RAGE128 32 /* ATI Rage128 family */
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#define FB_ACCEL_IGS_CYBER2000 33 /* CyberPro 2000 */
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#define FB_ACCEL_IGS_CYBER2010 34 /* CyberPro 2010 */
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#define FB_ACCEL_IGS_CYBER5000 35 /* CyberPro 5000 */
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#define FB_ACCEL_SIS_GLAMOUR 36 /* SiS 300/630/540 */
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#define FB_ACCEL_3DLABS_PERMEDIA3 37 /* 3Dlabs Permedia 3 */
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#define FB_ACCEL_ATI_RADEON 38 /* ATI Radeon family */
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#define FB_ACCEL_I810 39 /* Intel 810/815 */
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#define FB_ACCEL_SIS_GLAMOUR_2 40 /* SiS 315, 650, 740 */
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#define FB_ACCEL_SIS_XABRE 41 /* SiS 330 ("Xabre") */
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#define FB_ACCEL_I830 42 /* Intel 830M/845G/85x/865G */
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#define FB_ACCEL_NV_10 43 /* nVidia Arch 10 */
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#define FB_ACCEL_NV_20 44 /* nVidia Arch 20 */
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#define FB_ACCEL_NV_30 45 /* nVidia Arch 30 */
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#define FB_ACCEL_NV_40 46 /* nVidia Arch 40 */
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#define FB_ACCEL_NEOMAGIC_NM2070 90 /* NeoMagic NM2070 */
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#define FB_ACCEL_NEOMAGIC_NM2090 91 /* NeoMagic NM2090 */
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#define FB_ACCEL_NEOMAGIC_NM2093 92 /* NeoMagic NM2093 */
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#define FB_ACCEL_NEOMAGIC_NM2097 93 /* NeoMagic NM2097 */
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#define FB_ACCEL_NEOMAGIC_NM2160 94 /* NeoMagic NM2160 */
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#define FB_ACCEL_NEOMAGIC_NM2200 95 /* NeoMagic NM2200 */
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#define FB_ACCEL_NEOMAGIC_NM2230 96 /* NeoMagic NM2230 */
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#define FB_ACCEL_NEOMAGIC_NM2360 97 /* NeoMagic NM2360 */
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#define FB_ACCEL_NEOMAGIC_NM2380 98 /* NeoMagic NM2380 */
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#define FB_ACCEL_NONE 0 /* no hardware accelerator */
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#define FB_ACCEL_ATARIBLITT 1 /* Atari Blitter */
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#define FB_ACCEL_AMIGABLITT 2 /* Amiga Blitter */
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#define FB_ACCEL_S3_TRIO64 3 /* Cybervision64 (S3 Trio64) */
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#define FB_ACCEL_NCR_77C32BLT 4 /* RetinaZ3 (NCR 77C32BLT) */
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#define FB_ACCEL_S3_VIRGE 5 /* Cybervision64/3D (S3 ViRGE) */
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#define FB_ACCEL_ATI_MACH64GX 6 /* ATI Mach 64GX family */
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#define FB_ACCEL_DEC_TGA 7 /* DEC 21030 TGA */
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#define FB_ACCEL_ATI_MACH64CT 8 /* ATI Mach 64CT family */
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#define FB_ACCEL_ATI_MACH64VT 9 /* ATI Mach 64CT family VT class */
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#define FB_ACCEL_ATI_MACH64GT 10 /* ATI Mach 64CT family GT class */
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#define FB_ACCEL_SUN_CREATOR 11 /* Sun Creator/Creator3D */
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#define FB_ACCEL_SUN_CGSIX 12 /* Sun cg6 */
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#define FB_ACCEL_SUN_LEO 13 /* Sun leo/zx */
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#define FB_ACCEL_IMS_TWINTURBO 14 /* IMS Twin Turbo */
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#define FB_ACCEL_3DLABS_PERMEDIA2 15 /* 3Dlabs Permedia 2 */
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#define FB_ACCEL_MATROX_MGA2064W 16 /* Matrox MGA2064W (Millenium) */
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#define FB_ACCEL_MATROX_MGA1064SG 17 /* Matrox MGA1064SG (Mystique) */
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#define FB_ACCEL_MATROX_MGA2164W 18 /* Matrox MGA2164W (Millenium II) */
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#define FB_ACCEL_MATROX_MGA2164W_AGP 19 /* Matrox MGA2164W (Millenium II) */
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#define FB_ACCEL_MATROX_MGAG100 20 /* Matrox G100 (Productiva G100) */
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#define FB_ACCEL_MATROX_MGAG200 21 /* Matrox G200 (Myst, Mill, ...) */
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#define FB_ACCEL_SUN_CG14 22 /* Sun cgfourteen */
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#define FB_ACCEL_SUN_BWTWO 23 /* Sun bwtwo */
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#define FB_ACCEL_SUN_CGTHREE 24 /* Sun cgthree */
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#define FB_ACCEL_SUN_TCX 25 /* Sun tcx */
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#define FB_ACCEL_MATROX_MGAG400 26 /* Matrox G400 */
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#define FB_ACCEL_NV3 27 /* nVidia RIVA 128 */
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#define FB_ACCEL_NV4 28 /* nVidia RIVA TNT */
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#define FB_ACCEL_NV5 29 /* nVidia RIVA TNT2 */
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#define FB_ACCEL_CT_6555x 30 /* C&T 6555x */
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#define FB_ACCEL_3DFX_BANSHEE 31 /* 3Dfx Banshee */
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#define FB_ACCEL_ATI_RAGE128 32 /* ATI Rage128 family */
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#define FB_ACCEL_IGS_CYBER2000 33 /* CyberPro 2000 */
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#define FB_ACCEL_IGS_CYBER2010 34 /* CyberPro 2010 */
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#define FB_ACCEL_IGS_CYBER5000 35 /* CyberPro 5000 */
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#define FB_ACCEL_SIS_GLAMOUR 36 /* SiS 300/630/540 */
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#define FB_ACCEL_3DLABS_PERMEDIA3 37 /* 3Dlabs Permedia 3 */
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#define FB_ACCEL_ATI_RADEON 38 /* ATI Radeon family */
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#define FB_ACCEL_I810 39 /* Intel 810/815 */
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#define FB_ACCEL_SIS_GLAMOUR_2 40 /* SiS 315, 650, 740 */
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#define FB_ACCEL_SIS_XABRE 41 /* SiS 330 ("Xabre") */
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#define FB_ACCEL_I830 42 /* Intel 830M/845G/85x/865G */
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#define FB_ACCEL_NV_10 43 /* nVidia Arch 10 */
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#define FB_ACCEL_NV_20 44 /* nVidia Arch 20 */
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#define FB_ACCEL_NV_30 45 /* nVidia Arch 30 */
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#define FB_ACCEL_NV_40 46 /* nVidia Arch 40 */
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#define FB_ACCEL_NEOMAGIC_NM2070 90 /* NeoMagic NM2070 */
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#define FB_ACCEL_NEOMAGIC_NM2090 91 /* NeoMagic NM2090 */
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#define FB_ACCEL_NEOMAGIC_NM2093 92 /* NeoMagic NM2093 */
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#define FB_ACCEL_NEOMAGIC_NM2097 93 /* NeoMagic NM2097 */
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#define FB_ACCEL_NEOMAGIC_NM2160 94 /* NeoMagic NM2160 */
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#define FB_ACCEL_NEOMAGIC_NM2200 95 /* NeoMagic NM2200 */
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#define FB_ACCEL_NEOMAGIC_NM2230 96 /* NeoMagic NM2230 */
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#define FB_ACCEL_NEOMAGIC_NM2360 97 /* NeoMagic NM2360 */
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#define FB_ACCEL_NEOMAGIC_NM2380 98 /* NeoMagic NM2380 */
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#define FB_ACCEL_SAVAGE4 0x80 /* S3 Savage4 */
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#define FB_ACCEL_SAVAGE3D 0x81 /* S3 Savage3D */
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#define FB_ACCEL_SAVAGE3D_MV 0x82 /* S3 Savage3D-MV */
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#define FB_ACCEL_SAVAGE2000 0x83 /* S3 Savage2000 */
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#define FB_ACCEL_SAVAGE_MX_MV 0x84 /* S3 Savage/MX-MV */
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#define FB_ACCEL_SAVAGE_MX 0x85 /* S3 Savage/MX */
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#define FB_ACCEL_SAVAGE_IX_MV 0x86 /* S3 Savage/IX-MV */
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#define FB_ACCEL_SAVAGE_IX 0x87 /* S3 Savage/IX */
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#define FB_ACCEL_PROSAVAGE_PM 0x88 /* S3 ProSavage PM133 */
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#define FB_ACCEL_PROSAVAGE_KM 0x89 /* S3 ProSavage KM133 */
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#define FB_ACCEL_S3TWISTER_P 0x8a /* S3 Twister */
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#define FB_ACCEL_S3TWISTER_K 0x8b /* S3 TwisterK */
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#define FB_ACCEL_SUPERSAVAGE 0x8c /* S3 Supersavage */
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#define FB_ACCEL_PROSAVAGE_DDR 0x8d /* S3 ProSavage DDR */
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#define FB_ACCEL_PROSAVAGE_DDRK 0x8e /* S3 ProSavage DDR-K */
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#define FB_ACCEL_SAVAGE4 0x80 /* S3 Savage4 */
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#define FB_ACCEL_SAVAGE3D 0x81 /* S3 Savage3D */
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#define FB_ACCEL_SAVAGE3D_MV 0x82 /* S3 Savage3D-MV */
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#define FB_ACCEL_SAVAGE2000 0x83 /* S3 Savage2000 */
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#define FB_ACCEL_SAVAGE_MX_MV 0x84 /* S3 Savage/MX-MV */
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#define FB_ACCEL_SAVAGE_MX 0x85 /* S3 Savage/MX */
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#define FB_ACCEL_SAVAGE_IX_MV 0x86 /* S3 Savage/IX-MV */
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#define FB_ACCEL_SAVAGE_IX 0x87 /* S3 Savage/IX */
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#define FB_ACCEL_PROSAVAGE_PM 0x88 /* S3 ProSavage PM133 */
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#define FB_ACCEL_PROSAVAGE_KM 0x89 /* S3 ProSavage KM133 */
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#define FB_ACCEL_S3TWISTER_P 0x8a /* S3 Twister */
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#define FB_ACCEL_S3TWISTER_K 0x8b /* S3 TwisterK */
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#define FB_ACCEL_SUPERSAVAGE 0x8c /* S3 Supersavage */
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#define FB_ACCEL_PROSAVAGE_DDR 0x8d /* S3 ProSavage DDR */
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#define FB_ACCEL_PROSAVAGE_DDRK 0x8e /* S3 ProSavage DDR-K */
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struct fb_fix_screeninfo {
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struct fb_fix_screeninfo
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{
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char id[16]; /* identification string eg "TT Builtin" */
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unsigned long smem_start; /* Start of frame buffer mem */
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/* (physical address) */
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@@ -199,18 +200,19 @@ struct fb_fix_screeninfo {
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* stream and is written to video memory as that unmodified. This implies
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* big-endian byte order if bits_per_pixel is greater than 8.
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*/
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struct fb_bitfield {
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struct fb_bitfield
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{
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unsigned long offset; /* beginning of bitfield */
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unsigned long length; /* length of bitfield */
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unsigned long msb_right; /* != 0 : Most significant bit is */
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/* right */
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};
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#define FB_NONSTD_HAM 1 /* Hold-And-Modify (HAM) */
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#define FB_NONSTD_HAM 1 /* Hold-And-Modify (HAM) */
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#define FB_ACTIVATE_NOW 0 /* set values immediately (or vbl)*/
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#define FB_ACTIVATE_NXTOPEN 1 /* activate on next open */
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#define FB_ACTIVATE_TEST 2 /* don't set, round up impossible */
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#define FB_ACTIVATE_NOW 0 /* set values immediately (or vbl)*/
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#define FB_ACTIVATE_NXTOPEN 1 /* activate on next open */
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#define FB_ACTIVATE_TEST 2 /* don't set, round up impossible */
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#define FB_ACTIVATE_MASK 15
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/* values */
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#define FB_ACTIVATE_VBL 16 /* activate values on next vbl */
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@@ -219,30 +221,31 @@ struct fb_bitfield {
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#define FB_ACTIVATE_FORCE 128 /* force apply even when no change*/
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#define FB_ACTIVATE_INV_MODE 256 /* invalidate videomode */
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#define FB_ACCELF_TEXT 1 /* (OBSOLETE) see fb_info.flags and vc_mode */
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#define FB_ACCELF_TEXT 1 /* (OBSOLETE) see fb_info.flags and vc_mode */
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#define FB_SYNC_HOR_HIGH_ACT 1 /* horizontal sync high active */
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#define FB_SYNC_VERT_HIGH_ACT 2 /* vertical sync high active */
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#define FB_SYNC_EXT 4 /* external sync */
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#define FB_SYNC_COMP_HIGH_ACT 8 /* composite sync high active */
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#define FB_SYNC_BROADCAST 16 /* broadcast video timings */
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#define FB_SYNC_HOR_HIGH_ACT 1 /* horizontal sync high active */
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#define FB_SYNC_VERT_HIGH_ACT 2 /* vertical sync high active */
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#define FB_SYNC_EXT 4 /* external sync */
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#define FB_SYNC_COMP_HIGH_ACT 8 /* composite sync high active */
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#define FB_SYNC_BROADCAST 16 /* broadcast video timings */
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/* vtotal = 144d/288n/576i => PAL */
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/* vtotal = 121d/242n/484i => NTSC */
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#define FB_SYNC_ON_GREEN 32 /* sync on green */
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#define FB_SYNC_ON_GREEN 32 /* sync on green */
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#define FB_VMODE_NONINTERLACED 0 /* non interlaced */
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#define FB_VMODE_INTERLACED 1 /* interlaced */
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#define FB_VMODE_DOUBLE 2 /* double scan */
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#define FB_VMODE_MASK 255
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#define FB_VMODE_INTERLACED 1 /* interlaced */
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#define FB_VMODE_DOUBLE 2 /* double scan */
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#define FB_VMODE_MASK 255
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#define FB_VMODE_YWRAP 256 /* ywrap instead of panning */
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#define FB_VMODE_SMOOTH_XPAN 512 /* smooth xpan possible (internally used) */
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#define FB_VMODE_CONUPDATE 512 /* don't update x/yoffset */
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#define FB_VMODE_YWRAP 256 /* ywrap instead of panning */
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#define FB_VMODE_SMOOTH_XPAN 512 /* smooth xpan possible (internally used) */
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#define FB_VMODE_CONUPDATE 512 /* don't update x/yoffset */
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#define PICOS2KHZ(a) (1000000000UL/(a))
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#define KHZ2PICOS(a) (1000000000UL/(a))
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#define PICOS2KHZ(a) (1000000000UL/(a))
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#define KHZ2PICOS(a) (1000000000UL/(a))
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struct fb_var_screeninfo {
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struct fb_var_screeninfo
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{
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unsigned long xres; /* visible resolution */
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unsigned long yres;
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unsigned long xres_virtual; /* virtual resolution */
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@@ -311,7 +314,8 @@ enum {
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#define FB_VBLANK_VSYNCING 0x080 /* currently in a vsync */
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#define FB_VBLANK_HAVE_VSYNC 0x100 /* verical syncs can be detected */
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struct fb_vblank {
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struct fb_vblank
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{
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unsigned long flags; /* FB_VBLANK flags */
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unsigned long count; /* counter of retraces since boot */
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unsigned long vcount; /* current scanline position */
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@@ -349,7 +353,8 @@ struct file;
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#define FB_MISC_PRIM_COLOR 1
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#define FB_MISC_1ST_DETAIL 2 /* First Detailed Timing is preferred */
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struct fb_chroma {
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struct fb_chroma
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{
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unsigned long redx; /* in fraction of 1024 */
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unsigned long greenx;
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unsigned long bluex;
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@@ -360,7 +365,8 @@ struct fb_chroma {
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unsigned long whitey;
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};
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||||
|
||||
struct fb_monspecs {
|
||||
struct fb_monspecs
|
||||
{
|
||||
struct fb_chroma chroma;
|
||||
struct fb_videomode *modedb; /* mode database */
|
||||
unsigned char manufacturer[4]; /* Manufacturer */
|
||||
@@ -390,7 +396,8 @@ struct fb_monspecs {
|
||||
unsigned char max_y; /* Maximum vertical size (cm) */
|
||||
};
|
||||
|
||||
struct fb_ops {
|
||||
struct fb_ops
|
||||
{
|
||||
/* checks var and eventually tweaks if to soomething supported,
|
||||
* DO NOT MODIFY PAR */
|
||||
int (*fb_check_var)(struct fb_var_screeninfo *var, struct fb_info *info);
|
||||
@@ -449,7 +456,8 @@ struct fb_ops {
|
||||
void (*WaitVbl)(struct fb_info *info);
|
||||
};
|
||||
|
||||
struct fb_info {
|
||||
struct fb_info
|
||||
{
|
||||
struct fb_var_screeninfo var; /* Current var */
|
||||
struct fb_fix_screeninfo fix; /* Current fix */
|
||||
struct fb_monspecs monspecs; /* Current Monitor specs */
|
||||
|
||||
@@ -1,6 +1,10 @@
|
||||
#ifndef __RADEONFB_H__
|
||||
#define __RADEONFB_H__
|
||||
|
||||
#ifdef CONFIG_FB_RADEON_I2C
|
||||
#undef CONFIG_FB_RADEON_I2C
|
||||
#endif
|
||||
|
||||
#include <bas_string.h>
|
||||
#include "pci.h"
|
||||
#include "mod_devicetable.h"
|
||||
@@ -39,50 +43,50 @@
|
||||
*/
|
||||
enum radeon_family
|
||||
{
|
||||
CHIP_FAMILY_UNKNOW,
|
||||
CHIP_FAMILY_LEGACY,
|
||||
CHIP_FAMILY_RADEON,
|
||||
CHIP_FAMILY_RV100,
|
||||
CHIP_FAMILY_RS100, /* U1 (IGP320M) or A3 (IGP320)*/
|
||||
CHIP_FAMILY_RV200,
|
||||
CHIP_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350), RS250 (IGP 7000) */
|
||||
CHIP_FAMILY_R200,
|
||||
CHIP_FAMILY_RV250,
|
||||
CHIP_FAMILY_RS300, /* Radeon 9000 IGP */
|
||||
CHIP_FAMILY_RV280,
|
||||
CHIP_FAMILY_R300,
|
||||
CHIP_FAMILY_R350,
|
||||
CHIP_FAMILY_RV350,
|
||||
CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */
|
||||
CHIP_FAMILY_R420, /* R420/R423/M18 */
|
||||
CHIP_FAMILY_LAST,
|
||||
CHIP_FAMILY_UNKNOW,
|
||||
CHIP_FAMILY_LEGACY,
|
||||
CHIP_FAMILY_RADEON,
|
||||
CHIP_FAMILY_RV100,
|
||||
CHIP_FAMILY_RS100, /* U1 (IGP320M) or A3 (IGP320)*/
|
||||
CHIP_FAMILY_RV200,
|
||||
CHIP_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350), RS250 (IGP 7000) */
|
||||
CHIP_FAMILY_R200,
|
||||
CHIP_FAMILY_RV250,
|
||||
CHIP_FAMILY_RS300, /* Radeon 9000 IGP */
|
||||
CHIP_FAMILY_RV280,
|
||||
CHIP_FAMILY_R300,
|
||||
CHIP_FAMILY_R350,
|
||||
CHIP_FAMILY_RV350,
|
||||
CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */
|
||||
CHIP_FAMILY_R420, /* R420/R423/M18 */
|
||||
CHIP_FAMILY_LAST,
|
||||
};
|
||||
|
||||
#define IS_RV100_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_RV100) || \
|
||||
((rinfo)->family == CHIP_FAMILY_RV200) || \
|
||||
((rinfo)->family == CHIP_FAMILY_RS100) || \
|
||||
((rinfo)->family == CHIP_FAMILY_RS200) || \
|
||||
((rinfo)->family == CHIP_FAMILY_RV250) || \
|
||||
((rinfo)->family == CHIP_FAMILY_RV280) || \
|
||||
((rinfo)->family == CHIP_FAMILY_RS300))
|
||||
((rinfo)->family == CHIP_FAMILY_RV200) || \
|
||||
((rinfo)->family == CHIP_FAMILY_RS100) || \
|
||||
((rinfo)->family == CHIP_FAMILY_RS200) || \
|
||||
((rinfo)->family == CHIP_FAMILY_RV250) || \
|
||||
((rinfo)->family == CHIP_FAMILY_RV280) || \
|
||||
((rinfo)->family == CHIP_FAMILY_RS300))
|
||||
|
||||
|
||||
#define IS_R300_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_R300) || \
|
||||
((rinfo)->family == CHIP_FAMILY_RV350) || \
|
||||
((rinfo)->family == CHIP_FAMILY_R350) || \
|
||||
((rinfo)->family == CHIP_FAMILY_RV380) || \
|
||||
((rinfo)->family == CHIP_FAMILY_R420))
|
||||
((rinfo)->family == CHIP_FAMILY_RV350) || \
|
||||
((rinfo)->family == CHIP_FAMILY_R350) || \
|
||||
((rinfo)->family == CHIP_FAMILY_RV380) || \
|
||||
((rinfo)->family == CHIP_FAMILY_R420))
|
||||
|
||||
/*
|
||||
* Chip flags
|
||||
*/
|
||||
enum radeon_chip_flags
|
||||
{
|
||||
CHIP_FAMILY_MASK = 0x0000ffffUL,
|
||||
CHIP_FLAGS_MASK = 0xffff0000UL,
|
||||
CHIP_IS_MOBILITY = 0x00010000UL,
|
||||
CHIP_IS_IGP = 0x00020000UL,
|
||||
CHIP_HAS_CRTC2 = 0x00040000UL,
|
||||
CHIP_FAMILY_MASK = 0x0000ffffUL,
|
||||
CHIP_FLAGS_MASK = 0xffff0000UL,
|
||||
CHIP_IS_MOBILITY = 0x00010000UL,
|
||||
CHIP_IS_IGP = 0x00020000UL,
|
||||
CHIP_HAS_CRTC2 = 0x00040000UL,
|
||||
};
|
||||
|
||||
/*
|
||||
@@ -90,9 +94,9 @@ enum radeon_chip_flags
|
||||
*/
|
||||
enum radeon_errata
|
||||
{
|
||||
CHIP_ERRATA_R300_CG = 0x00000001,
|
||||
CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
|
||||
CHIP_ERRATA_PLL_DELAY = 0x00000004,
|
||||
CHIP_ERRATA_R300_CG = 0x00000001,
|
||||
CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
|
||||
CHIP_ERRATA_PLL_DELAY = 0x00000004,
|
||||
};
|
||||
|
||||
|
||||
@@ -101,12 +105,12 @@ enum radeon_errata
|
||||
*/
|
||||
enum radeon_montype
|
||||
{
|
||||
MT_NONE = 0,
|
||||
MT_CRT, /* CRT */
|
||||
MT_LCD, /* LCD */
|
||||
MT_DFP, /* DVI */
|
||||
MT_CTV, /* composite TV */
|
||||
MT_STV /* S-Video out */
|
||||
MT_NONE = 0,
|
||||
MT_CRT, /* CRT */
|
||||
MT_LCD, /* LCD */
|
||||
MT_DFP, /* DVI */
|
||||
MT_CTV, /* composite TV */
|
||||
MT_STV /* S-Video out */
|
||||
};
|
||||
|
||||
/*
|
||||
@@ -114,11 +118,11 @@ enum radeon_montype
|
||||
*/
|
||||
enum ddc_type
|
||||
{
|
||||
ddc_none,
|
||||
ddc_monid,
|
||||
ddc_dvi,
|
||||
ddc_vga,
|
||||
ddc_crt2,
|
||||
ddc_none,
|
||||
ddc_monid,
|
||||
ddc_dvi,
|
||||
ddc_vga,
|
||||
ddc_crt2,
|
||||
};
|
||||
|
||||
/*
|
||||
@@ -126,11 +130,11 @@ enum ddc_type
|
||||
*/
|
||||
enum conn_type
|
||||
{
|
||||
conn_none,
|
||||
conn_proprietary,
|
||||
conn_crt,
|
||||
conn_DVI_I,
|
||||
conn_DVI_D,
|
||||
conn_none,
|
||||
conn_proprietary,
|
||||
conn_crt,
|
||||
conn_DVI_I,
|
||||
conn_DVI_D,
|
||||
};
|
||||
|
||||
|
||||
@@ -139,11 +143,11 @@ enum conn_type
|
||||
*/
|
||||
struct pll_info
|
||||
{
|
||||
int32_t ppll_max;
|
||||
int32_t ppll_min;
|
||||
int32_t sclk, mclk;
|
||||
int32_t ref_div;
|
||||
int32_t ref_clk;
|
||||
int32_t ppll_max;
|
||||
int32_t ppll_min;
|
||||
int32_t sclk, mclk;
|
||||
int32_t ref_div;
|
||||
int32_t ref_clk;
|
||||
};
|
||||
|
||||
|
||||
@@ -155,120 +159,120 @@ struct pll_info
|
||||
*/
|
||||
struct radeon_regs
|
||||
{
|
||||
/* Common registers */
|
||||
uint32_t ovr_clr;
|
||||
uint32_t ovr_wid_left_right;
|
||||
uint32_t ovr_wid_top_bottom;
|
||||
uint32_t ov0_scale_cntl;
|
||||
uint32_t mpp_tb_config;
|
||||
uint32_t mpp_gp_config;
|
||||
uint32_t subpic_cntl;
|
||||
uint32_t viph_control;
|
||||
uint32_t i2c_cntl_1;
|
||||
uint32_t gen_int32_t_cntl;
|
||||
uint32_t cap0_trig_cntl;
|
||||
uint32_t cap1_trig_cntl;
|
||||
uint32_t bus_cntl;
|
||||
uint32_t surface_cntl;
|
||||
uint32_t bios_5_scratch;
|
||||
/* Common registers */
|
||||
uint32_t ovr_clr;
|
||||
uint32_t ovr_wid_left_right;
|
||||
uint32_t ovr_wid_top_bottom;
|
||||
uint32_t ov0_scale_cntl;
|
||||
uint32_t mpp_tb_config;
|
||||
uint32_t mpp_gp_config;
|
||||
uint32_t subpic_cntl;
|
||||
uint32_t viph_control;
|
||||
uint32_t i2c_cntl_1;
|
||||
uint32_t gen_int32_t_cntl;
|
||||
uint32_t cap0_trig_cntl;
|
||||
uint32_t cap1_trig_cntl;
|
||||
uint32_t bus_cntl;
|
||||
uint32_t surface_cntl;
|
||||
uint32_t bios_5_scratch;
|
||||
|
||||
/* Other registers to save for VT switches or driver load/unload */
|
||||
uint32_t dp_datatype;
|
||||
uint32_t rbbm_soft_reset;
|
||||
uint32_t clock_cntl_index;
|
||||
uint32_t amcgpio_en_reg;
|
||||
uint32_t amcgpio_mask;
|
||||
/* Other registers to save for VT switches or driver load/unload */
|
||||
uint32_t dp_datatype;
|
||||
uint32_t rbbm_soft_reset;
|
||||
uint32_t clock_cntl_index;
|
||||
uint32_t amcgpio_en_reg;
|
||||
uint32_t amcgpio_mask;
|
||||
|
||||
/* Surface/tiling registers */
|
||||
uint32_t surf_lower_bound[8];
|
||||
uint32_t surf_upper_bound[8];
|
||||
uint32_t surf_info[8];
|
||||
/* Surface/tiling registers */
|
||||
uint32_t surf_lower_bound[8];
|
||||
uint32_t surf_upper_bound[8];
|
||||
uint32_t surf_info[8];
|
||||
|
||||
/* CRTC registers */
|
||||
uint32_t crtc_gen_cntl;
|
||||
uint32_t crtc_ext_cntl;
|
||||
uint32_t dac_cntl;
|
||||
uint32_t crtc_h_total_disp;
|
||||
uint32_t crtc_h_sync_strt_wid;
|
||||
uint32_t crtc_v_total_disp;
|
||||
uint32_t crtc_v_sync_strt_wid;
|
||||
uint32_t crtc_offset;
|
||||
uint32_t crtc_offset_cntl;
|
||||
uint32_t crtc_pitch;
|
||||
uint32_t disp_merge_cntl;
|
||||
uint32_t grph_buffer_cntl;
|
||||
uint32_t crtc_more_cntl;
|
||||
/* CRTC registers */
|
||||
uint32_t crtc_gen_cntl;
|
||||
uint32_t crtc_ext_cntl;
|
||||
uint32_t dac_cntl;
|
||||
uint32_t crtc_h_total_disp;
|
||||
uint32_t crtc_h_sync_strt_wid;
|
||||
uint32_t crtc_v_total_disp;
|
||||
uint32_t crtc_v_sync_strt_wid;
|
||||
uint32_t crtc_offset;
|
||||
uint32_t crtc_offset_cntl;
|
||||
uint32_t crtc_pitch;
|
||||
uint32_t disp_merge_cntl;
|
||||
uint32_t grph_buffer_cntl;
|
||||
uint32_t crtc_more_cntl;
|
||||
|
||||
/* CRTC2 registers */
|
||||
uint32_t crtc2_gen_cntl;
|
||||
uint32_t dac2_cntl;
|
||||
uint32_t disp_output_cntl;
|
||||
uint32_t disp_hw_debug;
|
||||
uint32_t disp2_merge_cntl;
|
||||
uint32_t grph2_buffer_cntl;
|
||||
uint32_t crtc2_h_total_disp;
|
||||
uint32_t crtc2_h_sync_strt_wid;
|
||||
uint32_t crtc2_v_total_disp;
|
||||
uint32_t crtc2_v_sync_strt_wid;
|
||||
uint32_t crtc2_offset;
|
||||
uint32_t crtc2_offset_cntl;
|
||||
uint32_t crtc2_pitch;
|
||||
/* CRTC2 registers */
|
||||
uint32_t crtc2_gen_cntl;
|
||||
uint32_t dac2_cntl;
|
||||
uint32_t disp_output_cntl;
|
||||
uint32_t disp_hw_debug;
|
||||
uint32_t disp2_merge_cntl;
|
||||
uint32_t grph2_buffer_cntl;
|
||||
uint32_t crtc2_h_total_disp;
|
||||
uint32_t crtc2_h_sync_strt_wid;
|
||||
uint32_t crtc2_v_total_disp;
|
||||
uint32_t crtc2_v_sync_strt_wid;
|
||||
uint32_t crtc2_offset;
|
||||
uint32_t crtc2_offset_cntl;
|
||||
uint32_t crtc2_pitch;
|
||||
|
||||
/* Flat panel regs */
|
||||
uint32_t fp_crtc_h_total_disp;
|
||||
uint32_t fp_crtc_v_total_disp;
|
||||
uint32_t fp_gen_cntl;
|
||||
uint32_t fp2_gen_cntl;
|
||||
uint32_t fp_h_sync_strt_wid;
|
||||
uint32_t fp2_h_sync_strt_wid;
|
||||
uint32_t fp_horz_stretch;
|
||||
uint32_t fp_panel_cntl;
|
||||
uint32_t fp_v_sync_strt_wid;
|
||||
uint32_t fp2_v_sync_strt_wid;
|
||||
uint32_t fp_vert_stretch;
|
||||
uint32_t lvds_gen_cntl;
|
||||
uint32_t lvds_pll_cntl;
|
||||
uint32_t tmds_crc;
|
||||
uint32_t tmds_transmitter_cntl;
|
||||
/* Flat panel regs */
|
||||
uint32_t fp_crtc_h_total_disp;
|
||||
uint32_t fp_crtc_v_total_disp;
|
||||
uint32_t fp_gen_cntl;
|
||||
uint32_t fp2_gen_cntl;
|
||||
uint32_t fp_h_sync_strt_wid;
|
||||
uint32_t fp2_h_sync_strt_wid;
|
||||
uint32_t fp_horz_stretch;
|
||||
uint32_t fp_panel_cntl;
|
||||
uint32_t fp_v_sync_strt_wid;
|
||||
uint32_t fp2_v_sync_strt_wid;
|
||||
uint32_t fp_vert_stretch;
|
||||
uint32_t lvds_gen_cntl;
|
||||
uint32_t lvds_pll_cntl;
|
||||
uint32_t tmds_crc;
|
||||
uint32_t tmds_transmitter_cntl;
|
||||
|
||||
/* Computed values for PLL */
|
||||
uint32_t dot_clock_freq;
|
||||
uint32_t pll_output_freq;
|
||||
int32_t feedback_div;
|
||||
int32_t post_div;
|
||||
/* Computed values for PLL */
|
||||
uint32_t dot_clock_freq;
|
||||
uint32_t pll_output_freq;
|
||||
int32_t feedback_div;
|
||||
int32_t post_div;
|
||||
|
||||
/* PLL registers */
|
||||
uint32_t ppll_div_3;
|
||||
uint32_t ppll_ref_div;
|
||||
uint32_t vclk_ecp_cntl;
|
||||
uint32_t clk_cntl_index;
|
||||
uint32_t htotal_cntl;
|
||||
/* PLL registers */
|
||||
uint32_t ppll_div_3;
|
||||
uint32_t ppll_ref_div;
|
||||
uint32_t vclk_ecp_cntl;
|
||||
uint32_t clk_cntl_index;
|
||||
uint32_t htotal_cntl;
|
||||
|
||||
/* Computed values for PLL2 */
|
||||
uint32_t dot_clock_freq_2;
|
||||
uint32_t pll_output_freq_2;
|
||||
int32_t feedback_div_2;
|
||||
int32_t post_div_2;
|
||||
/* Computed values for PLL2 */
|
||||
uint32_t dot_clock_freq_2;
|
||||
uint32_t pll_output_freq_2;
|
||||
int32_t feedback_div_2;
|
||||
int32_t post_div_2;
|
||||
|
||||
/* PLL2 registers */
|
||||
uint32_t p2pll_ref_div;
|
||||
uint32_t p2pll_div_0;
|
||||
uint32_t htotal_cntl2;
|
||||
/* PLL2 registers */
|
||||
uint32_t p2pll_ref_div;
|
||||
uint32_t p2pll_div_0;
|
||||
uint32_t htotal_cntl2;
|
||||
};
|
||||
|
||||
struct panel_info
|
||||
{
|
||||
int32_t xres, yres;
|
||||
int32_t valid;
|
||||
int32_t clock;
|
||||
int32_t hOver_plus, hSync_width, hblank;
|
||||
int32_t vOver_plus, vSync_width, vblank;
|
||||
int32_t hAct_high, vAct_high, int32_terlaced;
|
||||
int32_t pwr_delay;
|
||||
int32_t use_bios_dividers;
|
||||
int32_t ref_divider;
|
||||
int32_t post_divider;
|
||||
int32_t fbk_divider;
|
||||
int32_t xres, yres;
|
||||
int32_t valid;
|
||||
int32_t clock;
|
||||
int32_t hOver_plus, hSync_width, hblank;
|
||||
int32_t vOver_plus, vSync_width, vblank;
|
||||
int32_t hAct_high, vAct_high, int32_terlaced;
|
||||
int32_t pwr_delay;
|
||||
int32_t use_bios_dividers;
|
||||
int32_t ref_divider;
|
||||
int32_t post_divider;
|
||||
int32_t fbk_divider;
|
||||
};
|
||||
|
||||
struct radeonfb_info;
|
||||
@@ -276,186 +280,186 @@ struct radeonfb_info;
|
||||
#ifdef CONFIG_FB_RADEON_I2C
|
||||
struct radeon_i2c_chan
|
||||
{
|
||||
struct radeonfb_info *rinfo;
|
||||
uint32_t ddc_reg;
|
||||
struct i2c_adapter adapter;
|
||||
struct i2c_algo_bit_data algo;
|
||||
struct radeonfb_info *rinfo;
|
||||
uint32_t ddc_reg;
|
||||
struct i2c_adapter adapter;
|
||||
struct i2c_algo_bit_data algo;
|
||||
};
|
||||
#endif
|
||||
|
||||
enum radeon_pm_mode
|
||||
{
|
||||
radeon_pm_none = 0, /* Nothing supported */
|
||||
radeon_pm_d2 = 0x00000001, /* Can do D2 state */
|
||||
radeon_pm_off = 0x00000002, /* Can resume from D3 cold */
|
||||
radeon_pm_none = 0, /* Nothing supported */
|
||||
radeon_pm_d2 = 0x00000001, /* Can do D2 state */
|
||||
radeon_pm_off = 0x00000002, /* Can resume from D3 cold */
|
||||
};
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint8_t table_revision;
|
||||
uint8_t table_size;
|
||||
uint8_t tuner_type;
|
||||
uint8_t audio_chip;
|
||||
uint8_t product_id;
|
||||
uint8_t tuner_voltage_teletext_fm;
|
||||
uint8_t i2s_config; /* configuration of the sound chip */
|
||||
uint8_t video_decoder_type;
|
||||
uint8_t video_decoder_host_config;
|
||||
uint8_t input[5];
|
||||
uint8_t table_revision;
|
||||
uint8_t table_size;
|
||||
uint8_t tuner_type;
|
||||
uint8_t audio_chip;
|
||||
uint8_t product_id;
|
||||
uint8_t tuner_voltage_teletext_fm;
|
||||
uint8_t i2s_config; /* configuration of the sound chip */
|
||||
uint8_t video_decoder_type;
|
||||
uint8_t video_decoder_host_config;
|
||||
uint8_t input[5];
|
||||
} _MM_TABLE;
|
||||
|
||||
struct radeonfb_info
|
||||
{
|
||||
int32_t handle; /* PCI BIOS, must be 1st place */
|
||||
int32_t big_endian; /* PCI BIOS */
|
||||
int32_t handle; /* PCI BIOS, must be 1st place */
|
||||
int32_t big_endian; /* PCI BIOS */
|
||||
|
||||
uint32_t cursor_x;
|
||||
uint32_t cursor_y;
|
||||
int32_t cursor_show;
|
||||
uint32_t cursor_start;
|
||||
uint32_t cursor_end;
|
||||
int32_t cursor_fg;
|
||||
int32_t cursor_bg;
|
||||
uint32_t cursor_x;
|
||||
uint32_t cursor_y;
|
||||
int32_t cursor_show;
|
||||
uint32_t cursor_start;
|
||||
uint32_t cursor_end;
|
||||
int32_t cursor_fg;
|
||||
int32_t cursor_bg;
|
||||
|
||||
int32_t fifo_slots; /* Free slots in the FIFO (64 max) */
|
||||
int32_t fifo_slots; /* Free slots in the FIFO (64 max) */
|
||||
|
||||
/* Computed values for Radeon */
|
||||
uint32_t dp_gui_master_cntl_clip;
|
||||
uint32_t trans_color;
|
||||
/* Computed values for Radeon */
|
||||
uint32_t dp_gui_master_cntl_clip;
|
||||
uint32_t trans_color;
|
||||
|
||||
/* Saved values for ScreenToScreenCopy */
|
||||
int32_t xdir;
|
||||
int32_t ydir;
|
||||
/* Saved values for ScreenToScreenCopy */
|
||||
int32_t xdir;
|
||||
int32_t ydir;
|
||||
|
||||
/* ScanlineScreenToScreenColorExpand support */
|
||||
int32_t scanline_h;
|
||||
int32_t scanline_words;
|
||||
int32_t scanline_bpp; /* Only used for ImageWrite */
|
||||
/* ScanlineScreenToScreenColorExpand support */
|
||||
int32_t scanline_h;
|
||||
int32_t scanline_words;
|
||||
int32_t scanline_bpp; /* Only used for ImageWrite */
|
||||
|
||||
/* Saved values for DashedTwoPoint32_tLine */
|
||||
int32_t dashLen;
|
||||
uint32_t dashPattern;
|
||||
int32_t dash_fg;
|
||||
int32_t dash_bg;
|
||||
/* Saved values for DashedTwoPoint32_tLine */
|
||||
int32_t dashLen;
|
||||
uint32_t dashPattern;
|
||||
int32_t dash_fg;
|
||||
int32_t dash_bg;
|
||||
|
||||
struct fb_info *info;
|
||||
struct fb_info *info;
|
||||
|
||||
struct radeon_regs state;
|
||||
struct radeon_regs init_state;
|
||||
struct radeon_regs state;
|
||||
struct radeon_regs init_state;
|
||||
|
||||
uint8_t name[50];
|
||||
uint8_t name[50];
|
||||
|
||||
uint32_t io_base_phys;
|
||||
uint32_t mmio_base_phys;
|
||||
uint32_t fb_base_phys;
|
||||
uint32_t io_base_phys;
|
||||
uint32_t mmio_base_phys;
|
||||
uint32_t fb_base_phys;
|
||||
|
||||
void *io_base;
|
||||
void *mmio_base;
|
||||
void *fb_base;
|
||||
void *io_base;
|
||||
void *mmio_base;
|
||||
void *fb_base;
|
||||
|
||||
uint32_t fb_local_base;
|
||||
uint32_t fb_offset;
|
||||
uint32_t fb_local_base;
|
||||
uint32_t fb_offset;
|
||||
|
||||
uint32_t bios_seg_phys;
|
||||
void *bios_seg;
|
||||
int32_t fp_bios_start;
|
||||
uint32_t bios_seg_phys;
|
||||
void *bios_seg;
|
||||
int32_t fp_bios_start;
|
||||
|
||||
struct
|
||||
{
|
||||
uint8_t red;
|
||||
uint8_t green;
|
||||
uint8_t blue;
|
||||
uint8_t pad;
|
||||
} palette[256];
|
||||
struct
|
||||
{
|
||||
uint8_t red;
|
||||
uint8_t green;
|
||||
uint8_t blue;
|
||||
uint8_t pad;
|
||||
} palette[256];
|
||||
|
||||
int32_t chipset;
|
||||
uint8_t family;
|
||||
uint8_t rev;
|
||||
int32_t errata;
|
||||
uint32_t video_ram;
|
||||
uint32_t mapped_vram;
|
||||
int32_t vram_width;
|
||||
int32_t vram_ddr;
|
||||
int32_t chipset;
|
||||
uint8_t family;
|
||||
uint8_t rev;
|
||||
int32_t errata;
|
||||
uint32_t video_ram;
|
||||
uint32_t mapped_vram;
|
||||
int32_t vram_width;
|
||||
int32_t vram_ddr;
|
||||
|
||||
int32_t pitch, bpp, depth;
|
||||
int32_t pitch, bpp, depth;
|
||||
|
||||
int32_t has_CRTC2;
|
||||
int32_t is_mobility;
|
||||
int32_t is_IGP;
|
||||
int32_t reversed_DAC;
|
||||
int32_t reversed_TMDS;
|
||||
struct panel_info panel_info;
|
||||
int32_t mon1_type;
|
||||
uint8_t *mon1_EDID;
|
||||
struct fb_videomode *mon1_modedb;
|
||||
int32_t mon1_dbsize;
|
||||
int32_t mon2_type;
|
||||
uint8_t *mon2_EDID;
|
||||
int32_t has_CRTC2;
|
||||
int32_t is_mobility;
|
||||
int32_t is_IGP;
|
||||
int32_t reversed_DAC;
|
||||
int32_t reversed_TMDS;
|
||||
struct panel_info panel_info;
|
||||
int32_t mon1_type;
|
||||
uint8_t *mon1_EDID;
|
||||
struct fb_videomode *mon1_modedb;
|
||||
int32_t mon1_dbsize;
|
||||
int32_t mon2_type;
|
||||
uint8_t *mon2_EDID;
|
||||
|
||||
uint32_t dp_gui_master_cntl;
|
||||
uint32_t dp_gui_master_cntl;
|
||||
|
||||
struct pll_info bios_pll;
|
||||
struct pll_info pll;
|
||||
struct pll_info bios_pll;
|
||||
struct pll_info pll;
|
||||
|
||||
uint32_t save_regs[100];
|
||||
int32_t asleep;
|
||||
int32_t lock_blank;
|
||||
int32_t dynclk;
|
||||
int32_t no_schedule;
|
||||
enum radeon_pm_mode pm_mode;
|
||||
uint32_t save_regs[100];
|
||||
int32_t asleep;
|
||||
int32_t lock_blank;
|
||||
int32_t dynclk;
|
||||
int32_t no_schedule;
|
||||
enum radeon_pm_mode pm_mode;
|
||||
|
||||
/* Timer used for delayed LVDS operations */
|
||||
int32_t lvds_timer;
|
||||
uint32_t pending_lvds_gen_cntl;
|
||||
/* Timer used for delayed LVDS operations */
|
||||
int32_t lvds_timer;
|
||||
uint32_t pending_lvds_gen_cntl;
|
||||
|
||||
#ifdef CONFIG_FB_RADEON_I2C
|
||||
struct radeon_i2c_chan i2c[4];
|
||||
struct radeon_i2c_chan i2c[4];
|
||||
#endif
|
||||
|
||||
/* Texture */
|
||||
/* Texture */
|
||||
|
||||
int32_t RenderInited3D;
|
||||
int32_t tilingEnabled;
|
||||
void *RenderTex;
|
||||
uint32_t RenderTexOffset;
|
||||
int32_t RenderTexSize;
|
||||
void (*RenderCallback)(struct radeonfb_info *rinfo);
|
||||
uint32_t RenderTimeout;
|
||||
uint32_t dst_pitch_offset;
|
||||
int32_t RenderInited3D;
|
||||
int32_t tilingEnabled;
|
||||
void *RenderTex;
|
||||
uint32_t RenderTexOffset;
|
||||
int32_t RenderTexSize;
|
||||
void (*RenderCallback)(struct radeonfb_info *rinfo);
|
||||
uint32_t RenderTimeout;
|
||||
uint32_t dst_pitch_offset;
|
||||
|
||||
|
||||
#ifdef _NOT_USED_
|
||||
/* Video & theatre */
|
||||
/* Video & theatre */
|
||||
|
||||
TheatrePtr theatre;
|
||||
TheatrePtr theatre;
|
||||
|
||||
int32_t MM_TABLE_valid;
|
||||
_MM_TABLE MM_TABLE;
|
||||
int32_t MM_TABLE_valid;
|
||||
_MM_TABLE MM_TABLE;
|
||||
|
||||
int32_t RageTheatreCrystal;
|
||||
int32_t RageTheatreTunerPort;
|
||||
int32_t RageTheatreCompositePort;
|
||||
int32_t RageTheatreSVideoPort;
|
||||
int32_t tunerType;
|
||||
int32_t RageTheatreCrystal;
|
||||
int32_t RageTheatreTunerPort;
|
||||
int32_t RageTheatreCompositePort;
|
||||
int32_t RageTheatreSVideoPort;
|
||||
int32_t tunerType;
|
||||
|
||||
int32_t videoStatus;
|
||||
int32_t encoding;
|
||||
int32_t overlay_deint32_terlacing_method;
|
||||
int32_t video_stream_active;
|
||||
int32_t capture_vbi_data;
|
||||
int32_t v;
|
||||
void *videoLinear;
|
||||
int32_t videoLinearSize;
|
||||
struct
|
||||
{
|
||||
uint32_t y,u,v;
|
||||
} videoLinearOffset;
|
||||
int32_t videoStatus;
|
||||
int32_t encoding;
|
||||
int32_t overlay_deint32_terlacing_method;
|
||||
int32_t video_stream_active;
|
||||
int32_t capture_vbi_data;
|
||||
int32_t v;
|
||||
void *videoLinear;
|
||||
int32_t videoLinearSize;
|
||||
struct
|
||||
{
|
||||
uint32_t y,u,v;
|
||||
} videoLinearOffset;
|
||||
#endif /* _NOT_USED_ */
|
||||
|
||||
int32_t dec_hue;
|
||||
int32_t dec_saturation;
|
||||
int32_t dec_contrast;
|
||||
int32_t dec_brightness;
|
||||
int32_t dec_hue;
|
||||
int32_t dec_saturation;
|
||||
int32_t dec_contrast;
|
||||
int32_t dec_brightness;
|
||||
};
|
||||
|
||||
#define PRIMARY_MONITOR(rinfo) (rinfo->mon1_type)
|
||||
@@ -473,7 +477,7 @@ struct radeonfb_info
|
||||
*/
|
||||
static inline void _radeon_msleep(struct radeonfb_info *rinfo, uint32_t ms)
|
||||
{
|
||||
wait_ms(ms);
|
||||
wait_ms(ms);
|
||||
}
|
||||
|
||||
#define radeon_msleep(ms) _radeon_msleep(rinfo,ms)
|
||||
@@ -509,14 +513,14 @@ extern int32_t *tab_funcs_pci;
|
||||
|
||||
static inline uint32_t radeon_get_dstbpp(uint16_t depth)
|
||||
{
|
||||
switch(depth)
|
||||
{
|
||||
case 8: return DST_8BPP;
|
||||
case 15: return DST_15BPP;
|
||||
case 16: return DST_16BPP;
|
||||
case 32: return DST_32BPP;
|
||||
default: return 0;
|
||||
}
|
||||
switch(depth)
|
||||
{
|
||||
case 8: return DST_8BPP;
|
||||
case 15: return DST_15BPP;
|
||||
case 16: return DST_16BPP;
|
||||
case 32: return DST_32BPP;
|
||||
default: return 0;
|
||||
}
|
||||
}
|
||||
|
||||
/* I2C Functions */
|
||||
@@ -532,11 +536,11 @@ extern void radeonfb_pm_exit(struct radeonfb_info *rinfo);
|
||||
|
||||
/* Monitor probe functions */
|
||||
extern void radeon_probe_screens(struct radeonfb_info *rinfo,
|
||||
const char *monitor_layout, int ignore_edid);
|
||||
const char *monitor_layout, int ignore_edid);
|
||||
extern void radeon_check_modes(struct radeonfb_info *rinfo, struct mode_option *resolution);
|
||||
extern int radeon_match_mode(struct radeonfb_info *rinfo,
|
||||
struct fb_var_screeninfo *dest,
|
||||
const struct fb_var_screeninfo *src);
|
||||
struct fb_var_screeninfo *dest,
|
||||
const struct fb_var_screeninfo *src);
|
||||
|
||||
/* Video functions */
|
||||
void RADEONResetVideo(struct radeonfb_info *rinfo);
|
||||
@@ -549,7 +553,7 @@ void RADEONVIP_reset(struct radeonfb_info *rinfo);
|
||||
void RADEONInitVideo(struct radeonfb_info *rinfo);
|
||||
void RADEONShutdownVideo(struct radeonfb_info *rinfo);
|
||||
int32_t RADEONPutVideo(struct radeonfb_info *rinfo, int32_t src_x, int32_t src_y, int32_t src_w, int32_t src_h,
|
||||
int32_t drw_x, int32_t drw_y, int32_t drw_w, int32_t drw_h);
|
||||
int32_t drw_x, int32_t drw_y, int32_t drw_w, int32_t drw_h);
|
||||
void RADEONStopVideo(struct radeonfb_info *rinfo, int32_t cleanup);
|
||||
|
||||
/* Theatre functions */
|
||||
@@ -582,18 +586,18 @@ extern void radeon_wait_for_idle_mmio(struct radeonfb_info *rinfo);
|
||||
#define radeon_engine_idle() radeon_wait_for_idle_mmio(rinfo)
|
||||
|
||||
#define radeon_wait_for_fifo(rinfo, entries) \
|
||||
do \
|
||||
{ \
|
||||
if (rinfo->fifo_slots < entries) \
|
||||
radeon_wait_for_fifo_function(rinfo, entries); \
|
||||
rinfo->fifo_slots -= entries; \
|
||||
} while (0)
|
||||
do \
|
||||
{ \
|
||||
if (rinfo->fifo_slots < entries) \
|
||||
radeon_wait_for_fifo_function(rinfo, entries); \
|
||||
rinfo->fifo_slots -= entries; \
|
||||
} while (0)
|
||||
|
||||
static inline int radeonfb_sync(struct fb_info *info)
|
||||
{
|
||||
struct radeonfb_info *rinfo = info->par;
|
||||
radeon_engine_idle();
|
||||
return 0;
|
||||
struct radeonfb_info *rinfo = info->par;
|
||||
radeon_engine_idle();
|
||||
return 0;
|
||||
}
|
||||
|
||||
extern void radeon_restore_accel_state_mmio(struct fb_info *info);
|
||||
@@ -602,47 +606,47 @@ extern void radeon_subsequent_solid_fill_rect_mmio(struct fb_info *info, int x,
|
||||
extern void radeon_setup_for_solid_line_mmio(struct fb_info *info, int color, int rop, unsigned int planemask);
|
||||
extern void radeon_subsequent_solid_hor_vert_line_mmio(struct fb_info *info, int x, int y, int len, int dir);
|
||||
extern void radeon_subsequent_solid_two_point_line_mmio(struct fb_info *info, int xa, int ya, int xb,
|
||||
int yb, int flags);
|
||||
int yb, int flags);
|
||||
extern void radeon_setup_for_dashed_line_mmio(struct fb_info *info, int fg, int bg,
|
||||
int rop, unsigned int planemask, int length, unsigned char *pattern);
|
||||
int rop, unsigned int planemask, int length, unsigned char *pattern);
|
||||
extern void radeon_subsequent_dashed_two_point_line_mmio(struct fb_info *info,
|
||||
int xa, int ya, int xb, int yb, int flags, int phase);
|
||||
int xa, int ya, int xb, int yb, int flags, int phase);
|
||||
extern void radeon_setup_for_screen_to_screen_copy_mmio(struct fb_info *info,
|
||||
int xdir, int ydir, int rop, unsigned int planemask, int trans_color);
|
||||
int xdir, int ydir, int rop, unsigned int planemask, int trans_color);
|
||||
extern void radeon_subsequent_screen_to_screen_copy_mmio(struct fb_info *info,
|
||||
int xa, int ya, int xb, int yb, int w, int h);
|
||||
int xa, int ya, int xb, int yb, int w, int h);
|
||||
extern void radeon_screen_to_screen_copy_mmio(struct fb_info *info,
|
||||
int xa, int ya, int xb, int yb, int w, int h, int rop);
|
||||
int xa, int ya, int xb, int yb, int w, int h, int rop);
|
||||
extern void radeon_setup_for_mono_8x8_pattern_fill_mmio(struct fb_info *info,
|
||||
int patternx, int patterny, int fg, int bg, int rop, unsigned int planemask);
|
||||
int patternx, int patterny, int fg, int bg, int rop, unsigned int planemask);
|
||||
extern void radeon_subsequent_mono_8x8_pattern_fill_rect_mmio(struct fb_info *info,
|
||||
int patternx, int patterny, int x, int y, int w, int h);
|
||||
int patternx, int patterny, int x, int y, int w, int h);
|
||||
extern void radeon_setup_for_scanline_cpu_to_screen_color_expand_fill_mmio(struct fb_info *info,
|
||||
int fg, int bg, int rop, unsigned int planemask);
|
||||
int fg, int bg, int rop, unsigned int planemask);
|
||||
extern void radeon_subsequent_scanline_cpu_to_screen_color_expand_fill_mmio(struct fb_info *info,
|
||||
int x, int y, int w, int h, int skipleft);
|
||||
int x, int y, int w, int h, int skipleft);
|
||||
extern void radeon_subsequent_scanline_mmio(struct fb_info *info, unsigned long *buf);
|
||||
extern void radeon_setup_for_scanline_image_write_mmio(struct fb_info *info,
|
||||
int rop, unsigned int planemask, int trans_color, int bpp);
|
||||
int rop, unsigned int planemask, int trans_color, int bpp);
|
||||
extern void radeon_subsequent_scanline_image_write_rect_mmio(struct fb_info *info,
|
||||
int x, int y, int w, int h, int skipleft);
|
||||
int x, int y, int w, int h, int skipleft);
|
||||
extern void radeon_set_clipping_rectangle_mmio(struct fb_info *info,
|
||||
int xa, int ya, int xb, int yb);
|
||||
int xa, int ya, int xb, int yb);
|
||||
extern void radeon_disable_clipping_mmio(struct fb_info *info);
|
||||
|
||||
extern int32_t radeon_setup_for_cpu_to_screen_alpha_texture_mmio(struct fb_info *info,
|
||||
int op, int red, int green, int blue,
|
||||
int alpha, int maskFormat, int dstFormat,
|
||||
uint8_t *alphaPtr, int alphaPitch,
|
||||
int width, int height, int32_t flags);
|
||||
int op, int red, int green, int blue,
|
||||
int alpha, int maskFormat, int dstFormat,
|
||||
uint8_t *alphaPtr, int alphaPitch,
|
||||
int width, int height, int32_t flags);
|
||||
extern int32_t radeon_setup_for_cpu_to_screen_texture_mmio(struct fb_info *info, int32_t op,
|
||||
uint32_t srcFormat, uint32_t dstFormat,
|
||||
uint8_t *texPtr, int32_t texPitch,
|
||||
int32_t width, int32_t height, int32_t flags);
|
||||
uint32_t srcFormat, uint32_t dstFormat,
|
||||
uint8_t *texPtr, int32_t texPitch,
|
||||
int32_t width, int32_t height, int32_t flags);
|
||||
extern void radeon_subsequent_cpu_to_screen_texture_mmio(struct fb_info *info,
|
||||
int32_t dstx, int32_t dsty,
|
||||
int32_t srcx, int32_t srcy,
|
||||
int32_t width, int32_t height);
|
||||
int32_t dstx, int32_t dsty,
|
||||
int32_t srcx, int32_t srcy,
|
||||
int32_t width, int32_t height);
|
||||
/* Cursor functions */
|
||||
extern void radeon_set_cursor_colors(struct fb_info *info, int bg, int fg);
|
||||
extern void radeon_set_cursor_position(struct fb_info *info, int x, int y);
|
||||
@@ -655,7 +659,7 @@ extern long radeon_cursor_init(struct fb_info *info);
|
||||
extern int32_t radeon_screen_blank(struct radeonfb_info *rinfo, int32_t blank, int32_t mode_switch);
|
||||
extern void radeon_write_mode(struct radeonfb_info *rinfo, struct radeon_regs *mode, int32_t reg_only);
|
||||
int radeonfb_setcolreg(unsigned regno, unsigned red, unsigned green,
|
||||
unsigned blue, unsigned transp, struct fb_info *info);
|
||||
unsigned blue, unsigned transp, struct fb_info *info);
|
||||
extern int32_t radeonfb_pci_register(int32_t handle, const struct pci_device_id *ent);
|
||||
extern void radeonfb_pci_unregister(void);
|
||||
|
||||
|
||||
Reference in New Issue
Block a user