IP migration and cleanup - again
This commit is contained in:
torlus
99
FPGA_quartus_GE/altip_orig/altddio_bidir0.bsf
Normal file
99
FPGA_quartus_GE/altip_orig/altddio_bidir0.bsf
Normal file
@@ -0,0 +1,99 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2008 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 0 0 240 136)
|
||||
(text "altddio_bidir0" (rect 82 1 171 17)(font "Arial" (font_size 10)))
|
||||
(text "inst" (rect 8 120 25 132)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 24)
|
||||
(input)
|
||||
(text "datain_h[31..0]" (rect 0 0 83 14)(font "Arial" (font_size 8)))
|
||||
(text "datain_h[31..0]" (rect 4 11 76 24)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 24)(pt 88 24)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 40)
|
||||
(input)
|
||||
(text "datain_l[31..0]" (rect 0 0 79 14)(font "Arial" (font_size 8)))
|
||||
(text "datain_l[31..0]" (rect 4 27 73 40)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 40)(pt 88 40)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 56)
|
||||
(input)
|
||||
(text "oe" (rect 0 0 14 14)(font "Arial" (font_size 8)))
|
||||
(text "oe" (rect 4 43 16 56)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 56)(pt 88 56)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 72)
|
||||
(input)
|
||||
(text "inclock" (rect 0 0 38 14)(font "Arial" (font_size 8)))
|
||||
(text "inclock" (rect 4 59 36 72)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 72)(pt 88 72)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 88)
|
||||
(input)
|
||||
(text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8)))
|
||||
(text "outclock" (rect 4 75 42 88)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 88)(pt 88 88)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 240 24)
|
||||
(output)
|
||||
(text "dataout_h[31..0]" (rect 0 0 92 14)(font "Arial" (font_size 8)))
|
||||
(text "dataout_h[31..0]" (rect 159 11 237 24)(font "Arial" (font_size 8)))
|
||||
(line (pt 240 24)(pt 144 24)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 240 40)
|
||||
(output)
|
||||
(text "dataout_l[31..0]" (rect 0 0 87 14)(font "Arial" (font_size 8)))
|
||||
(text "dataout_l[31..0]" (rect 163 27 238 40)(font "Arial" (font_size 8)))
|
||||
(line (pt 240 40)(pt 144 40)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 240 72)
|
||||
(output)
|
||||
(text "combout[31..0]" (rect 0 0 83 14)(font "Arial" (font_size 8)))
|
||||
(text "combout[31..0]" (rect 166 59 237 72)(font "Arial" (font_size 8)))
|
||||
(line (pt 240 72)(pt 144 72)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 240 56)
|
||||
(bidir)
|
||||
(text "padio[31..0]" (rect 0 0 66 14)(font "Arial" (font_size 8)))
|
||||
(text "padio[31..0]" (rect 181 43 238 56)(font "Arial" (font_size 8)))
|
||||
(line (pt 240 56)(pt 144 56)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(text "ddio" (rect 108 27 129 40)(font "Arial" (font_size 8)))
|
||||
(text "bidir" (rect 108 42 129 55)(font "Arial" (font_size 8)))
|
||||
(text "power up" (rect 92 90 129 102)(font "Arial" ))
|
||||
(text "low" (rect 92 100 105 112)(font "Arial" ))
|
||||
(line (pt 88 16)(pt 144 16)(line_width 1))
|
||||
(line (pt 144 16)(pt 144 112)(line_width 1))
|
||||
(line (pt 144 112)(pt 88 112)(line_width 1))
|
||||
(line (pt 88 112)(pt 88 16)(line_width 1))
|
||||
)
|
||||
)
|
||||
30
FPGA_quartus_GE/altip_orig/altddio_bidir0.inc
Normal file
30
FPGA_quartus_GE/altip_orig/altddio_bidir0.inc
Normal file
@@ -0,0 +1,30 @@
|
||||
--Copyright (C) 1991-2008 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
FUNCTION altddio_bidir0
|
||||
(
|
||||
datain_h[31..0],
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||||
datain_l[31..0],
|
||||
inclock,
|
||||
oe,
|
||||
outclock
|
||||
)
|
||||
|
||||
RETURNS (
|
||||
combout[31..0],
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||||
dataout_h[31..0],
|
||||
dataout_l[31..0],
|
||||
padio[31..0]
|
||||
);
|
||||
16
FPGA_quartus_GE/altip_orig/altddio_bidir0.ppf
Normal file
16
FPGA_quartus_GE/altip_orig/altddio_bidir0.ppf
Normal file
@@ -0,0 +1,16 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<!DOCTYPE pinplan>
|
||||
<pinplan intended_family="Cyclone III" variation_name="altddio_bidir0" megafunction_name="ALTDDIO_BIDIR" specifies="all_ports">
|
||||
<global>
|
||||
<pin name="datain_h[31..0]" direction="input" scope="external" />
|
||||
<pin name="datain_l[31..0]" direction="input" scope="external" />
|
||||
<pin name="inclock" direction="input" scope="external" source="clock" />
|
||||
<pin name="oe" direction="input" scope="external" />
|
||||
<pin name="outclock" direction="input" scope="external" source="clock" />
|
||||
<pin name="combout[31..0]" direction="output" scope="external" />
|
||||
<pin name="dataout_h[31..0]" direction="output" scope="external" />
|
||||
<pin name="dataout_l[31..0]" direction="output" scope="external" />
|
||||
<pin name="padio[31..0]" direction="bidir" scope="external" />
|
||||
|
||||
</global>
|
||||
</pinplan>
|
||||
7
FPGA_quartus_GE/altip_orig/altddio_bidir0.qip
Normal file
7
FPGA_quartus_GE/altip_orig/altddio_bidir0.qip
Normal file
@@ -0,0 +1,7 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ALTDDIO_BIDIR"
|
||||
set_global_assignment -name IP_TOOL_VERSION "8.1"
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_bidir0.vhd"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.bsf"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.inc"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.cmp"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.ppf"]
|
||||
172
FPGA_quartus_GE/altip_orig/altddio_bidir0.vhd
Normal file
172
FPGA_quartus_GE/altip_orig/altddio_bidir0.vhd
Normal file
@@ -0,0 +1,172 @@
|
||||
-- megafunction wizard: %ALTDDIO_BIDIR%
|
||||
-- GENERATION: STANDARD
|
||||
-- VERSION: WM1.0
|
||||
-- MODULE: altddio_bidir
|
||||
|
||||
-- ============================================================
|
||||
-- File Name: altddio_bidir0.vhd
|
||||
-- Megafunction Name(s):
|
||||
-- altddio_bidir
|
||||
--
|
||||
-- Simulation Library Files(s):
|
||||
-- altera_mf
|
||||
-- ============================================================
|
||||
-- ************************************************************
|
||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
--
|
||||
-- 8.1 Build 163 10/28/2008 SJ Web Edition
|
||||
-- ************************************************************
|
||||
|
||||
|
||||
--Copyright (C) 1991-2008 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
|
||||
LIBRARY altera_mf;
|
||||
USE altera_mf.all;
|
||||
|
||||
ENTITY altddio_bidir0 IS
|
||||
PORT
|
||||
(
|
||||
datain_h : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
|
||||
datain_l : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
|
||||
inclock : IN STD_LOGIC ;
|
||||
oe : IN STD_LOGIC := '1';
|
||||
outclock : IN STD_LOGIC ;
|
||||
combout : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
|
||||
dataout_h : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
|
||||
dataout_l : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
|
||||
padio : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0)
|
||||
);
|
||||
END altddio_bidir0;
|
||||
|
||||
|
||||
ARCHITECTURE SYN OF altddio_bidir0 IS
|
||||
|
||||
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
|
||||
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
|
||||
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (31 DOWNTO 0);
|
||||
|
||||
|
||||
|
||||
COMPONENT altddio_bidir
|
||||
GENERIC (
|
||||
extend_oe_disable : STRING;
|
||||
implement_input_in_lcell : STRING;
|
||||
intended_device_family : STRING;
|
||||
invert_output : STRING;
|
||||
lpm_type : STRING;
|
||||
oe_reg : STRING;
|
||||
power_up_high : STRING;
|
||||
width : NATURAL
|
||||
);
|
||||
PORT (
|
||||
outclock : IN STD_LOGIC ;
|
||||
padio : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0);
|
||||
inclock : IN STD_LOGIC ;
|
||||
dataout_h : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
|
||||
oe : IN STD_LOGIC ;
|
||||
datain_h : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
|
||||
combout : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
|
||||
dataout_l : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
|
||||
datain_l : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
BEGIN
|
||||
dataout_h <= sub_wire0(31 DOWNTO 0);
|
||||
combout <= sub_wire1(31 DOWNTO 0);
|
||||
dataout_l <= sub_wire2(31 DOWNTO 0);
|
||||
|
||||
altddio_bidir_component : altddio_bidir
|
||||
GENERIC MAP (
|
||||
extend_oe_disable => "UNUSED",
|
||||
implement_input_in_lcell => "ON",
|
||||
intended_device_family => "Cyclone III",
|
||||
invert_output => "OFF",
|
||||
lpm_type => "altddio_bidir",
|
||||
oe_reg => "UNUSED",
|
||||
power_up_high => "OFF",
|
||||
width => 32
|
||||
)
|
||||
PORT MAP (
|
||||
outclock => outclock,
|
||||
inclock => inclock,
|
||||
oe => oe,
|
||||
datain_h => datain_h,
|
||||
datain_l => datain_l,
|
||||
dataout_h => sub_wire0,
|
||||
combout => sub_wire1,
|
||||
dataout_l => sub_wire2,
|
||||
padio => padio
|
||||
);
|
||||
|
||||
|
||||
|
||||
END SYN;
|
||||
|
||||
-- ============================================================
|
||||
-- CNX file retrieval info
|
||||
-- ============================================================
|
||||
-- Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2"
|
||||
-- Retrieval info: PRIVATE: CLKEN NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: IMPLEMENT_INPUT_IN_LCELL NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: PRIVATE: OE NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: OE_REG NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2"
|
||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_COMBOUT NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: USE_DATAOUT NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: USE_DQS_UNDELAYOUT NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: WIDTH NUMERIC "32"
|
||||
-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
|
||||
-- Retrieval info: CONSTANT: IMPLEMENT_INPUT_IN_LCELL STRING "ON"
|
||||
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
|
||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_bidir"
|
||||
-- Retrieval info: CONSTANT: OE_REG STRING "UNUSED"
|
||||
-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
|
||||
-- Retrieval info: CONSTANT: WIDTH NUMERIC "32"
|
||||
-- Retrieval info: USED_PORT: combout 0 0 32 0 OUTPUT NODEFVAL combout[31..0]
|
||||
-- Retrieval info: USED_PORT: datain_h 0 0 32 0 INPUT NODEFVAL datain_h[31..0]
|
||||
-- Retrieval info: USED_PORT: datain_l 0 0 32 0 INPUT NODEFVAL datain_l[31..0]
|
||||
-- Retrieval info: USED_PORT: dataout_h 0 0 32 0 OUTPUT NODEFVAL dataout_h[31..0]
|
||||
-- Retrieval info: USED_PORT: dataout_l 0 0 32 0 OUTPUT NODEFVAL dataout_l[31..0]
|
||||
-- Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL inclock
|
||||
-- Retrieval info: USED_PORT: oe 0 0 0 0 INPUT VCC oe
|
||||
-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock
|
||||
-- Retrieval info: USED_PORT: padio 0 0 32 0 BIDIR NODEFVAL padio[31..0]
|
||||
-- Retrieval info: CONNECT: @datain_h 0 0 32 0 datain_h 0 0 32 0
|
||||
-- Retrieval info: CONNECT: @datain_l 0 0 32 0 datain_l 0 0 32 0
|
||||
-- Retrieval info: CONNECT: padio 0 0 32 0 @padio 0 0 32 0
|
||||
-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @oe 0 0 0 0 oe 0 0 0 0
|
||||
-- Retrieval info: CONNECT: dataout_h 0 0 32 0 @dataout_h 0 0 32 0
|
||||
-- Retrieval info: CONNECT: dataout_l 0 0 32 0 @dataout_l 0 0 32 0
|
||||
-- Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0
|
||||
-- Retrieval info: CONNECT: combout 0 0 32 0 @combout 0 0 32 0
|
||||
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.vhd TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.ppf TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.inc TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.cmp TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.bsf TRUE FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0_inst.vhd FALSE
|
||||
-- Retrieval info: LIB_FILE: altera_mf
|
||||
64
FPGA_quartus_GE/altip_orig/altddio_out0.bsf
Normal file
64
FPGA_quartus_GE/altip_orig/altddio_out0.bsf
Normal file
@@ -0,0 +1,64 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2008 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 0 0 232 120)
|
||||
(text "altddio_out0" (rect 81 1 163 17)(font "Arial" (font_size 10)))
|
||||
(text "inst" (rect 8 104 25 116)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 24)
|
||||
(input)
|
||||
(text "datain_h" (rect 0 0 48 14)(font "Arial" (font_size 8)))
|
||||
(text "datain_h" (rect 4 11 46 24)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 24)(pt 88 24)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 40)
|
||||
(input)
|
||||
(text "datain_l" (rect 0 0 43 14)(font "Arial" (font_size 8)))
|
||||
(text "datain_l" (rect 4 27 43 40)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 40)(pt 88 40)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 56)
|
||||
(input)
|
||||
(text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8)))
|
||||
(text "outclock" (rect 4 43 42 56)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 56)(pt 88 56)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 232 24)
|
||||
(output)
|
||||
(text "dataout" (rect 0 0 42 14)(font "Arial" (font_size 8)))
|
||||
(text "dataout" (rect 193 11 229 24)(font "Arial" (font_size 8)))
|
||||
(line (pt 232 24)(pt 152 24)(line_width 1))
|
||||
)
|
||||
(drawing
|
||||
(text "ddio" (rect 110 27 131 40)(font "Arial" (font_size 8)))
|
||||
(text "output" (rect 105 42 135 55)(font "Arial" (font_size 8)))
|
||||
(text "power up" (rect 92 74 129 86)(font "Arial" ))
|
||||
(text "low" (rect 92 84 105 96)(font "Arial" ))
|
||||
(line (pt 88 16)(pt 152 16)(line_width 1))
|
||||
(line (pt 152 16)(pt 152 96)(line_width 1))
|
||||
(line (pt 152 96)(pt 88 96)(line_width 1))
|
||||
(line (pt 88 96)(pt 88 16)(line_width 1))
|
||||
)
|
||||
)
|
||||
25
FPGA_quartus_GE/altip_orig/altddio_out0.inc
Normal file
25
FPGA_quartus_GE/altip_orig/altddio_out0.inc
Normal file
@@ -0,0 +1,25 @@
|
||||
--Copyright (C) 1991-2008 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
FUNCTION altddio_out0
|
||||
(
|
||||
datain_h,
|
||||
datain_l,
|
||||
outclock
|
||||
)
|
||||
|
||||
RETURNS (
|
||||
dataout
|
||||
);
|
||||
11
FPGA_quartus_GE/altip_orig/altddio_out0.ppf
Normal file
11
FPGA_quartus_GE/altip_orig/altddio_out0.ppf
Normal file
@@ -0,0 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<!DOCTYPE pinplan>
|
||||
<pinplan intended_family="Cyclone III" variation_name="altddio_out0" megafunction_name="ALTDDIO_OUT" specifies="all_ports">
|
||||
<global>
|
||||
<pin name="datain_h" direction="input" scope="external" />
|
||||
<pin name="datain_l" direction="input" scope="external" />
|
||||
<pin name="outclock" direction="input" scope="external" source="clock" />
|
||||
<pin name="dataout" direction="output" scope="external" />
|
||||
|
||||
</global>
|
||||
</pinplan>
|
||||
5
FPGA_quartus_GE/altip_orig/altddio_out0.qip
Normal file
5
FPGA_quartus_GE/altip_orig/altddio_out0.qip
Normal file
@@ -0,0 +1,5 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "altddio_out0.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0_bb.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.ppf"]
|
||||
146
FPGA_quartus_GE/altip_orig/altddio_out0.vhd
Normal file
146
FPGA_quartus_GE/altip_orig/altddio_out0.vhd
Normal file
@@ -0,0 +1,146 @@
|
||||
-- megafunction wizard: %ALTDDIO_OUT%
|
||||
-- GENERATION: STANDARD
|
||||
-- VERSION: WM1.0
|
||||
-- MODULE: altddio_out
|
||||
|
||||
-- ============================================================
|
||||
-- File Name: altddio_out0.vhd
|
||||
-- Megafunction Name(s):
|
||||
-- altddio_out
|
||||
--
|
||||
-- Simulation Library Files(s):
|
||||
-- altera_mf
|
||||
-- ============================================================
|
||||
-- ************************************************************
|
||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
--
|
||||
-- 8.1 Build 163 10/28/2008 SJ Web Edition
|
||||
-- ************************************************************
|
||||
|
||||
|
||||
--Copyright (C) 1991-2008 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
|
||||
LIBRARY altera_mf;
|
||||
USE altera_mf.all;
|
||||
|
||||
ENTITY altddio_out0 IS
|
||||
PORT
|
||||
(
|
||||
datain_h : IN STD_LOGIC ;
|
||||
datain_l : IN STD_LOGIC ;
|
||||
outclock : IN STD_LOGIC ;
|
||||
dataout : OUT STD_LOGIC
|
||||
);
|
||||
END altddio_out0;
|
||||
|
||||
|
||||
ARCHITECTURE SYN OF altddio_out0 IS
|
||||
|
||||
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
|
||||
SIGNAL sub_wire1 : STD_LOGIC ;
|
||||
SIGNAL sub_wire2 : STD_LOGIC ;
|
||||
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (0 DOWNTO 0);
|
||||
SIGNAL sub_wire4 : STD_LOGIC ;
|
||||
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);
|
||||
|
||||
|
||||
|
||||
COMPONENT altddio_out
|
||||
GENERIC (
|
||||
extend_oe_disable : STRING;
|
||||
intended_device_family : STRING;
|
||||
invert_output : STRING;
|
||||
lpm_type : STRING;
|
||||
oe_reg : STRING;
|
||||
power_up_high : STRING;
|
||||
width : NATURAL
|
||||
);
|
||||
PORT (
|
||||
dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
|
||||
outclock : IN STD_LOGIC ;
|
||||
datain_h : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
|
||||
datain_l : IN STD_LOGIC_VECTOR (0 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
BEGIN
|
||||
sub_wire1 <= sub_wire0(0);
|
||||
dataout <= sub_wire1;
|
||||
sub_wire2 <= datain_h;
|
||||
sub_wire3(0) <= sub_wire2;
|
||||
sub_wire4 <= datain_l;
|
||||
sub_wire5(0) <= sub_wire4;
|
||||
|
||||
altddio_out_component : altddio_out
|
||||
GENERIC MAP (
|
||||
extend_oe_disable => "UNUSED",
|
||||
intended_device_family => "Cyclone III",
|
||||
invert_output => "OFF",
|
||||
lpm_type => "altddio_out",
|
||||
oe_reg => "UNUSED",
|
||||
power_up_high => "OFF",
|
||||
width => 1
|
||||
)
|
||||
PORT MAP (
|
||||
outclock => outclock,
|
||||
datain_h => sub_wire3,
|
||||
datain_l => sub_wire5,
|
||||
dataout => sub_wire0
|
||||
);
|
||||
|
||||
|
||||
|
||||
END SYN;
|
||||
|
||||
-- ============================================================
|
||||
-- CNX file retrieval info
|
||||
-- ============================================================
|
||||
-- Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2"
|
||||
-- Retrieval info: PRIVATE: CLKEN NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: PRIVATE: OE NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: OE_REG NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2"
|
||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
-- Retrieval info: PRIVATE: WIDTH NUMERIC "1"
|
||||
-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
|
||||
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
|
||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
|
||||
-- Retrieval info: CONSTANT: OE_REG STRING "UNUSED"
|
||||
-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
|
||||
-- Retrieval info: CONSTANT: WIDTH NUMERIC "1"
|
||||
-- Retrieval info: USED_PORT: datain_h 0 0 0 0 INPUT NODEFVAL datain_h
|
||||
-- Retrieval info: USED_PORT: datain_l 0 0 0 0 INPUT NODEFVAL datain_l
|
||||
-- Retrieval info: USED_PORT: dataout 0 0 0 0 OUTPUT NODEFVAL dataout
|
||||
-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock
|
||||
-- Retrieval info: CONNECT: @datain_h 0 0 1 0 datain_h 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @datain_l 0 0 1 0 datain_l 0 0 0 0
|
||||
-- Retrieval info: CONNECT: dataout 0 0 0 0 @dataout 0 0 1 0
|
||||
-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
|
||||
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.vhd TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.ppf TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.inc TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.cmp TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.bsf TRUE FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0_inst.vhd FALSE
|
||||
-- Retrieval info: LIB_FILE: altera_mf
|
||||
64
FPGA_quartus_GE/altip_orig/altddio_out1.bsf
Normal file
64
FPGA_quartus_GE/altip_orig/altddio_out1.bsf
Normal file
@@ -0,0 +1,64 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2008 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 0 0 232 120)
|
||||
(text "altddio_out1" (rect 81 1 163 17)(font "Arial" (font_size 10)))
|
||||
(text "inst" (rect 8 104 25 116)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 24)
|
||||
(input)
|
||||
(text "datain_h" (rect 0 0 48 14)(font "Arial" (font_size 8)))
|
||||
(text "datain_h" (rect 4 11 46 24)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 24)(pt 88 24)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 40)
|
||||
(input)
|
||||
(text "datain_l" (rect 0 0 43 14)(font "Arial" (font_size 8)))
|
||||
(text "datain_l" (rect 4 27 43 40)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 40)(pt 88 40)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 56)
|
||||
(input)
|
||||
(text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8)))
|
||||
(text "outclock" (rect 4 43 42 56)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 56)(pt 88 56)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 232 24)
|
||||
(output)
|
||||
(text "dataout" (rect 0 0 42 14)(font "Arial" (font_size 8)))
|
||||
(text "dataout" (rect 193 11 229 24)(font "Arial" (font_size 8)))
|
||||
(line (pt 232 24)(pt 152 24)(line_width 1))
|
||||
)
|
||||
(drawing
|
||||
(text "ddio" (rect 110 27 131 40)(font "Arial" (font_size 8)))
|
||||
(text "output" (rect 105 42 135 55)(font "Arial" (font_size 8)))
|
||||
(text "power up" (rect 92 74 129 86)(font "Arial" ))
|
||||
(text "low" (rect 92 84 105 96)(font "Arial" ))
|
||||
(line (pt 88 16)(pt 152 16)(line_width 1))
|
||||
(line (pt 152 16)(pt 152 96)(line_width 1))
|
||||
(line (pt 152 96)(pt 88 96)(line_width 1))
|
||||
(line (pt 88 96)(pt 88 16)(line_width 1))
|
||||
)
|
||||
)
|
||||
25
FPGA_quartus_GE/altip_orig/altddio_out1.inc
Normal file
25
FPGA_quartus_GE/altip_orig/altddio_out1.inc
Normal file
@@ -0,0 +1,25 @@
|
||||
--Copyright (C) 1991-2008 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
FUNCTION altddio_out1
|
||||
(
|
||||
datain_h,
|
||||
datain_l,
|
||||
outclock
|
||||
)
|
||||
|
||||
RETURNS (
|
||||
dataout
|
||||
);
|
||||
11
FPGA_quartus_GE/altip_orig/altddio_out1.ppf
Normal file
11
FPGA_quartus_GE/altip_orig/altddio_out1.ppf
Normal file
@@ -0,0 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<!DOCTYPE pinplan>
|
||||
<pinplan intended_family="Cyclone III" variation_name="altddio_out1" megafunction_name="ALTDDIO_OUT" specifies="all_ports">
|
||||
<global>
|
||||
<pin name="datain_h" direction="input" scope="external" />
|
||||
<pin name="datain_l" direction="input" scope="external" />
|
||||
<pin name="outclock" direction="input" scope="external" source="clock" />
|
||||
<pin name="dataout" direction="output" scope="external" />
|
||||
|
||||
</global>
|
||||
</pinplan>
|
||||
7
FPGA_quartus_GE/altip_orig/altddio_out1.qip
Normal file
7
FPGA_quartus_GE/altip_orig/altddio_out1.qip
Normal file
@@ -0,0 +1,7 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT"
|
||||
set_global_assignment -name IP_TOOL_VERSION "8.1"
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_out1.vhd"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out1.bsf"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out1.inc"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out1.cmp"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out1.ppf"]
|
||||
146
FPGA_quartus_GE/altip_orig/altddio_out1.vhd
Normal file
146
FPGA_quartus_GE/altip_orig/altddio_out1.vhd
Normal file
@@ -0,0 +1,146 @@
|
||||
-- megafunction wizard: %ALTDDIO_OUT%
|
||||
-- GENERATION: STANDARD
|
||||
-- VERSION: WM1.0
|
||||
-- MODULE: altddio_out
|
||||
|
||||
-- ============================================================
|
||||
-- File Name: altddio_out1.vhd
|
||||
-- Megafunction Name(s):
|
||||
-- altddio_out
|
||||
--
|
||||
-- Simulation Library Files(s):
|
||||
-- altera_mf
|
||||
-- ============================================================
|
||||
-- ************************************************************
|
||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
--
|
||||
-- 8.1 Build 163 10/28/2008 SJ Web Edition
|
||||
-- ************************************************************
|
||||
|
||||
|
||||
--Copyright (C) 1991-2008 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
|
||||
LIBRARY altera_mf;
|
||||
USE altera_mf.all;
|
||||
|
||||
ENTITY altddio_out1 IS
|
||||
PORT
|
||||
(
|
||||
datain_h : IN STD_LOGIC ;
|
||||
datain_l : IN STD_LOGIC ;
|
||||
outclock : IN STD_LOGIC ;
|
||||
dataout : OUT STD_LOGIC
|
||||
);
|
||||
END altddio_out1;
|
||||
|
||||
|
||||
ARCHITECTURE SYN OF altddio_out1 IS
|
||||
|
||||
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
|
||||
SIGNAL sub_wire1 : STD_LOGIC ;
|
||||
SIGNAL sub_wire2 : STD_LOGIC ;
|
||||
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (0 DOWNTO 0);
|
||||
SIGNAL sub_wire4 : STD_LOGIC ;
|
||||
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);
|
||||
|
||||
|
||||
|
||||
COMPONENT altddio_out
|
||||
GENERIC (
|
||||
extend_oe_disable : STRING;
|
||||
intended_device_family : STRING;
|
||||
invert_output : STRING;
|
||||
lpm_type : STRING;
|
||||
oe_reg : STRING;
|
||||
power_up_high : STRING;
|
||||
width : NATURAL
|
||||
);
|
||||
PORT (
|
||||
dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
|
||||
outclock : IN STD_LOGIC ;
|
||||
datain_h : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
|
||||
datain_l : IN STD_LOGIC_VECTOR (0 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
BEGIN
|
||||
sub_wire1 <= sub_wire0(0);
|
||||
dataout <= sub_wire1;
|
||||
sub_wire2 <= datain_h;
|
||||
sub_wire3(0) <= sub_wire2;
|
||||
sub_wire4 <= datain_l;
|
||||
sub_wire5(0) <= sub_wire4;
|
||||
|
||||
altddio_out_component : altddio_out
|
||||
GENERIC MAP (
|
||||
extend_oe_disable => "UNUSED",
|
||||
intended_device_family => "Cyclone III",
|
||||
invert_output => "OFF",
|
||||
lpm_type => "altddio_out",
|
||||
oe_reg => "UNUSED",
|
||||
power_up_high => "OFF",
|
||||
width => 1
|
||||
)
|
||||
PORT MAP (
|
||||
outclock => outclock,
|
||||
datain_h => sub_wire3,
|
||||
datain_l => sub_wire5,
|
||||
dataout => sub_wire0
|
||||
);
|
||||
|
||||
|
||||
|
||||
END SYN;
|
||||
|
||||
-- ============================================================
|
||||
-- CNX file retrieval info
|
||||
-- ============================================================
|
||||
-- Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2"
|
||||
-- Retrieval info: PRIVATE: CLKEN NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: PRIVATE: OE NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: OE_REG NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2"
|
||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
-- Retrieval info: PRIVATE: WIDTH NUMERIC "1"
|
||||
-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
|
||||
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
|
||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
|
||||
-- Retrieval info: CONSTANT: OE_REG STRING "UNUSED"
|
||||
-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
|
||||
-- Retrieval info: CONSTANT: WIDTH NUMERIC "1"
|
||||
-- Retrieval info: USED_PORT: datain_h 0 0 0 0 INPUT NODEFVAL datain_h
|
||||
-- Retrieval info: USED_PORT: datain_l 0 0 0 0 INPUT NODEFVAL datain_l
|
||||
-- Retrieval info: USED_PORT: dataout 0 0 0 0 OUTPUT NODEFVAL dataout
|
||||
-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock
|
||||
-- Retrieval info: CONNECT: @datain_h 0 0 1 0 datain_h 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @datain_l 0 0 1 0 datain_l 0 0 0 0
|
||||
-- Retrieval info: CONNECT: dataout 0 0 0 0 @dataout 0 0 1 0
|
||||
-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
|
||||
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1.vhd TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1.ppf TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1.inc TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1.cmp TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1.bsf TRUE FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1_inst.vhd FALSE
|
||||
-- Retrieval info: LIB_FILE: altera_mf
|
||||
64
FPGA_quartus_GE/altip_orig/altddio_out2.bsf
Normal file
64
FPGA_quartus_GE/altip_orig/altddio_out2.bsf
Normal file
@@ -0,0 +1,64 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2008 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 0 0 232 120)
|
||||
(text "altddio_out2" (rect 81 1 163 17)(font "Arial" (font_size 10)))
|
||||
(text "inst" (rect 8 104 25 116)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 24)
|
||||
(input)
|
||||
(text "datain_h[23..0]" (rect 0 0 83 14)(font "Arial" (font_size 8)))
|
||||
(text "datain_h[23..0]" (rect 4 11 76 24)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 24)(pt 88 24)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 40)
|
||||
(input)
|
||||
(text "datain_l[23..0]" (rect 0 0 79 14)(font "Arial" (font_size 8)))
|
||||
(text "datain_l[23..0]" (rect 4 27 73 40)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 40)(pt 88 40)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 56)
|
||||
(input)
|
||||
(text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8)))
|
||||
(text "outclock" (rect 4 43 42 56)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 56)(pt 88 56)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 232 24)
|
||||
(output)
|
||||
(text "dataout[23..0]" (rect 0 0 77 14)(font "Arial" (font_size 8)))
|
||||
(text "dataout[23..0]" (rect 163 11 229 24)(font "Arial" (font_size 8)))
|
||||
(line (pt 232 24)(pt 152 24)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(text "ddio" (rect 110 27 131 40)(font "Arial" (font_size 8)))
|
||||
(text "output" (rect 105 42 135 55)(font "Arial" (font_size 8)))
|
||||
(text "power up" (rect 92 74 129 86)(font "Arial" ))
|
||||
(text "low" (rect 92 84 105 96)(font "Arial" ))
|
||||
(line (pt 88 16)(pt 152 16)(line_width 1))
|
||||
(line (pt 152 16)(pt 152 96)(line_width 1))
|
||||
(line (pt 152 96)(pt 88 96)(line_width 1))
|
||||
(line (pt 88 96)(pt 88 16)(line_width 1))
|
||||
)
|
||||
)
|
||||
25
FPGA_quartus_GE/altip_orig/altddio_out2.inc
Normal file
25
FPGA_quartus_GE/altip_orig/altddio_out2.inc
Normal file
@@ -0,0 +1,25 @@
|
||||
--Copyright (C) 1991-2008 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
FUNCTION altddio_out2
|
||||
(
|
||||
datain_h[23..0],
|
||||
datain_l[23..0],
|
||||
outclock
|
||||
)
|
||||
|
||||
RETURNS (
|
||||
dataout[23..0]
|
||||
);
|
||||
11
FPGA_quartus_GE/altip_orig/altddio_out2.ppf
Normal file
11
FPGA_quartus_GE/altip_orig/altddio_out2.ppf
Normal file
@@ -0,0 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<!DOCTYPE pinplan>
|
||||
<pinplan intended_family="Cyclone III" variation_name="altddio_out2" megafunction_name="ALTDDIO_OUT" specifies="all_ports">
|
||||
<global>
|
||||
<pin name="datain_h[23..0]" direction="input" scope="external" />
|
||||
<pin name="datain_l[23..0]" direction="input" scope="external" />
|
||||
<pin name="outclock" direction="input" scope="external" source="clock" />
|
||||
<pin name="dataout[23..0]" direction="output" scope="external" />
|
||||
|
||||
</global>
|
||||
</pinplan>
|
||||
7
FPGA_quartus_GE/altip_orig/altddio_out2.qip
Normal file
7
FPGA_quartus_GE/altip_orig/altddio_out2.qip
Normal file
@@ -0,0 +1,7 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT"
|
||||
set_global_assignment -name IP_TOOL_VERSION "8.1"
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_out2.vhd"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.bsf"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.inc"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.cmp"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.ppf"]
|
||||
136
FPGA_quartus_GE/altip_orig/altddio_out2.vhd
Normal file
136
FPGA_quartus_GE/altip_orig/altddio_out2.vhd
Normal file
@@ -0,0 +1,136 @@
|
||||
-- megafunction wizard: %ALTDDIO_OUT%
|
||||
-- GENERATION: STANDARD
|
||||
-- VERSION: WM1.0
|
||||
-- MODULE: altddio_out
|
||||
|
||||
-- ============================================================
|
||||
-- File Name: altddio_out2.vhd
|
||||
-- Megafunction Name(s):
|
||||
-- altddio_out
|
||||
--
|
||||
-- Simulation Library Files(s):
|
||||
-- altera_mf
|
||||
-- ============================================================
|
||||
-- ************************************************************
|
||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
--
|
||||
-- 8.1 Build 163 10/28/2008 SJ Web Edition
|
||||
-- ************************************************************
|
||||
|
||||
|
||||
--Copyright (C) 1991-2008 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
|
||||
LIBRARY altera_mf;
|
||||
USE altera_mf.all;
|
||||
|
||||
ENTITY altddio_out2 IS
|
||||
PORT
|
||||
(
|
||||
datain_h : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
|
||||
datain_l : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
|
||||
outclock : IN STD_LOGIC ;
|
||||
dataout : OUT STD_LOGIC_VECTOR (23 DOWNTO 0)
|
||||
);
|
||||
END altddio_out2;
|
||||
|
||||
|
||||
ARCHITECTURE SYN OF altddio_out2 IS
|
||||
|
||||
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (23 DOWNTO 0);
|
||||
|
||||
|
||||
|
||||
COMPONENT altddio_out
|
||||
GENERIC (
|
||||
extend_oe_disable : STRING;
|
||||
intended_device_family : STRING;
|
||||
invert_output : STRING;
|
||||
lpm_type : STRING;
|
||||
oe_reg : STRING;
|
||||
power_up_high : STRING;
|
||||
width : NATURAL
|
||||
);
|
||||
PORT (
|
||||
dataout : OUT STD_LOGIC_VECTOR (23 DOWNTO 0);
|
||||
outclock : IN STD_LOGIC ;
|
||||
datain_h : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
|
||||
datain_l : IN STD_LOGIC_VECTOR (23 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
BEGIN
|
||||
dataout <= sub_wire0(23 DOWNTO 0);
|
||||
|
||||
altddio_out_component : altddio_out
|
||||
GENERIC MAP (
|
||||
extend_oe_disable => "UNUSED",
|
||||
intended_device_family => "Cyclone III",
|
||||
invert_output => "OFF",
|
||||
lpm_type => "altddio_out",
|
||||
oe_reg => "UNUSED",
|
||||
power_up_high => "OFF",
|
||||
width => 24
|
||||
)
|
||||
PORT MAP (
|
||||
outclock => outclock,
|
||||
datain_h => datain_h,
|
||||
datain_l => datain_l,
|
||||
dataout => sub_wire0
|
||||
);
|
||||
|
||||
|
||||
|
||||
END SYN;
|
||||
|
||||
-- ============================================================
|
||||
-- CNX file retrieval info
|
||||
-- ============================================================
|
||||
-- Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2"
|
||||
-- Retrieval info: PRIVATE: CLKEN NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: PRIVATE: OE NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: OE_REG NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2"
|
||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
-- Retrieval info: PRIVATE: WIDTH NUMERIC "24"
|
||||
-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
|
||||
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
|
||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
|
||||
-- Retrieval info: CONSTANT: OE_REG STRING "UNUSED"
|
||||
-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
|
||||
-- Retrieval info: CONSTANT: WIDTH NUMERIC "24"
|
||||
-- Retrieval info: USED_PORT: datain_h 0 0 24 0 INPUT NODEFVAL datain_h[23..0]
|
||||
-- Retrieval info: USED_PORT: datain_l 0 0 24 0 INPUT NODEFVAL datain_l[23..0]
|
||||
-- Retrieval info: USED_PORT: dataout 0 0 24 0 OUTPUT NODEFVAL dataout[23..0]
|
||||
-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock
|
||||
-- Retrieval info: CONNECT: @datain_h 0 0 24 0 datain_h 0 0 24 0
|
||||
-- Retrieval info: CONNECT: @datain_l 0 0 24 0 datain_l 0 0 24 0
|
||||
-- Retrieval info: CONNECT: dataout 0 0 24 0 @dataout 0 0 24 0
|
||||
-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
|
||||
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.vhd TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.ppf TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.inc TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.cmp TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.bsf TRUE FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2_inst.vhd FALSE
|
||||
-- Retrieval info: LIB_FILE: altera_mf
|
||||
64
FPGA_quartus_GE/altip_orig/altddio_out3.bsf
Normal file
64
FPGA_quartus_GE/altip_orig/altddio_out3.bsf
Normal file
@@ -0,0 +1,64 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2008 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 0 0 232 120)
|
||||
(text "altddio_out3" (rect 81 1 163 17)(font "Arial" (font_size 10)))
|
||||
(text "inst" (rect 8 104 25 116)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 24)
|
||||
(input)
|
||||
(text "datain_h" (rect 0 0 48 14)(font "Arial" (font_size 8)))
|
||||
(text "datain_h" (rect 4 11 46 24)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 24)(pt 88 24)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 40)
|
||||
(input)
|
||||
(text "datain_l" (rect 0 0 43 14)(font "Arial" (font_size 8)))
|
||||
(text "datain_l" (rect 4 27 43 40)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 40)(pt 88 40)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 56)
|
||||
(input)
|
||||
(text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8)))
|
||||
(text "outclock" (rect 4 43 42 56)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 56)(pt 88 56)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 232 24)
|
||||
(output)
|
||||
(text "dataout" (rect 0 0 42 14)(font "Arial" (font_size 8)))
|
||||
(text "dataout" (rect 193 11 229 24)(font "Arial" (font_size 8)))
|
||||
(line (pt 232 24)(pt 152 24)(line_width 1))
|
||||
)
|
||||
(drawing
|
||||
(text "ddio" (rect 110 27 131 40)(font "Arial" (font_size 8)))
|
||||
(text "output" (rect 105 42 135 55)(font "Arial" (font_size 8)))
|
||||
(text "power up" (rect 92 74 129 86)(font "Arial" ))
|
||||
(text "low" (rect 92 84 105 96)(font "Arial" ))
|
||||
(line (pt 88 16)(pt 152 16)(line_width 1))
|
||||
(line (pt 152 16)(pt 152 96)(line_width 1))
|
||||
(line (pt 152 96)(pt 88 96)(line_width 1))
|
||||
(line (pt 88 96)(pt 88 16)(line_width 1))
|
||||
)
|
||||
)
|
||||
25
FPGA_quartus_GE/altip_orig/altddio_out3.inc
Normal file
25
FPGA_quartus_GE/altip_orig/altddio_out3.inc
Normal file
@@ -0,0 +1,25 @@
|
||||
--Copyright (C) 1991-2008 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
FUNCTION altddio_out3
|
||||
(
|
||||
datain_h,
|
||||
datain_l,
|
||||
outclock
|
||||
)
|
||||
|
||||
RETURNS (
|
||||
dataout
|
||||
);
|
||||
11
FPGA_quartus_GE/altip_orig/altddio_out3.ppf
Normal file
11
FPGA_quartus_GE/altip_orig/altddio_out3.ppf
Normal file
@@ -0,0 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<!DOCTYPE pinplan>
|
||||
<pinplan intended_family="Cyclone III" variation_name="altddio_out3" megafunction_name="ALTDDIO_OUT" specifies="all_ports">
|
||||
<global>
|
||||
<pin name="datain_h" direction="input" scope="external" />
|
||||
<pin name="datain_l" direction="input" scope="external" />
|
||||
<pin name="outclock" direction="input" scope="external" source="clock" />
|
||||
<pin name="dataout" direction="output" scope="external" />
|
||||
|
||||
</global>
|
||||
</pinplan>
|
||||
4
FPGA_quartus_GE/altip_orig/altddio_out3.qip
Normal file
4
FPGA_quartus_GE/altip_orig/altddio_out3.qip
Normal file
@@ -0,0 +1,4 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "altddio_out3.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out3.ppf"]
|
||||
146
FPGA_quartus_GE/altip_orig/altddio_out3.vhd
Normal file
146
FPGA_quartus_GE/altip_orig/altddio_out3.vhd
Normal file
@@ -0,0 +1,146 @@
|
||||
-- megafunction wizard: %ALTDDIO_OUT%
|
||||
-- GENERATION: STANDARD
|
||||
-- VERSION: WM1.0
|
||||
-- MODULE: altddio_out
|
||||
|
||||
-- ============================================================
|
||||
-- File Name: altddio_out3.vhd
|
||||
-- Megafunction Name(s):
|
||||
-- altddio_out
|
||||
--
|
||||
-- Simulation Library Files(s):
|
||||
-- altera_mf
|
||||
-- ============================================================
|
||||
-- ************************************************************
|
||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
--
|
||||
-- 8.1 Build 163 10/28/2008 SJ Web Edition
|
||||
-- ************************************************************
|
||||
|
||||
|
||||
--Copyright (C) 1991-2008 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
|
||||
LIBRARY altera_mf;
|
||||
USE altera_mf.all;
|
||||
|
||||
ENTITY altddio_out3 IS
|
||||
PORT
|
||||
(
|
||||
datain_h : IN STD_LOGIC ;
|
||||
datain_l : IN STD_LOGIC ;
|
||||
outclock : IN STD_LOGIC ;
|
||||
dataout : OUT STD_LOGIC
|
||||
);
|
||||
END altddio_out3;
|
||||
|
||||
|
||||
ARCHITECTURE SYN OF altddio_out3 IS
|
||||
|
||||
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
|
||||
SIGNAL sub_wire1 : STD_LOGIC ;
|
||||
SIGNAL sub_wire2 : STD_LOGIC ;
|
||||
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (0 DOWNTO 0);
|
||||
SIGNAL sub_wire4 : STD_LOGIC ;
|
||||
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);
|
||||
|
||||
|
||||
|
||||
COMPONENT altddio_out
|
||||
GENERIC (
|
||||
extend_oe_disable : STRING;
|
||||
intended_device_family : STRING;
|
||||
invert_output : STRING;
|
||||
lpm_type : STRING;
|
||||
oe_reg : STRING;
|
||||
power_up_high : STRING;
|
||||
width : NATURAL
|
||||
);
|
||||
PORT (
|
||||
dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
|
||||
outclock : IN STD_LOGIC ;
|
||||
datain_h : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
|
||||
datain_l : IN STD_LOGIC_VECTOR (0 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
BEGIN
|
||||
sub_wire1 <= sub_wire0(0);
|
||||
dataout <= sub_wire1;
|
||||
sub_wire2 <= datain_h;
|
||||
sub_wire3(0) <= sub_wire2;
|
||||
sub_wire4 <= datain_l;
|
||||
sub_wire5(0) <= sub_wire4;
|
||||
|
||||
altddio_out_component : altddio_out
|
||||
GENERIC MAP (
|
||||
extend_oe_disable => "UNUSED",
|
||||
intended_device_family => "Cyclone III",
|
||||
invert_output => "OFF",
|
||||
lpm_type => "altddio_out",
|
||||
oe_reg => "UNUSED",
|
||||
power_up_high => "OFF",
|
||||
width => 1
|
||||
)
|
||||
PORT MAP (
|
||||
outclock => outclock,
|
||||
datain_h => sub_wire3,
|
||||
datain_l => sub_wire5,
|
||||
dataout => sub_wire0
|
||||
);
|
||||
|
||||
|
||||
|
||||
END SYN;
|
||||
|
||||
-- ============================================================
|
||||
-- CNX file retrieval info
|
||||
-- ============================================================
|
||||
-- Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2"
|
||||
-- Retrieval info: PRIVATE: CLKEN NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: PRIVATE: OE NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: OE_REG NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2"
|
||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
-- Retrieval info: PRIVATE: WIDTH NUMERIC "1"
|
||||
-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
|
||||
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
|
||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
|
||||
-- Retrieval info: CONSTANT: OE_REG STRING "UNUSED"
|
||||
-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
|
||||
-- Retrieval info: CONSTANT: WIDTH NUMERIC "1"
|
||||
-- Retrieval info: USED_PORT: datain_h 0 0 0 0 INPUT NODEFVAL datain_h
|
||||
-- Retrieval info: USED_PORT: datain_l 0 0 0 0 INPUT NODEFVAL datain_l
|
||||
-- Retrieval info: USED_PORT: dataout 0 0 0 0 OUTPUT NODEFVAL dataout
|
||||
-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock
|
||||
-- Retrieval info: CONNECT: @datain_h 0 0 1 0 datain_h 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @datain_l 0 0 1 0 datain_l 0 0 0 0
|
||||
-- Retrieval info: CONNECT: dataout 0 0 0 0 @dataout 0 0 1 0
|
||||
-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
|
||||
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.vhd TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.ppf TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.inc TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.cmp TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.bsf TRUE FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3_inst.vhd FALSE
|
||||
-- Retrieval info: LIB_FILE: altera_mf
|
||||
173
FPGA_quartus_GE/altip_orig/altdpram0.bsf
Normal file
173
FPGA_quartus_GE/altip_orig/altdpram0.bsf
Normal file
@@ -0,0 +1,173 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2008 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 0 0 256 208)
|
||||
(text "altdpram0" (rect 100 1 167 17)(font "Arial" (font_size 10)))
|
||||
(text "inst" (rect 8 192 25 204)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "data_a[2..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
|
||||
(text "data_a[2..0]" (rect 4 19 61 32)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 32)(pt 112 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
(text "address_a[3..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
|
||||
(text "address_a[3..0]" (rect 4 35 75 48)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 48)(pt 112 48)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "wren_a" (rect 0 0 44 14)(font "Arial" (font_size 8)))
|
||||
(text "wren_a" (rect 4 51 38 64)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 64)(pt 112 64)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 96)
|
||||
(input)
|
||||
(text "data_b[2..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
|
||||
(text "data_b[2..0]" (rect 4 83 61 96)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 96)(pt 112 96)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 112)
|
||||
(input)
|
||||
(text "address_b[3..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
|
||||
(text "address_b[3..0]" (rect 4 99 75 112)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 112)(pt 112 112)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 128)
|
||||
(input)
|
||||
(text "wren_b" (rect 0 0 44 14)(font "Arial" (font_size 8)))
|
||||
(text "wren_b" (rect 4 115 38 128)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 128)(pt 112 128)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 160)
|
||||
(input)
|
||||
(text "clock_a" (rect 0 0 43 14)(font "Arial" (font_size 8)))
|
||||
(text "clock_a" (rect 4 147 39 160)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 160)(pt 176 160)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 176)
|
||||
(input)
|
||||
(text "clock_b" (rect 0 0 43 14)(font "Arial" (font_size 8)))
|
||||
(text "clock_b" (rect 4 163 39 176)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 176)(pt 181 176)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 256 32)
|
||||
(output)
|
||||
(text "q_a[2..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
|
||||
(text "q_a[2..0]" (rect 211 19 253 32)(font "Arial" (font_size 8)))
|
||||
(line (pt 256 32)(pt 192 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 256 96)
|
||||
(output)
|
||||
(text "q_b[2..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
|
||||
(text "q_b[2..0]" (rect 211 83 253 96)(font "Arial" (font_size 8)))
|
||||
(line (pt 256 96)(pt 192 96)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(text "16 Word(s)" (rect 136 61 148 107)(font "Arial" )(vertical))
|
||||
(text "RAM" (rect 149 74 161 94)(font "Arial" )(vertical))
|
||||
(text "Block Type: AUTO" (rect 41 188 119 200)(font "Arial" ))
|
||||
(line (pt 128 24)(pt 168 24)(line_width 1))
|
||||
(line (pt 168 24)(pt 168 144)(line_width 1))
|
||||
(line (pt 168 144)(pt 128 144)(line_width 1))
|
||||
(line (pt 128 144)(pt 128 24)(line_width 1))
|
||||
(line (pt 112 27)(pt 120 27)(line_width 1))
|
||||
(line (pt 120 27)(pt 120 39)(line_width 1))
|
||||
(line (pt 120 39)(pt 112 39)(line_width 1))
|
||||
(line (pt 112 39)(pt 112 27)(line_width 1))
|
||||
(line (pt 112 34)(pt 114 36)(line_width 1))
|
||||
(line (pt 114 36)(pt 112 38)(line_width 1))
|
||||
(line (pt 92 36)(pt 112 36)(line_width 1))
|
||||
(line (pt 120 32)(pt 128 32)(line_width 3))
|
||||
(line (pt 112 43)(pt 120 43)(line_width 1))
|
||||
(line (pt 120 43)(pt 120 55)(line_width 1))
|
||||
(line (pt 120 55)(pt 112 55)(line_width 1))
|
||||
(line (pt 112 55)(pt 112 43)(line_width 1))
|
||||
(line (pt 112 50)(pt 114 52)(line_width 1))
|
||||
(line (pt 114 52)(pt 112 54)(line_width 1))
|
||||
(line (pt 92 52)(pt 112 52)(line_width 1))
|
||||
(line (pt 120 48)(pt 128 48)(line_width 3))
|
||||
(line (pt 112 59)(pt 120 59)(line_width 1))
|
||||
(line (pt 120 59)(pt 120 71)(line_width 1))
|
||||
(line (pt 120 71)(pt 112 71)(line_width 1))
|
||||
(line (pt 112 71)(pt 112 59)(line_width 1))
|
||||
(line (pt 112 66)(pt 114 68)(line_width 1))
|
||||
(line (pt 114 68)(pt 112 70)(line_width 1))
|
||||
(line (pt 92 68)(pt 112 68)(line_width 1))
|
||||
(line (pt 120 64)(pt 128 64)(line_width 1))
|
||||
(line (pt 112 91)(pt 120 91)(line_width 1))
|
||||
(line (pt 120 91)(pt 120 103)(line_width 1))
|
||||
(line (pt 120 103)(pt 112 103)(line_width 1))
|
||||
(line (pt 112 103)(pt 112 91)(line_width 1))
|
||||
(line (pt 112 98)(pt 114 100)(line_width 1))
|
||||
(line (pt 114 100)(pt 112 102)(line_width 1))
|
||||
(line (pt 104 100)(pt 112 100)(line_width 1))
|
||||
(line (pt 120 96)(pt 128 96)(line_width 3))
|
||||
(line (pt 112 107)(pt 120 107)(line_width 1))
|
||||
(line (pt 120 107)(pt 120 119)(line_width 1))
|
||||
(line (pt 120 119)(pt 112 119)(line_width 1))
|
||||
(line (pt 112 119)(pt 112 107)(line_width 1))
|
||||
(line (pt 112 114)(pt 114 116)(line_width 1))
|
||||
(line (pt 114 116)(pt 112 118)(line_width 1))
|
||||
(line (pt 104 116)(pt 112 116)(line_width 1))
|
||||
(line (pt 120 112)(pt 128 112)(line_width 3))
|
||||
(line (pt 112 123)(pt 120 123)(line_width 1))
|
||||
(line (pt 120 123)(pt 120 135)(line_width 1))
|
||||
(line (pt 120 135)(pt 112 135)(line_width 1))
|
||||
(line (pt 112 135)(pt 112 123)(line_width 1))
|
||||
(line (pt 112 130)(pt 114 132)(line_width 1))
|
||||
(line (pt 114 132)(pt 112 134)(line_width 1))
|
||||
(line (pt 104 132)(pt 112 132)(line_width 1))
|
||||
(line (pt 120 128)(pt 128 128)(line_width 1))
|
||||
(line (pt 92 36)(pt 92 161)(line_width 1))
|
||||
(line (pt 176 36)(pt 176 161)(line_width 1))
|
||||
(line (pt 104 100)(pt 104 177)(line_width 1))
|
||||
(line (pt 181 100)(pt 181 177)(line_width 1))
|
||||
(line (pt 184 27)(pt 192 27)(line_width 1))
|
||||
(line (pt 192 27)(pt 192 39)(line_width 1))
|
||||
(line (pt 192 39)(pt 184 39)(line_width 1))
|
||||
(line (pt 184 39)(pt 184 27)(line_width 1))
|
||||
(line (pt 184 34)(pt 186 36)(line_width 1))
|
||||
(line (pt 186 36)(pt 184 38)(line_width 1))
|
||||
(line (pt 176 36)(pt 184 36)(line_width 1))
|
||||
(line (pt 168 32)(pt 184 32)(line_width 3))
|
||||
(line (pt 184 91)(pt 192 91)(line_width 1))
|
||||
(line (pt 192 91)(pt 192 103)(line_width 1))
|
||||
(line (pt 192 103)(pt 184 103)(line_width 1))
|
||||
(line (pt 184 103)(pt 184 91)(line_width 1))
|
||||
(line (pt 184 98)(pt 186 100)(line_width 1))
|
||||
(line (pt 186 100)(pt 184 102)(line_width 1))
|
||||
(line (pt 181 100)(pt 184 100)(line_width 1))
|
||||
(line (pt 168 96)(pt 184 96)(line_width 3))
|
||||
)
|
||||
)
|
||||
31
FPGA_quartus_GE/altip_orig/altdpram0.inc
Normal file
31
FPGA_quartus_GE/altip_orig/altdpram0.inc
Normal file
@@ -0,0 +1,31 @@
|
||||
--Copyright (C) 1991-2008 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
FUNCTION altdpram0
|
||||
(
|
||||
address_a[3..0],
|
||||
address_b[3..0],
|
||||
clock_a,
|
||||
clock_b,
|
||||
data_a[2..0],
|
||||
data_b[2..0],
|
||||
wren_a,
|
||||
wren_b
|
||||
)
|
||||
|
||||
RETURNS (
|
||||
q_a[2..0],
|
||||
q_b[2..0]
|
||||
);
|
||||
6
FPGA_quartus_GE/altip_orig/altdpram0.qip
Normal file
6
FPGA_quartus_GE/altip_orig/altdpram0.qip
Normal file
@@ -0,0 +1,6 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "LPM_RAM_DP+"
|
||||
set_global_assignment -name IP_TOOL_VERSION "8.1"
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altdpram0.vhd"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram0.bsf"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram0.inc"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram0.cmp"]
|
||||
273
FPGA_quartus_GE/altip_orig/altdpram0.vhd
Normal file
273
FPGA_quartus_GE/altip_orig/altdpram0.vhd
Normal file
@@ -0,0 +1,273 @@
|
||||
-- megafunction wizard: %LPM_RAM_DP+%
|
||||
-- GENERATION: STANDARD
|
||||
-- VERSION: WM1.0
|
||||
-- MODULE: altsyncram
|
||||
|
||||
-- ============================================================
|
||||
-- File Name: altdpram0.vhd
|
||||
-- Megafunction Name(s):
|
||||
-- altsyncram
|
||||
--
|
||||
-- Simulation Library Files(s):
|
||||
-- altera_mf
|
||||
-- ============================================================
|
||||
-- ************************************************************
|
||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
--
|
||||
-- 8.1 Build 163 10/28/2008 SJ Web Edition
|
||||
-- ************************************************************
|
||||
|
||||
|
||||
--Copyright (C) 1991-2008 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
|
||||
LIBRARY altera_mf;
|
||||
USE altera_mf.all;
|
||||
|
||||
ENTITY altdpram0 IS
|
||||
PORT
|
||||
(
|
||||
address_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
|
||||
address_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
|
||||
clock_a : IN STD_LOGIC ;
|
||||
clock_b : IN STD_LOGIC ;
|
||||
data_a : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
|
||||
data_b : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
|
||||
wren_a : IN STD_LOGIC := '1';
|
||||
wren_b : IN STD_LOGIC := '1';
|
||||
q_a : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
|
||||
q_b : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
|
||||
);
|
||||
END altdpram0;
|
||||
|
||||
|
||||
ARCHITECTURE SYN OF altdpram0 IS
|
||||
|
||||
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (2 DOWNTO 0);
|
||||
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (2 DOWNTO 0);
|
||||
|
||||
|
||||
|
||||
COMPONENT altsyncram
|
||||
GENERIC (
|
||||
address_reg_b : STRING;
|
||||
clock_enable_input_a : STRING;
|
||||
clock_enable_input_b : STRING;
|
||||
clock_enable_output_a : STRING;
|
||||
clock_enable_output_b : STRING;
|
||||
indata_reg_b : STRING;
|
||||
intended_device_family : STRING;
|
||||
lpm_type : STRING;
|
||||
numwords_a : NATURAL;
|
||||
numwords_b : NATURAL;
|
||||
operation_mode : STRING;
|
||||
outdata_aclr_a : STRING;
|
||||
outdata_aclr_b : STRING;
|
||||
outdata_reg_a : STRING;
|
||||
outdata_reg_b : STRING;
|
||||
power_up_uninitialized : STRING;
|
||||
read_during_write_mode_port_a : STRING;
|
||||
read_during_write_mode_port_b : STRING;
|
||||
widthad_a : NATURAL;
|
||||
widthad_b : NATURAL;
|
||||
width_a : NATURAL;
|
||||
width_b : NATURAL;
|
||||
width_byteena_a : NATURAL;
|
||||
width_byteena_b : NATURAL;
|
||||
wrcontrol_wraddress_reg_b : STRING
|
||||
);
|
||||
PORT (
|
||||
wren_a : IN STD_LOGIC ;
|
||||
clock0 : IN STD_LOGIC ;
|
||||
wren_b : IN STD_LOGIC ;
|
||||
clock1 : IN STD_LOGIC ;
|
||||
address_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
|
||||
address_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
|
||||
q_a : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
|
||||
q_b : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
|
||||
data_a : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
|
||||
data_b : IN STD_LOGIC_VECTOR (2 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
BEGIN
|
||||
q_a <= sub_wire0(2 DOWNTO 0);
|
||||
q_b <= sub_wire1(2 DOWNTO 0);
|
||||
|
||||
altsyncram_component : altsyncram
|
||||
GENERIC MAP (
|
||||
address_reg_b => "CLOCK1",
|
||||
clock_enable_input_a => "BYPASS",
|
||||
clock_enable_input_b => "BYPASS",
|
||||
clock_enable_output_a => "BYPASS",
|
||||
clock_enable_output_b => "BYPASS",
|
||||
indata_reg_b => "CLOCK1",
|
||||
intended_device_family => "Cyclone III",
|
||||
lpm_type => "altsyncram",
|
||||
numwords_a => 16,
|
||||
numwords_b => 16,
|
||||
operation_mode => "BIDIR_DUAL_PORT",
|
||||
outdata_aclr_a => "NONE",
|
||||
outdata_aclr_b => "NONE",
|
||||
outdata_reg_a => "CLOCK0",
|
||||
outdata_reg_b => "CLOCK1",
|
||||
power_up_uninitialized => "FALSE",
|
||||
read_during_write_mode_port_a => "OLD_DATA",
|
||||
read_during_write_mode_port_b => "OLD_DATA",
|
||||
widthad_a => 4,
|
||||
widthad_b => 4,
|
||||
width_a => 3,
|
||||
width_b => 3,
|
||||
width_byteena_a => 1,
|
||||
width_byteena_b => 1,
|
||||
wrcontrol_wraddress_reg_b => "CLOCK1"
|
||||
)
|
||||
PORT MAP (
|
||||
wren_a => wren_a,
|
||||
clock0 => clock_a,
|
||||
wren_b => wren_b,
|
||||
clock1 => clock_b,
|
||||
address_a => address_a,
|
||||
address_b => address_b,
|
||||
data_a => data_a,
|
||||
data_b => data_b,
|
||||
q_a => sub_wire0,
|
||||
q_b => sub_wire1
|
||||
);
|
||||
|
||||
|
||||
|
||||
END SYN;
|
||||
|
||||
-- ============================================================
|
||||
-- CNX file retrieval info
|
||||
-- ============================================================
|
||||
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
|
||||
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: Clock NUMERIC "5"
|
||||
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: ECC NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
|
||||
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
|
||||
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "48"
|
||||
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: MIFfilename STRING ""
|
||||
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
|
||||
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
|
||||
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: REGq NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: REGrren NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "3"
|
||||
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "3"
|
||||
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "3"
|
||||
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "3"
|
||||
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: enable NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: rden NUMERIC "0"
|
||||
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
|
||||
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
|
||||
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
|
||||
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
|
||||
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
|
||||
-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
|
||||
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
|
||||
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16"
|
||||
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16"
|
||||
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
|
||||
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
|
||||
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
|
||||
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
|
||||
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
|
||||
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
|
||||
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "OLD_DATA"
|
||||
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "OLD_DATA"
|
||||
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "4"
|
||||
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "4"
|
||||
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "3"
|
||||
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "3"
|
||||
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
|
||||
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
|
||||
-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
|
||||
-- Retrieval info: USED_PORT: address_a 0 0 4 0 INPUT NODEFVAL address_a[3..0]
|
||||
-- Retrieval info: USED_PORT: address_b 0 0 4 0 INPUT NODEFVAL address_b[3..0]
|
||||
-- Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT NODEFVAL clock_a
|
||||
-- Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL clock_b
|
||||
-- Retrieval info: USED_PORT: data_a 0 0 3 0 INPUT NODEFVAL data_a[2..0]
|
||||
-- Retrieval info: USED_PORT: data_b 0 0 3 0 INPUT NODEFVAL data_b[2..0]
|
||||
-- Retrieval info: USED_PORT: q_a 0 0 3 0 OUTPUT NODEFVAL q_a[2..0]
|
||||
-- Retrieval info: USED_PORT: q_b 0 0 3 0 OUTPUT NODEFVAL q_b[2..0]
|
||||
-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a
|
||||
-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b
|
||||
-- Retrieval info: CONNECT: @data_a 0 0 3 0 data_a 0 0 3 0
|
||||
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
|
||||
-- Retrieval info: CONNECT: q_a 0 0 3 0 @q_a 0 0 3 0
|
||||
-- Retrieval info: CONNECT: q_b 0 0 3 0 @q_b 0 0 3 0
|
||||
-- Retrieval info: CONNECT: @address_a 0 0 4 0 address_a 0 0 4 0
|
||||
-- Retrieval info: CONNECT: @data_b 0 0 3 0 data_b 0 0 3 0
|
||||
-- Retrieval info: CONNECT: @address_b 0 0 4 0 address_b 0 0 4 0
|
||||
-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
|
||||
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0.vhd TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0.inc TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0.cmp TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0.bsf TRUE FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0_inst.vhd FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0_waveforms.html TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0_wave*.jpg FALSE
|
||||
-- Retrieval info: LIB_FILE: altera_mf
|
||||
173
FPGA_quartus_GE/altip_orig/altdpram1.bsf
Normal file
173
FPGA_quartus_GE/altip_orig/altdpram1.bsf
Normal file
@@ -0,0 +1,173 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2008 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 0 0 256 208)
|
||||
(text "altdpram1" (rect 100 1 167 17)(font "Arial" (font_size 10)))
|
||||
(text "inst" (rect 8 192 25 204)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "data_a[5..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
|
||||
(text "data_a[5..0]" (rect 4 19 61 32)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 32)(pt 112 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
(text "address_a[7..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
|
||||
(text "address_a[7..0]" (rect 4 35 75 48)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 48)(pt 112 48)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "wren_a" (rect 0 0 44 14)(font "Arial" (font_size 8)))
|
||||
(text "wren_a" (rect 4 51 38 64)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 64)(pt 112 64)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 96)
|
||||
(input)
|
||||
(text "data_b[5..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
|
||||
(text "data_b[5..0]" (rect 4 83 61 96)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 96)(pt 112 96)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 112)
|
||||
(input)
|
||||
(text "address_b[7..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
|
||||
(text "address_b[7..0]" (rect 4 99 75 112)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 112)(pt 112 112)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 128)
|
||||
(input)
|
||||
(text "wren_b" (rect 0 0 44 14)(font "Arial" (font_size 8)))
|
||||
(text "wren_b" (rect 4 115 38 128)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 128)(pt 112 128)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 160)
|
||||
(input)
|
||||
(text "clock_a" (rect 0 0 43 14)(font "Arial" (font_size 8)))
|
||||
(text "clock_a" (rect 4 147 39 160)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 160)(pt 176 160)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 176)
|
||||
(input)
|
||||
(text "clock_b" (rect 0 0 43 14)(font "Arial" (font_size 8)))
|
||||
(text "clock_b" (rect 4 163 39 176)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 176)(pt 181 176)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 256 32)
|
||||
(output)
|
||||
(text "q_a[5..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
|
||||
(text "q_a[5..0]" (rect 211 19 253 32)(font "Arial" (font_size 8)))
|
||||
(line (pt 256 32)(pt 192 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 256 96)
|
||||
(output)
|
||||
(text "q_b[5..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
|
||||
(text "q_b[5..0]" (rect 211 83 253 96)(font "Arial" (font_size 8)))
|
||||
(line (pt 256 96)(pt 192 96)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(text "256 Word(s)" (rect 136 58 148 109)(font "Arial" )(vertical))
|
||||
(text "RAM" (rect 149 74 161 94)(font "Arial" )(vertical))
|
||||
(text "Block Type: AUTO" (rect 41 188 119 200)(font "Arial" ))
|
||||
(line (pt 128 24)(pt 168 24)(line_width 1))
|
||||
(line (pt 168 24)(pt 168 144)(line_width 1))
|
||||
(line (pt 168 144)(pt 128 144)(line_width 1))
|
||||
(line (pt 128 144)(pt 128 24)(line_width 1))
|
||||
(line (pt 112 27)(pt 120 27)(line_width 1))
|
||||
(line (pt 120 27)(pt 120 39)(line_width 1))
|
||||
(line (pt 120 39)(pt 112 39)(line_width 1))
|
||||
(line (pt 112 39)(pt 112 27)(line_width 1))
|
||||
(line (pt 112 34)(pt 114 36)(line_width 1))
|
||||
(line (pt 114 36)(pt 112 38)(line_width 1))
|
||||
(line (pt 92 36)(pt 112 36)(line_width 1))
|
||||
(line (pt 120 32)(pt 128 32)(line_width 3))
|
||||
(line (pt 112 43)(pt 120 43)(line_width 1))
|
||||
(line (pt 120 43)(pt 120 55)(line_width 1))
|
||||
(line (pt 120 55)(pt 112 55)(line_width 1))
|
||||
(line (pt 112 55)(pt 112 43)(line_width 1))
|
||||
(line (pt 112 50)(pt 114 52)(line_width 1))
|
||||
(line (pt 114 52)(pt 112 54)(line_width 1))
|
||||
(line (pt 92 52)(pt 112 52)(line_width 1))
|
||||
(line (pt 120 48)(pt 128 48)(line_width 3))
|
||||
(line (pt 112 59)(pt 120 59)(line_width 1))
|
||||
(line (pt 120 59)(pt 120 71)(line_width 1))
|
||||
(line (pt 120 71)(pt 112 71)(line_width 1))
|
||||
(line (pt 112 71)(pt 112 59)(line_width 1))
|
||||
(line (pt 112 66)(pt 114 68)(line_width 1))
|
||||
(line (pt 114 68)(pt 112 70)(line_width 1))
|
||||
(line (pt 92 68)(pt 112 68)(line_width 1))
|
||||
(line (pt 120 64)(pt 128 64)(line_width 1))
|
||||
(line (pt 112 91)(pt 120 91)(line_width 1))
|
||||
(line (pt 120 91)(pt 120 103)(line_width 1))
|
||||
(line (pt 120 103)(pt 112 103)(line_width 1))
|
||||
(line (pt 112 103)(pt 112 91)(line_width 1))
|
||||
(line (pt 112 98)(pt 114 100)(line_width 1))
|
||||
(line (pt 114 100)(pt 112 102)(line_width 1))
|
||||
(line (pt 104 100)(pt 112 100)(line_width 1))
|
||||
(line (pt 120 96)(pt 128 96)(line_width 3))
|
||||
(line (pt 112 107)(pt 120 107)(line_width 1))
|
||||
(line (pt 120 107)(pt 120 119)(line_width 1))
|
||||
(line (pt 120 119)(pt 112 119)(line_width 1))
|
||||
(line (pt 112 119)(pt 112 107)(line_width 1))
|
||||
(line (pt 112 114)(pt 114 116)(line_width 1))
|
||||
(line (pt 114 116)(pt 112 118)(line_width 1))
|
||||
(line (pt 104 116)(pt 112 116)(line_width 1))
|
||||
(line (pt 120 112)(pt 128 112)(line_width 3))
|
||||
(line (pt 112 123)(pt 120 123)(line_width 1))
|
||||
(line (pt 120 123)(pt 120 135)(line_width 1))
|
||||
(line (pt 120 135)(pt 112 135)(line_width 1))
|
||||
(line (pt 112 135)(pt 112 123)(line_width 1))
|
||||
(line (pt 112 130)(pt 114 132)(line_width 1))
|
||||
(line (pt 114 132)(pt 112 134)(line_width 1))
|
||||
(line (pt 104 132)(pt 112 132)(line_width 1))
|
||||
(line (pt 120 128)(pt 128 128)(line_width 1))
|
||||
(line (pt 92 36)(pt 92 161)(line_width 1))
|
||||
(line (pt 176 36)(pt 176 161)(line_width 1))
|
||||
(line (pt 104 100)(pt 104 177)(line_width 1))
|
||||
(line (pt 181 100)(pt 181 177)(line_width 1))
|
||||
(line (pt 184 27)(pt 192 27)(line_width 1))
|
||||
(line (pt 192 27)(pt 192 39)(line_width 1))
|
||||
(line (pt 192 39)(pt 184 39)(line_width 1))
|
||||
(line (pt 184 39)(pt 184 27)(line_width 1))
|
||||
(line (pt 184 34)(pt 186 36)(line_width 1))
|
||||
(line (pt 186 36)(pt 184 38)(line_width 1))
|
||||
(line (pt 176 36)(pt 184 36)(line_width 1))
|
||||
(line (pt 168 32)(pt 184 32)(line_width 3))
|
||||
(line (pt 184 91)(pt 192 91)(line_width 1))
|
||||
(line (pt 192 91)(pt 192 103)(line_width 1))
|
||||
(line (pt 192 103)(pt 184 103)(line_width 1))
|
||||
(line (pt 184 103)(pt 184 91)(line_width 1))
|
||||
(line (pt 184 98)(pt 186 100)(line_width 1))
|
||||
(line (pt 186 100)(pt 184 102)(line_width 1))
|
||||
(line (pt 181 100)(pt 184 100)(line_width 1))
|
||||
(line (pt 168 96)(pt 184 96)(line_width 3))
|
||||
)
|
||||
)
|
||||
31
FPGA_quartus_GE/altip_orig/altdpram1.inc
Normal file
31
FPGA_quartus_GE/altip_orig/altdpram1.inc
Normal file
@@ -0,0 +1,31 @@
|
||||
--Copyright (C) 1991-2008 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
FUNCTION altdpram1
|
||||
(
|
||||
address_a[7..0],
|
||||
address_b[7..0],
|
||||
clock_a,
|
||||
clock_b,
|
||||
data_a[5..0],
|
||||
data_b[5..0],
|
||||
wren_a,
|
||||
wren_b
|
||||
)
|
||||
|
||||
RETURNS (
|
||||
q_a[5..0],
|
||||
q_b[5..0]
|
||||
);
|
||||
6
FPGA_quartus_GE/altip_orig/altdpram1.qip
Normal file
6
FPGA_quartus_GE/altip_orig/altdpram1.qip
Normal file
@@ -0,0 +1,6 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "LPM_RAM_DP+"
|
||||
set_global_assignment -name IP_TOOL_VERSION "8.1"
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altdpram1.vhd"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram1.bsf"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram1.inc"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram1.cmp"]
|
||||
273
FPGA_quartus_GE/altip_orig/altdpram1.vhd
Normal file
273
FPGA_quartus_GE/altip_orig/altdpram1.vhd
Normal file
@@ -0,0 +1,273 @@
|
||||
-- megafunction wizard: %LPM_RAM_DP+%
|
||||
-- GENERATION: STANDARD
|
||||
-- VERSION: WM1.0
|
||||
-- MODULE: altsyncram
|
||||
|
||||
-- ============================================================
|
||||
-- File Name: altdpram1.vhd
|
||||
-- Megafunction Name(s):
|
||||
-- altsyncram
|
||||
--
|
||||
-- Simulation Library Files(s):
|
||||
-- altera_mf
|
||||
-- ============================================================
|
||||
-- ************************************************************
|
||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
--
|
||||
-- 8.1 Build 163 10/28/2008 SJ Web Edition
|
||||
-- ************************************************************
|
||||
|
||||
|
||||
--Copyright (C) 1991-2008 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
|
||||
LIBRARY altera_mf;
|
||||
USE altera_mf.all;
|
||||
|
||||
ENTITY altdpram1 IS
|
||||
PORT
|
||||
(
|
||||
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
|
||||
address_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
|
||||
clock_a : IN STD_LOGIC ;
|
||||
clock_b : IN STD_LOGIC ;
|
||||
data_a : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
|
||||
data_b : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
|
||||
wren_a : IN STD_LOGIC := '1';
|
||||
wren_b : IN STD_LOGIC := '1';
|
||||
q_a : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
|
||||
q_b : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
|
||||
);
|
||||
END altdpram1;
|
||||
|
||||
|
||||
ARCHITECTURE SYN OF altdpram1 IS
|
||||
|
||||
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
|
||||
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (5 DOWNTO 0);
|
||||
|
||||
|
||||
|
||||
COMPONENT altsyncram
|
||||
GENERIC (
|
||||
address_reg_b : STRING;
|
||||
clock_enable_input_a : STRING;
|
||||
clock_enable_input_b : STRING;
|
||||
clock_enable_output_a : STRING;
|
||||
clock_enable_output_b : STRING;
|
||||
indata_reg_b : STRING;
|
||||
intended_device_family : STRING;
|
||||
lpm_type : STRING;
|
||||
numwords_a : NATURAL;
|
||||
numwords_b : NATURAL;
|
||||
operation_mode : STRING;
|
||||
outdata_aclr_a : STRING;
|
||||
outdata_aclr_b : STRING;
|
||||
outdata_reg_a : STRING;
|
||||
outdata_reg_b : STRING;
|
||||
power_up_uninitialized : STRING;
|
||||
read_during_write_mode_port_a : STRING;
|
||||
read_during_write_mode_port_b : STRING;
|
||||
widthad_a : NATURAL;
|
||||
widthad_b : NATURAL;
|
||||
width_a : NATURAL;
|
||||
width_b : NATURAL;
|
||||
width_byteena_a : NATURAL;
|
||||
width_byteena_b : NATURAL;
|
||||
wrcontrol_wraddress_reg_b : STRING
|
||||
);
|
||||
PORT (
|
||||
wren_a : IN STD_LOGIC ;
|
||||
clock0 : IN STD_LOGIC ;
|
||||
wren_b : IN STD_LOGIC ;
|
||||
clock1 : IN STD_LOGIC ;
|
||||
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
|
||||
address_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
|
||||
q_a : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
|
||||
q_b : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
|
||||
data_a : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
|
||||
data_b : IN STD_LOGIC_VECTOR (5 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
BEGIN
|
||||
q_a <= sub_wire0(5 DOWNTO 0);
|
||||
q_b <= sub_wire1(5 DOWNTO 0);
|
||||
|
||||
altsyncram_component : altsyncram
|
||||
GENERIC MAP (
|
||||
address_reg_b => "CLOCK1",
|
||||
clock_enable_input_a => "BYPASS",
|
||||
clock_enable_input_b => "BYPASS",
|
||||
clock_enable_output_a => "BYPASS",
|
||||
clock_enable_output_b => "BYPASS",
|
||||
indata_reg_b => "CLOCK1",
|
||||
intended_device_family => "Cyclone III",
|
||||
lpm_type => "altsyncram",
|
||||
numwords_a => 256,
|
||||
numwords_b => 256,
|
||||
operation_mode => "BIDIR_DUAL_PORT",
|
||||
outdata_aclr_a => "NONE",
|
||||
outdata_aclr_b => "NONE",
|
||||
outdata_reg_a => "CLOCK0",
|
||||
outdata_reg_b => "CLOCK1",
|
||||
power_up_uninitialized => "FALSE",
|
||||
read_during_write_mode_port_a => "OLD_DATA",
|
||||
read_during_write_mode_port_b => "OLD_DATA",
|
||||
widthad_a => 8,
|
||||
widthad_b => 8,
|
||||
width_a => 6,
|
||||
width_b => 6,
|
||||
width_byteena_a => 1,
|
||||
width_byteena_b => 1,
|
||||
wrcontrol_wraddress_reg_b => "CLOCK1"
|
||||
)
|
||||
PORT MAP (
|
||||
wren_a => wren_a,
|
||||
clock0 => clock_a,
|
||||
wren_b => wren_b,
|
||||
clock1 => clock_b,
|
||||
address_a => address_a,
|
||||
address_b => address_b,
|
||||
data_a => data_a,
|
||||
data_b => data_b,
|
||||
q_a => sub_wire0,
|
||||
q_b => sub_wire1
|
||||
);
|
||||
|
||||
|
||||
|
||||
END SYN;
|
||||
|
||||
-- ============================================================
|
||||
-- CNX file retrieval info
|
||||
-- ============================================================
|
||||
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
|
||||
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: Clock NUMERIC "5"
|
||||
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: ECC NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
|
||||
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
|
||||
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "1536"
|
||||
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: MIFfilename STRING ""
|
||||
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
|
||||
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
|
||||
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: REGq NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: REGrren NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "6"
|
||||
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "6"
|
||||
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "6"
|
||||
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "6"
|
||||
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: enable NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: rden NUMERIC "0"
|
||||
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
|
||||
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
|
||||
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
|
||||
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
|
||||
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
|
||||
-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
|
||||
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
|
||||
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
|
||||
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256"
|
||||
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
|
||||
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
|
||||
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
|
||||
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
|
||||
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
|
||||
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
|
||||
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "OLD_DATA"
|
||||
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "OLD_DATA"
|
||||
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
|
||||
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8"
|
||||
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "6"
|
||||
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "6"
|
||||
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
|
||||
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
|
||||
-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
|
||||
-- Retrieval info: USED_PORT: address_a 0 0 8 0 INPUT NODEFVAL address_a[7..0]
|
||||
-- Retrieval info: USED_PORT: address_b 0 0 8 0 INPUT NODEFVAL address_b[7..0]
|
||||
-- Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT NODEFVAL clock_a
|
||||
-- Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL clock_b
|
||||
-- Retrieval info: USED_PORT: data_a 0 0 6 0 INPUT NODEFVAL data_a[5..0]
|
||||
-- Retrieval info: USED_PORT: data_b 0 0 6 0 INPUT NODEFVAL data_b[5..0]
|
||||
-- Retrieval info: USED_PORT: q_a 0 0 6 0 OUTPUT NODEFVAL q_a[5..0]
|
||||
-- Retrieval info: USED_PORT: q_b 0 0 6 0 OUTPUT NODEFVAL q_b[5..0]
|
||||
-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a
|
||||
-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b
|
||||
-- Retrieval info: CONNECT: @data_a 0 0 6 0 data_a 0 0 6 0
|
||||
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
|
||||
-- Retrieval info: CONNECT: q_a 0 0 6 0 @q_a 0 0 6 0
|
||||
-- Retrieval info: CONNECT: q_b 0 0 6 0 @q_b 0 0 6 0
|
||||
-- Retrieval info: CONNECT: @address_a 0 0 8 0 address_a 0 0 8 0
|
||||
-- Retrieval info: CONNECT: @data_b 0 0 6 0 data_b 0 0 6 0
|
||||
-- Retrieval info: CONNECT: @address_b 0 0 8 0 address_b 0 0 8 0
|
||||
-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
|
||||
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1.vhd TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1.inc TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1.cmp TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1.bsf TRUE FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1_inst.vhd FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1_waveforms.html TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1_wave*.jpg FALSE
|
||||
-- Retrieval info: LIB_FILE: altera_mf
|
||||
173
FPGA_quartus_GE/altip_orig/altdpram2.bsf
Normal file
173
FPGA_quartus_GE/altip_orig/altdpram2.bsf
Normal file
@@ -0,0 +1,173 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2008 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 0 0 256 208)
|
||||
(text "altdpram2" (rect 100 1 167 17)(font "Arial" (font_size 10)))
|
||||
(text "inst" (rect 8 192 25 204)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "data_a[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
|
||||
(text "data_a[7..0]" (rect 4 19 61 32)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 32)(pt 112 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
(text "address_a[7..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
|
||||
(text "address_a[7..0]" (rect 4 35 75 48)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 48)(pt 112 48)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "wren_a" (rect 0 0 44 14)(font "Arial" (font_size 8)))
|
||||
(text "wren_a" (rect 4 51 38 64)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 64)(pt 112 64)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 96)
|
||||
(input)
|
||||
(text "data_b[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
|
||||
(text "data_b[7..0]" (rect 4 83 61 96)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 96)(pt 112 96)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 112)
|
||||
(input)
|
||||
(text "address_b[7..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
|
||||
(text "address_b[7..0]" (rect 4 99 75 112)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 112)(pt 112 112)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 128)
|
||||
(input)
|
||||
(text "wren_b" (rect 0 0 44 14)(font "Arial" (font_size 8)))
|
||||
(text "wren_b" (rect 4 115 38 128)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 128)(pt 112 128)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 160)
|
||||
(input)
|
||||
(text "clock_a" (rect 0 0 43 14)(font "Arial" (font_size 8)))
|
||||
(text "clock_a" (rect 4 147 39 160)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 160)(pt 176 160)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 176)
|
||||
(input)
|
||||
(text "clock_b" (rect 0 0 43 14)(font "Arial" (font_size 8)))
|
||||
(text "clock_b" (rect 4 163 39 176)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 176)(pt 181 176)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 256 32)
|
||||
(output)
|
||||
(text "q_a[7..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
|
||||
(text "q_a[7..0]" (rect 211 19 253 32)(font "Arial" (font_size 8)))
|
||||
(line (pt 256 32)(pt 192 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 256 96)
|
||||
(output)
|
||||
(text "q_b[7..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
|
||||
(text "q_b[7..0]" (rect 211 83 253 96)(font "Arial" (font_size 8)))
|
||||
(line (pt 256 96)(pt 192 96)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(text "256 Word(s)" (rect 136 58 148 109)(font "Arial" )(vertical))
|
||||
(text "RAM" (rect 149 74 161 94)(font "Arial" )(vertical))
|
||||
(text "Block Type: AUTO" (rect 41 188 119 200)(font "Arial" ))
|
||||
(line (pt 128 24)(pt 168 24)(line_width 1))
|
||||
(line (pt 168 24)(pt 168 144)(line_width 1))
|
||||
(line (pt 168 144)(pt 128 144)(line_width 1))
|
||||
(line (pt 128 144)(pt 128 24)(line_width 1))
|
||||
(line (pt 112 27)(pt 120 27)(line_width 1))
|
||||
(line (pt 120 27)(pt 120 39)(line_width 1))
|
||||
(line (pt 120 39)(pt 112 39)(line_width 1))
|
||||
(line (pt 112 39)(pt 112 27)(line_width 1))
|
||||
(line (pt 112 34)(pt 114 36)(line_width 1))
|
||||
(line (pt 114 36)(pt 112 38)(line_width 1))
|
||||
(line (pt 92 36)(pt 112 36)(line_width 1))
|
||||
(line (pt 120 32)(pt 128 32)(line_width 3))
|
||||
(line (pt 112 43)(pt 120 43)(line_width 1))
|
||||
(line (pt 120 43)(pt 120 55)(line_width 1))
|
||||
(line (pt 120 55)(pt 112 55)(line_width 1))
|
||||
(line (pt 112 55)(pt 112 43)(line_width 1))
|
||||
(line (pt 112 50)(pt 114 52)(line_width 1))
|
||||
(line (pt 114 52)(pt 112 54)(line_width 1))
|
||||
(line (pt 92 52)(pt 112 52)(line_width 1))
|
||||
(line (pt 120 48)(pt 128 48)(line_width 3))
|
||||
(line (pt 112 59)(pt 120 59)(line_width 1))
|
||||
(line (pt 120 59)(pt 120 71)(line_width 1))
|
||||
(line (pt 120 71)(pt 112 71)(line_width 1))
|
||||
(line (pt 112 71)(pt 112 59)(line_width 1))
|
||||
(line (pt 112 66)(pt 114 68)(line_width 1))
|
||||
(line (pt 114 68)(pt 112 70)(line_width 1))
|
||||
(line (pt 92 68)(pt 112 68)(line_width 1))
|
||||
(line (pt 120 64)(pt 128 64)(line_width 1))
|
||||
(line (pt 112 91)(pt 120 91)(line_width 1))
|
||||
(line (pt 120 91)(pt 120 103)(line_width 1))
|
||||
(line (pt 120 103)(pt 112 103)(line_width 1))
|
||||
(line (pt 112 103)(pt 112 91)(line_width 1))
|
||||
(line (pt 112 98)(pt 114 100)(line_width 1))
|
||||
(line (pt 114 100)(pt 112 102)(line_width 1))
|
||||
(line (pt 104 100)(pt 112 100)(line_width 1))
|
||||
(line (pt 120 96)(pt 128 96)(line_width 3))
|
||||
(line (pt 112 107)(pt 120 107)(line_width 1))
|
||||
(line (pt 120 107)(pt 120 119)(line_width 1))
|
||||
(line (pt 120 119)(pt 112 119)(line_width 1))
|
||||
(line (pt 112 119)(pt 112 107)(line_width 1))
|
||||
(line (pt 112 114)(pt 114 116)(line_width 1))
|
||||
(line (pt 114 116)(pt 112 118)(line_width 1))
|
||||
(line (pt 104 116)(pt 112 116)(line_width 1))
|
||||
(line (pt 120 112)(pt 128 112)(line_width 3))
|
||||
(line (pt 112 123)(pt 120 123)(line_width 1))
|
||||
(line (pt 120 123)(pt 120 135)(line_width 1))
|
||||
(line (pt 120 135)(pt 112 135)(line_width 1))
|
||||
(line (pt 112 135)(pt 112 123)(line_width 1))
|
||||
(line (pt 112 130)(pt 114 132)(line_width 1))
|
||||
(line (pt 114 132)(pt 112 134)(line_width 1))
|
||||
(line (pt 104 132)(pt 112 132)(line_width 1))
|
||||
(line (pt 120 128)(pt 128 128)(line_width 1))
|
||||
(line (pt 92 36)(pt 92 161)(line_width 1))
|
||||
(line (pt 176 36)(pt 176 161)(line_width 1))
|
||||
(line (pt 104 100)(pt 104 177)(line_width 1))
|
||||
(line (pt 181 100)(pt 181 177)(line_width 1))
|
||||
(line (pt 184 27)(pt 192 27)(line_width 1))
|
||||
(line (pt 192 27)(pt 192 39)(line_width 1))
|
||||
(line (pt 192 39)(pt 184 39)(line_width 1))
|
||||
(line (pt 184 39)(pt 184 27)(line_width 1))
|
||||
(line (pt 184 34)(pt 186 36)(line_width 1))
|
||||
(line (pt 186 36)(pt 184 38)(line_width 1))
|
||||
(line (pt 176 36)(pt 184 36)(line_width 1))
|
||||
(line (pt 168 32)(pt 184 32)(line_width 3))
|
||||
(line (pt 184 91)(pt 192 91)(line_width 1))
|
||||
(line (pt 192 91)(pt 192 103)(line_width 1))
|
||||
(line (pt 192 103)(pt 184 103)(line_width 1))
|
||||
(line (pt 184 103)(pt 184 91)(line_width 1))
|
||||
(line (pt 184 98)(pt 186 100)(line_width 1))
|
||||
(line (pt 186 100)(pt 184 102)(line_width 1))
|
||||
(line (pt 181 100)(pt 184 100)(line_width 1))
|
||||
(line (pt 168 96)(pt 184 96)(line_width 3))
|
||||
)
|
||||
)
|
||||
31
FPGA_quartus_GE/altip_orig/altdpram2.inc
Normal file
31
FPGA_quartus_GE/altip_orig/altdpram2.inc
Normal file
@@ -0,0 +1,31 @@
|
||||
--Copyright (C) 1991-2008 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
FUNCTION altdpram2
|
||||
(
|
||||
address_a[7..0],
|
||||
address_b[7..0],
|
||||
clock_a,
|
||||
clock_b,
|
||||
data_a[7..0],
|
||||
data_b[7..0],
|
||||
wren_a,
|
||||
wren_b
|
||||
)
|
||||
|
||||
RETURNS (
|
||||
q_a[7..0],
|
||||
q_b[7..0]
|
||||
);
|
||||
6
FPGA_quartus_GE/altip_orig/altdpram2.qip
Normal file
6
FPGA_quartus_GE/altip_orig/altdpram2.qip
Normal file
@@ -0,0 +1,6 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "LPM_RAM_DP+"
|
||||
set_global_assignment -name IP_TOOL_VERSION "8.1"
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altdpram2.vhd"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram2.bsf"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram2.inc"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram2.cmp"]
|
||||
273
FPGA_quartus_GE/altip_orig/altdpram2.vhd
Normal file
273
FPGA_quartus_GE/altip_orig/altdpram2.vhd
Normal file
@@ -0,0 +1,273 @@
|
||||
-- megafunction wizard: %LPM_RAM_DP+%
|
||||
-- GENERATION: STANDARD
|
||||
-- VERSION: WM1.0
|
||||
-- MODULE: altsyncram
|
||||
|
||||
-- ============================================================
|
||||
-- File Name: altdpram2.vhd
|
||||
-- Megafunction Name(s):
|
||||
-- altsyncram
|
||||
--
|
||||
-- Simulation Library Files(s):
|
||||
-- altera_mf
|
||||
-- ============================================================
|
||||
-- ************************************************************
|
||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
--
|
||||
-- 8.1 Build 163 10/28/2008 SJ Web Edition
|
||||
-- ************************************************************
|
||||
|
||||
|
||||
--Copyright (C) 1991-2008 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
|
||||
LIBRARY altera_mf;
|
||||
USE altera_mf.all;
|
||||
|
||||
ENTITY altdpram2 IS
|
||||
PORT
|
||||
(
|
||||
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
|
||||
address_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
|
||||
clock_a : IN STD_LOGIC ;
|
||||
clock_b : IN STD_LOGIC ;
|
||||
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
|
||||
data_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
|
||||
wren_a : IN STD_LOGIC := '1';
|
||||
wren_b : IN STD_LOGIC := '1';
|
||||
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
|
||||
q_b : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
|
||||
);
|
||||
END altdpram2;
|
||||
|
||||
|
||||
ARCHITECTURE SYN OF altdpram2 IS
|
||||
|
||||
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
|
||||
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (7 DOWNTO 0);
|
||||
|
||||
|
||||
|
||||
COMPONENT altsyncram
|
||||
GENERIC (
|
||||
address_reg_b : STRING;
|
||||
clock_enable_input_a : STRING;
|
||||
clock_enable_input_b : STRING;
|
||||
clock_enable_output_a : STRING;
|
||||
clock_enable_output_b : STRING;
|
||||
indata_reg_b : STRING;
|
||||
intended_device_family : STRING;
|
||||
lpm_type : STRING;
|
||||
numwords_a : NATURAL;
|
||||
numwords_b : NATURAL;
|
||||
operation_mode : STRING;
|
||||
outdata_aclr_a : STRING;
|
||||
outdata_aclr_b : STRING;
|
||||
outdata_reg_a : STRING;
|
||||
outdata_reg_b : STRING;
|
||||
power_up_uninitialized : STRING;
|
||||
read_during_write_mode_port_a : STRING;
|
||||
read_during_write_mode_port_b : STRING;
|
||||
widthad_a : NATURAL;
|
||||
widthad_b : NATURAL;
|
||||
width_a : NATURAL;
|
||||
width_b : NATURAL;
|
||||
width_byteena_a : NATURAL;
|
||||
width_byteena_b : NATURAL;
|
||||
wrcontrol_wraddress_reg_b : STRING
|
||||
);
|
||||
PORT (
|
||||
wren_a : IN STD_LOGIC ;
|
||||
clock0 : IN STD_LOGIC ;
|
||||
wren_b : IN STD_LOGIC ;
|
||||
clock1 : IN STD_LOGIC ;
|
||||
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
|
||||
address_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
|
||||
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
|
||||
q_b : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
|
||||
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
|
||||
data_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
BEGIN
|
||||
q_a <= sub_wire0(7 DOWNTO 0);
|
||||
q_b <= sub_wire1(7 DOWNTO 0);
|
||||
|
||||
altsyncram_component : altsyncram
|
||||
GENERIC MAP (
|
||||
address_reg_b => "CLOCK1",
|
||||
clock_enable_input_a => "BYPASS",
|
||||
clock_enable_input_b => "BYPASS",
|
||||
clock_enable_output_a => "BYPASS",
|
||||
clock_enable_output_b => "BYPASS",
|
||||
indata_reg_b => "CLOCK1",
|
||||
intended_device_family => "Cyclone III",
|
||||
lpm_type => "altsyncram",
|
||||
numwords_a => 256,
|
||||
numwords_b => 256,
|
||||
operation_mode => "BIDIR_DUAL_PORT",
|
||||
outdata_aclr_a => "NONE",
|
||||
outdata_aclr_b => "NONE",
|
||||
outdata_reg_a => "CLOCK0",
|
||||
outdata_reg_b => "CLOCK1",
|
||||
power_up_uninitialized => "FALSE",
|
||||
read_during_write_mode_port_a => "OLD_DATA",
|
||||
read_during_write_mode_port_b => "OLD_DATA",
|
||||
widthad_a => 8,
|
||||
widthad_b => 8,
|
||||
width_a => 8,
|
||||
width_b => 8,
|
||||
width_byteena_a => 1,
|
||||
width_byteena_b => 1,
|
||||
wrcontrol_wraddress_reg_b => "CLOCK1"
|
||||
)
|
||||
PORT MAP (
|
||||
wren_a => wren_a,
|
||||
clock0 => clock_a,
|
||||
wren_b => wren_b,
|
||||
clock1 => clock_b,
|
||||
address_a => address_a,
|
||||
address_b => address_b,
|
||||
data_a => data_a,
|
||||
data_b => data_b,
|
||||
q_a => sub_wire0,
|
||||
q_b => sub_wire1
|
||||
);
|
||||
|
||||
|
||||
|
||||
END SYN;
|
||||
|
||||
-- ============================================================
|
||||
-- CNX file retrieval info
|
||||
-- ============================================================
|
||||
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
|
||||
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: Clock NUMERIC "5"
|
||||
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: ECC NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
|
||||
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
|
||||
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "2048"
|
||||
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: MIFfilename STRING ""
|
||||
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
|
||||
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
|
||||
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: REGq NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: REGrren NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
|
||||
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
|
||||
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
|
||||
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
|
||||
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: enable NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: rden NUMERIC "0"
|
||||
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
|
||||
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
|
||||
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
|
||||
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
|
||||
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
|
||||
-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
|
||||
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
|
||||
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
|
||||
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256"
|
||||
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
|
||||
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
|
||||
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
|
||||
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
|
||||
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
|
||||
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
|
||||
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "OLD_DATA"
|
||||
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "OLD_DATA"
|
||||
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
|
||||
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8"
|
||||
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
|
||||
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
|
||||
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
|
||||
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
|
||||
-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
|
||||
-- Retrieval info: USED_PORT: address_a 0 0 8 0 INPUT NODEFVAL address_a[7..0]
|
||||
-- Retrieval info: USED_PORT: address_b 0 0 8 0 INPUT NODEFVAL address_b[7..0]
|
||||
-- Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT NODEFVAL clock_a
|
||||
-- Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL clock_b
|
||||
-- Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL data_a[7..0]
|
||||
-- Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL data_b[7..0]
|
||||
-- Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL q_a[7..0]
|
||||
-- Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL q_b[7..0]
|
||||
-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a
|
||||
-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b
|
||||
-- Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0
|
||||
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
|
||||
-- Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0
|
||||
-- Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0
|
||||
-- Retrieval info: CONNECT: @address_a 0 0 8 0 address_a 0 0 8 0
|
||||
-- Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0
|
||||
-- Retrieval info: CONNECT: @address_b 0 0 8 0 address_b 0 0 8 0
|
||||
-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
|
||||
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2.vhd TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2.inc TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2.cmp TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2.bsf TRUE FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2_inst.vhd FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2_waveforms.html TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2_wave*.jpg FALSE
|
||||
-- Retrieval info: LIB_FILE: altera_mf
|
||||
117
FPGA_quartus_GE/altip_orig/altpll0.bsf
Normal file
117
FPGA_quartus_GE/altip_orig/altpll0.bsf
Normal file
@@ -0,0 +1,117 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2010 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 0 0 280 248)
|
||||
(text "altpll0" (rect 120 1 167 20)(font "Arial" (font_size 10)))
|
||||
(text "inst" (rect 8 229 31 244)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 72)
|
||||
(input)
|
||||
(text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8)))
|
||||
(text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 72)(pt 48 72)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 280 72)
|
||||
(output)
|
||||
(text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8)))
|
||||
(text "c0" (rect 263 56 277 72)(font "Arial" (font_size 8)))
|
||||
(line (pt 280 72)(pt 248 72)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 280 96)
|
||||
(output)
|
||||
(text "c1" (rect 0 0 16 16)(font "Arial" (font_size 8)))
|
||||
(text "c1" (rect 263 80 277 96)(font "Arial" (font_size 8)))
|
||||
(line (pt 280 96)(pt 248 96)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 280 120)
|
||||
(output)
|
||||
(text "c2" (rect 0 0 16 16)(font "Arial" (font_size 8)))
|
||||
(text "c2" (rect 263 104 277 120)(font "Arial" (font_size 8)))
|
||||
(line (pt 280 120)(pt 248 120)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 280 144)
|
||||
(output)
|
||||
(text "c3" (rect 0 0 16 16)(font "Arial" (font_size 8)))
|
||||
(text "c3" (rect 263 128 277 144)(font "Arial" (font_size 8)))
|
||||
(line (pt 280 144)(pt 248 144)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 280 168)
|
||||
(output)
|
||||
(text "c4" (rect 0 0 16 16)(font "Arial" (font_size 8)))
|
||||
(text "c4" (rect 263 152 277 168)(font "Arial" (font_size 8)))
|
||||
(line (pt 280 168)(pt 248 168)(line_width 1))
|
||||
)
|
||||
(drawing
|
||||
(text "Cyclone III" (rect 205 230 253 244)(font "Arial" ))
|
||||
(text "inclk0 frequency: 33.000 MHz" (rect 58 67 201 81)(font "Arial" ))
|
||||
(text "Operation Mode: Normal" (rect 58 84 173 98)(font "Arial" ))
|
||||
(text "Clk " (rect 59 111 76 125)(font "Arial" ))
|
||||
(text "Ratio" (rect 90 111 114 125)(font "Arial" ))
|
||||
(text "Ph (dg)" (rect 128 111 163 125)(font "Arial" ))
|
||||
(text "DC (%)" (rect 173 111 208 125)(font "Arial" ))
|
||||
(text "c0" (rect 63 129 75 143)(font "Arial" ))
|
||||
(text "16/11" (rect 89 129 116 143)(font "Arial" ))
|
||||
(text "0.00" (rect 136 129 157 143)(font "Arial" ))
|
||||
(text "50.00" (rect 178 129 205 143)(font "Arial" ))
|
||||
(text "c1" (rect 63 147 75 161)(font "Arial" ))
|
||||
(text "50/11" (rect 89 147 116 161)(font "Arial" ))
|
||||
(text "0.00" (rect 136 147 157 161)(font "Arial" ))
|
||||
(text "50.00" (rect 178 147 205 161)(font "Arial" ))
|
||||
(text "c2" (rect 63 165 75 179)(font "Arial" ))
|
||||
(text "40/11" (rect 89 165 116 179)(font "Arial" ))
|
||||
(text "0.00" (rect 136 165 157 179)(font "Arial" ))
|
||||
(text "50.00" (rect 178 165 205 179)(font "Arial" ))
|
||||
(text "c3" (rect 63 183 75 197)(font "Arial" ))
|
||||
(text "109/33" (rect 85 183 118 197)(font "Arial" ))
|
||||
(text "0.00" (rect 136 183 157 197)(font "Arial" ))
|
||||
(text "50.00" (rect 178 183 205 197)(font "Arial" ))
|
||||
(text "c4" (rect 63 201 75 215)(font "Arial" ))
|
||||
(text "109/39" (rect 85 201 118 215)(font "Arial" ))
|
||||
(text "0.00" (rect 136 201 157 215)(font "Arial" ))
|
||||
(text "50.00" (rect 178 201 205 215)(font "Arial" ))
|
||||
(line (pt 0 0)(pt 281 0)(line_width 1))
|
||||
(line (pt 281 0)(pt 281 249)(line_width 1))
|
||||
(line (pt 0 249)(pt 281 249)(line_width 1))
|
||||
(line (pt 0 0)(pt 0 249)(line_width 1))
|
||||
(line (pt 56 108)(pt 215 108)(line_width 1))
|
||||
(line (pt 56 125)(pt 215 125)(line_width 1))
|
||||
(line (pt 56 143)(pt 215 143)(line_width 1))
|
||||
(line (pt 56 161)(pt 215 161)(line_width 1))
|
||||
(line (pt 56 179)(pt 215 179)(line_width 1))
|
||||
(line (pt 56 197)(pt 215 197)(line_width 1))
|
||||
(line (pt 56 215)(pt 215 215)(line_width 1))
|
||||
(line (pt 56 108)(pt 56 215)(line_width 1))
|
||||
(line (pt 82 108)(pt 82 215)(line_width 3))
|
||||
(line (pt 125 108)(pt 125 215)(line_width 3))
|
||||
(line (pt 170 108)(pt 170 215)(line_width 3))
|
||||
(line (pt 214 108)(pt 214 215)(line_width 1))
|
||||
(line (pt 48 56)(pt 248 56)(line_width 1))
|
||||
(line (pt 248 56)(pt 248 232)(line_width 1))
|
||||
(line (pt 48 232)(pt 248 232)(line_width 1))
|
||||
(line (pt 48 56)(pt 48 232)(line_width 1))
|
||||
)
|
||||
)
|
||||
27
FPGA_quartus_GE/altip_orig/altpll0.inc
Normal file
27
FPGA_quartus_GE/altip_orig/altpll0.inc
Normal file
@@ -0,0 +1,27 @@
|
||||
--Copyright (C) 1991-2010 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
FUNCTION altpll0
|
||||
(
|
||||
inclk0
|
||||
)
|
||||
|
||||
RETURNS (
|
||||
c0,
|
||||
c1,
|
||||
c2,
|
||||
c3,
|
||||
c4
|
||||
);
|
||||
13
FPGA_quartus_GE/altip_orig/altpll0.ppf
Normal file
13
FPGA_quartus_GE/altip_orig/altpll0.ppf
Normal file
@@ -0,0 +1,13 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<!DOCTYPE pinplan>
|
||||
<pinplan intended_family="Cyclone III" variation_name="altpll0" megafunction_name="ALTPLL" specifies="all_ports">
|
||||
<global>
|
||||
<pin name="inclk0" direction="input" scope="external" source="clock" />
|
||||
<pin name="c0" direction="output" scope="external" source="clock" />
|
||||
<pin name="c1" direction="output" scope="external" source="clock" />
|
||||
<pin name="c2" direction="output" scope="external" source="clock" />
|
||||
<pin name="c3" direction="output" scope="external" source="clock" />
|
||||
<pin name="c4" direction="output" scope="external" source="clock" />
|
||||
|
||||
</global>
|
||||
</pinplan>
|
||||
7
FPGA_quartus_GE/altip_orig/altpll0.qip
Normal file
7
FPGA_quartus_GE/altip_orig/altpll0.qip
Normal file
@@ -0,0 +1,7 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
|
||||
set_global_assignment -name IP_TOOL_VERSION "9.1"
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll0.vhd"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll0.bsf"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll0.inc"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll0.cmp"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll0.ppf"]
|
||||
477
FPGA_quartus_GE/altip_orig/altpll0.vhd
Normal file
477
FPGA_quartus_GE/altip_orig/altpll0.vhd
Normal file
@@ -0,0 +1,477 @@
|
||||
-- megafunction wizard: %ALTPLL%
|
||||
-- GENERATION: STANDARD
|
||||
-- VERSION: WM1.0
|
||||
-- MODULE: altpll
|
||||
|
||||
-- ============================================================
|
||||
-- File Name: altpll0.vhd
|
||||
-- Megafunction Name(s):
|
||||
-- altpll
|
||||
--
|
||||
-- Simulation Library Files(s):
|
||||
-- altera_mf
|
||||
-- ============================================================
|
||||
-- ************************************************************
|
||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
--
|
||||
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
|
||||
-- ************************************************************
|
||||
|
||||
|
||||
--Copyright (C) 1991-2010 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
|
||||
LIBRARY altera_mf;
|
||||
USE altera_mf.all;
|
||||
|
||||
ENTITY altpll0 IS
|
||||
PORT
|
||||
(
|
||||
inclk0 : IN STD_LOGIC := '0';
|
||||
c0 : OUT STD_LOGIC ;
|
||||
c1 : OUT STD_LOGIC ;
|
||||
c2 : OUT STD_LOGIC ;
|
||||
c3 : OUT STD_LOGIC ;
|
||||
c4 : OUT STD_LOGIC
|
||||
);
|
||||
END altpll0;
|
||||
|
||||
|
||||
ARCHITECTURE SYN OF altpll0 IS
|
||||
|
||||
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
|
||||
SIGNAL sub_wire1 : STD_LOGIC ;
|
||||
SIGNAL sub_wire2 : STD_LOGIC ;
|
||||
SIGNAL sub_wire3 : STD_LOGIC ;
|
||||
SIGNAL sub_wire4 : STD_LOGIC ;
|
||||
SIGNAL sub_wire5 : STD_LOGIC ;
|
||||
SIGNAL sub_wire6 : STD_LOGIC ;
|
||||
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (1 DOWNTO 0);
|
||||
SIGNAL sub_wire8_bv : BIT_VECTOR (0 DOWNTO 0);
|
||||
SIGNAL sub_wire8 : STD_LOGIC_VECTOR (0 DOWNTO 0);
|
||||
|
||||
|
||||
|
||||
COMPONENT altpll
|
||||
GENERIC (
|
||||
bandwidth_type : STRING;
|
||||
clk0_divide_by : NATURAL;
|
||||
clk0_duty_cycle : NATURAL;
|
||||
clk0_multiply_by : NATURAL;
|
||||
clk0_phase_shift : STRING;
|
||||
clk1_divide_by : NATURAL;
|
||||
clk1_duty_cycle : NATURAL;
|
||||
clk1_multiply_by : NATURAL;
|
||||
clk1_phase_shift : STRING;
|
||||
clk2_divide_by : NATURAL;
|
||||
clk2_duty_cycle : NATURAL;
|
||||
clk2_multiply_by : NATURAL;
|
||||
clk2_phase_shift : STRING;
|
||||
clk3_divide_by : NATURAL;
|
||||
clk3_duty_cycle : NATURAL;
|
||||
clk3_multiply_by : NATURAL;
|
||||
clk3_phase_shift : STRING;
|
||||
clk4_divide_by : NATURAL;
|
||||
clk4_duty_cycle : NATURAL;
|
||||
clk4_multiply_by : NATURAL;
|
||||
clk4_phase_shift : STRING;
|
||||
compensate_clock : STRING;
|
||||
inclk0_input_frequency : NATURAL;
|
||||
intended_device_family : STRING;
|
||||
lpm_type : STRING;
|
||||
operation_mode : STRING;
|
||||
pll_type : STRING;
|
||||
port_activeclock : STRING;
|
||||
port_areset : STRING;
|
||||
port_clkbad0 : STRING;
|
||||
port_clkbad1 : STRING;
|
||||
port_clkloss : STRING;
|
||||
port_clkswitch : STRING;
|
||||
port_configupdate : STRING;
|
||||
port_fbin : STRING;
|
||||
port_inclk0 : STRING;
|
||||
port_inclk1 : STRING;
|
||||
port_locked : STRING;
|
||||
port_pfdena : STRING;
|
||||
port_phasecounterselect : STRING;
|
||||
port_phasedone : STRING;
|
||||
port_phasestep : STRING;
|
||||
port_phaseupdown : STRING;
|
||||
port_pllena : STRING;
|
||||
port_scanaclr : STRING;
|
||||
port_scanclk : STRING;
|
||||
port_scanclkena : STRING;
|
||||
port_scandata : STRING;
|
||||
port_scandataout : STRING;
|
||||
port_scandone : STRING;
|
||||
port_scanread : STRING;
|
||||
port_scanwrite : STRING;
|
||||
port_clk0 : STRING;
|
||||
port_clk1 : STRING;
|
||||
port_clk2 : STRING;
|
||||
port_clk3 : STRING;
|
||||
port_clk4 : STRING;
|
||||
port_clk5 : STRING;
|
||||
port_clkena0 : STRING;
|
||||
port_clkena1 : STRING;
|
||||
port_clkena2 : STRING;
|
||||
port_clkena3 : STRING;
|
||||
port_clkena4 : STRING;
|
||||
port_clkena5 : STRING;
|
||||
port_extclk0 : STRING;
|
||||
port_extclk1 : STRING;
|
||||
port_extclk2 : STRING;
|
||||
port_extclk3 : STRING;
|
||||
width_clock : NATURAL
|
||||
);
|
||||
PORT (
|
||||
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
|
||||
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
BEGIN
|
||||
sub_wire8_bv(0 DOWNTO 0) <= "0";
|
||||
sub_wire8 <= To_stdlogicvector(sub_wire8_bv);
|
||||
sub_wire5 <= sub_wire0(4);
|
||||
sub_wire4 <= sub_wire0(3);
|
||||
sub_wire3 <= sub_wire0(2);
|
||||
sub_wire2 <= sub_wire0(1);
|
||||
sub_wire1 <= sub_wire0(0);
|
||||
c0 <= sub_wire1;
|
||||
c1 <= sub_wire2;
|
||||
c2 <= sub_wire3;
|
||||
c3 <= sub_wire4;
|
||||
c4 <= sub_wire5;
|
||||
sub_wire6 <= inclk0;
|
||||
sub_wire7 <= sub_wire8(0 DOWNTO 0) & sub_wire6;
|
||||
|
||||
altpll_component : altpll
|
||||
GENERIC MAP (
|
||||
bandwidth_type => "AUTO",
|
||||
clk0_divide_by => 11,
|
||||
clk0_duty_cycle => 50,
|
||||
clk0_multiply_by => 16,
|
||||
clk0_phase_shift => "0",
|
||||
clk1_divide_by => 11,
|
||||
clk1_duty_cycle => 50,
|
||||
clk1_multiply_by => 50,
|
||||
clk1_phase_shift => "0",
|
||||
clk2_divide_by => 11,
|
||||
clk2_duty_cycle => 50,
|
||||
clk2_multiply_by => 40,
|
||||
clk2_phase_shift => "0",
|
||||
clk3_divide_by => 33,
|
||||
clk3_duty_cycle => 50,
|
||||
clk3_multiply_by => 109,
|
||||
clk3_phase_shift => "0",
|
||||
clk4_divide_by => 39,
|
||||
clk4_duty_cycle => 50,
|
||||
clk4_multiply_by => 109,
|
||||
clk4_phase_shift => "0",
|
||||
compensate_clock => "CLK0",
|
||||
inclk0_input_frequency => 30303,
|
||||
intended_device_family => "Cyclone III",
|
||||
lpm_type => "altpll",
|
||||
operation_mode => "NORMAL",
|
||||
pll_type => "AUTO",
|
||||
port_activeclock => "PORT_UNUSED",
|
||||
port_areset => "PORT_UNUSED",
|
||||
port_clkbad0 => "PORT_UNUSED",
|
||||
port_clkbad1 => "PORT_UNUSED",
|
||||
port_clkloss => "PORT_UNUSED",
|
||||
port_clkswitch => "PORT_UNUSED",
|
||||
port_configupdate => "PORT_UNUSED",
|
||||
port_fbin => "PORT_UNUSED",
|
||||
port_inclk0 => "PORT_USED",
|
||||
port_inclk1 => "PORT_UNUSED",
|
||||
port_locked => "PORT_UNUSED",
|
||||
port_pfdena => "PORT_UNUSED",
|
||||
port_phasecounterselect => "PORT_UNUSED",
|
||||
port_phasedone => "PORT_UNUSED",
|
||||
port_phasestep => "PORT_UNUSED",
|
||||
port_phaseupdown => "PORT_UNUSED",
|
||||
port_pllena => "PORT_UNUSED",
|
||||
port_scanaclr => "PORT_UNUSED",
|
||||
port_scanclk => "PORT_UNUSED",
|
||||
port_scanclkena => "PORT_UNUSED",
|
||||
port_scandata => "PORT_UNUSED",
|
||||
port_scandataout => "PORT_UNUSED",
|
||||
port_scandone => "PORT_UNUSED",
|
||||
port_scanread => "PORT_UNUSED",
|
||||
port_scanwrite => "PORT_UNUSED",
|
||||
port_clk0 => "PORT_USED",
|
||||
port_clk1 => "PORT_USED",
|
||||
port_clk2 => "PORT_USED",
|
||||
port_clk3 => "PORT_USED",
|
||||
port_clk4 => "PORT_USED",
|
||||
port_clk5 => "PORT_UNUSED",
|
||||
port_clkena0 => "PORT_UNUSED",
|
||||
port_clkena1 => "PORT_UNUSED",
|
||||
port_clkena2 => "PORT_UNUSED",
|
||||
port_clkena3 => "PORT_UNUSED",
|
||||
port_clkena4 => "PORT_UNUSED",
|
||||
port_clkena5 => "PORT_UNUSED",
|
||||
port_extclk0 => "PORT_UNUSED",
|
||||
port_extclk1 => "PORT_UNUSED",
|
||||
port_extclk2 => "PORT_UNUSED",
|
||||
port_extclk3 => "PORT_UNUSED",
|
||||
width_clock => 5
|
||||
)
|
||||
PORT MAP (
|
||||
inclk => sub_wire7,
|
||||
clk => sub_wire0
|
||||
);
|
||||
|
||||
|
||||
|
||||
END SYN;
|
||||
|
||||
-- ============================================================
|
||||
-- CNX file retrieval info
|
||||
-- ============================================================
|
||||
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
|
||||
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
|
||||
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
|
||||
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
|
||||
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "75"
|
||||
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "33"
|
||||
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "36"
|
||||
-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "39"
|
||||
-- Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "39"
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.000000"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "150.000000"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "120.000000"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "109.000000"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "92.230766"
|
||||
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||||
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
|
||||
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
|
||||
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
|
||||
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.000"
|
||||
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
|
||||
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
|
||||
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000"
|
||||
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "ps"
|
||||
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
|
||||
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||||
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
|
||||
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
|
||||
-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
|
||||
-- Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0"
|
||||
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "109"
|
||||
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "109"
|
||||
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "109"
|
||||
-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "109"
|
||||
-- Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "109"
|
||||
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.00000000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "150.00000000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "120.00000000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "109.00000000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "92.00000000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "0"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "0.00000000"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "ps"
|
||||
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
|
||||
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll0.mif"
|
||||
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
|
||||
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
|
||||
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
|
||||
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
|
||||
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
|
||||
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
|
||||
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||||
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
|
||||
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
|
||||
-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
|
||||
-- Retrieval info: PRIVATE: STICKY_CLK4 STRING "1"
|
||||
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
||||
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
|
||||
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
|
||||
-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
|
||||
-- Retrieval info: PRIVATE: USE_CLK4 STRING "1"
|
||||
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_CLKENA4 STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
|
||||
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "11"
|
||||
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "16"
|
||||
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
|
||||
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "11"
|
||||
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
||||
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "11"
|
||||
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "40"
|
||||
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
|
||||
-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "33"
|
||||
-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "109"
|
||||
-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
|
||||
-- Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "39"
|
||||
-- Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "109"
|
||||
-- Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0"
|
||||
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303"
|
||||
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
|
||||
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
|
||||
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
|
||||
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
|
||||
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
|
||||
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
|
||||
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||||
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
|
||||
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
|
||||
-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
|
||||
-- Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
|
||||
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
||||
-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
|
||||
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
|
||||
-- Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
|
||||
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.vhd TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.ppf TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.inc TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.cmp TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.bsf TRUE FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0_inst.vhd FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0_waveforms.html TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0_wave*.jpg FALSE
|
||||
-- Retrieval info: LIB_FILE: altera_mf
|
||||
100
FPGA_quartus_GE/altip_orig/altpll1.bsf
Normal file
100
FPGA_quartus_GE/altip_orig/altpll1.bsf
Normal file
@@ -0,0 +1,100 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2010 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 0 0 328 216)
|
||||
(text "altpll1" (rect 144 1 191 20)(font "Arial" (font_size 10)))
|
||||
(text "inst" (rect 8 197 31 212)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 72)
|
||||
(input)
|
||||
(text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8)))
|
||||
(text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 72)(pt 48 72)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 328 72)
|
||||
(output)
|
||||
(text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8)))
|
||||
(text "c0" (rect 311 56 325 72)(font "Arial" (font_size 8)))
|
||||
(line (pt 328 72)(pt 272 72)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 328 96)
|
||||
(output)
|
||||
(text "c1" (rect 0 0 16 16)(font "Arial" (font_size 8)))
|
||||
(text "c1" (rect 311 80 325 96)(font "Arial" (font_size 8)))
|
||||
(line (pt 328 96)(pt 272 96)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 328 120)
|
||||
(output)
|
||||
(text "c2" (rect 0 0 16 16)(font "Arial" (font_size 8)))
|
||||
(text "c2" (rect 311 104 325 120)(font "Arial" (font_size 8)))
|
||||
(line (pt 328 120)(pt 272 120)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 328 144)
|
||||
(output)
|
||||
(text "locked" (rect 0 0 44 16)(font "Arial" (font_size 8)))
|
||||
(text "locked" (rect 287 128 325 144)(font "Arial" (font_size 8)))
|
||||
(line (pt 328 144)(pt 272 144)(line_width 1))
|
||||
)
|
||||
(drawing
|
||||
(text "Cyclone III" (rect 253 198 301 212)(font "Arial" ))
|
||||
(text "inclk0 frequency: 33.000 MHz" (rect 58 67 201 81)(font "Arial" ))
|
||||
(text "Operation Mode: Src Sync Comp" (rect 58 84 215 98)(font "Arial" ))
|
||||
(text "Clk " (rect 59 111 76 125)(font "Arial" ))
|
||||
(text "Ratio" (rect 90 111 114 125)(font "Arial" ))
|
||||
(text "Ph (dg)" (rect 128 111 163 125)(font "Arial" ))
|
||||
(text "DC (%)" (rect 173 111 208 125)(font "Arial" ))
|
||||
(text "c0" (rect 63 129 75 143)(font "Arial" ))
|
||||
(text "1/66" (rect 92 129 113 143)(font "Arial" ))
|
||||
(text "0.00" (rect 136 129 157 143)(font "Arial" ))
|
||||
(text "50.00" (rect 178 129 205 143)(font "Arial" ))
|
||||
(text "c1" (rect 63 147 75 161)(font "Arial" ))
|
||||
(text "67/900" (rect 85 147 118 161)(font "Arial" ))
|
||||
(text "0.00" (rect 136 147 157 161)(font "Arial" ))
|
||||
(text "50.00" (rect 178 147 205 161)(font "Arial" ))
|
||||
(text "c2" (rect 63 165 75 179)(font "Arial" ))
|
||||
(text "67/90" (rect 89 165 116 179)(font "Arial" ))
|
||||
(text "0.00" (rect 136 165 157 179)(font "Arial" ))
|
||||
(text "50.00" (rect 178 165 205 179)(font "Arial" ))
|
||||
(line (pt 0 0)(pt 329 0)(line_width 1))
|
||||
(line (pt 329 0)(pt 329 217)(line_width 1))
|
||||
(line (pt 0 217)(pt 329 217)(line_width 1))
|
||||
(line (pt 0 0)(pt 0 217)(line_width 1))
|
||||
(line (pt 56 108)(pt 215 108)(line_width 1))
|
||||
(line (pt 56 125)(pt 215 125)(line_width 1))
|
||||
(line (pt 56 143)(pt 215 143)(line_width 1))
|
||||
(line (pt 56 161)(pt 215 161)(line_width 1))
|
||||
(line (pt 56 179)(pt 215 179)(line_width 1))
|
||||
(line (pt 56 108)(pt 56 179)(line_width 1))
|
||||
(line (pt 82 108)(pt 82 179)(line_width 3))
|
||||
(line (pt 125 108)(pt 125 179)(line_width 3))
|
||||
(line (pt 170 108)(pt 170 179)(line_width 3))
|
||||
(line (pt 214 108)(pt 214 179)(line_width 1))
|
||||
(line (pt 48 56)(pt 272 56)(line_width 1))
|
||||
(line (pt 272 56)(pt 272 200)(line_width 1))
|
||||
(line (pt 48 200)(pt 272 200)(line_width 1))
|
||||
(line (pt 48 56)(pt 48 200)(line_width 1))
|
||||
)
|
||||
)
|
||||
26
FPGA_quartus_GE/altip_orig/altpll1.inc
Normal file
26
FPGA_quartus_GE/altip_orig/altpll1.inc
Normal file
@@ -0,0 +1,26 @@
|
||||
--Copyright (C) 1991-2010 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
FUNCTION altpll1
|
||||
(
|
||||
inclk0
|
||||
)
|
||||
|
||||
RETURNS (
|
||||
c0,
|
||||
c1,
|
||||
c2,
|
||||
locked
|
||||
);
|
||||
12
FPGA_quartus_GE/altip_orig/altpll1.ppf
Normal file
12
FPGA_quartus_GE/altip_orig/altpll1.ppf
Normal file
@@ -0,0 +1,12 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<!DOCTYPE pinplan>
|
||||
<pinplan intended_family="Cyclone III" variation_name="altpll1" megafunction_name="ALTPLL" specifies="all_ports">
|
||||
<global>
|
||||
<pin name="inclk0" direction="input" scope="external" source="clock" />
|
||||
<pin name="c0" direction="output" scope="external" source="clock" />
|
||||
<pin name="c1" direction="output" scope="external" source="clock" />
|
||||
<pin name="c2" direction="output" scope="external" source="clock" />
|
||||
<pin name="locked" direction="output" scope="external" />
|
||||
|
||||
</global>
|
||||
</pinplan>
|
||||
7
FPGA_quartus_GE/altip_orig/altpll1.qip
Normal file
7
FPGA_quartus_GE/altip_orig/altpll1.qip
Normal file
@@ -0,0 +1,7 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
|
||||
set_global_assignment -name IP_TOOL_VERSION "9.1"
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll1.vhd"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.bsf"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.inc"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.cmp"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.ppf"]
|
||||
423
FPGA_quartus_GE/altip_orig/altpll1.vhd
Normal file
423
FPGA_quartus_GE/altip_orig/altpll1.vhd
Normal file
@@ -0,0 +1,423 @@
|
||||
-- megafunction wizard: %ALTPLL%
|
||||
-- GENERATION: STANDARD
|
||||
-- VERSION: WM1.0
|
||||
-- MODULE: altpll
|
||||
|
||||
-- ============================================================
|
||||
-- File Name: altpll1.vhd
|
||||
-- Megafunction Name(s):
|
||||
-- altpll
|
||||
--
|
||||
-- Simulation Library Files(s):
|
||||
-- altera_mf
|
||||
-- ============================================================
|
||||
-- ************************************************************
|
||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
--
|
||||
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
|
||||
-- ************************************************************
|
||||
|
||||
|
||||
--Copyright (C) 1991-2010 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
|
||||
LIBRARY altera_mf;
|
||||
USE altera_mf.all;
|
||||
|
||||
ENTITY altpll1 IS
|
||||
PORT
|
||||
(
|
||||
inclk0 : IN STD_LOGIC := '0';
|
||||
c0 : OUT STD_LOGIC ;
|
||||
c1 : OUT STD_LOGIC ;
|
||||
c2 : OUT STD_LOGIC ;
|
||||
locked : OUT STD_LOGIC
|
||||
);
|
||||
END altpll1;
|
||||
|
||||
|
||||
ARCHITECTURE SYN OF altpll1 IS
|
||||
|
||||
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
|
||||
SIGNAL sub_wire1 : STD_LOGIC ;
|
||||
SIGNAL sub_wire2 : STD_LOGIC ;
|
||||
SIGNAL sub_wire3 : STD_LOGIC ;
|
||||
SIGNAL sub_wire4 : STD_LOGIC ;
|
||||
SIGNAL sub_wire5 : STD_LOGIC ;
|
||||
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0);
|
||||
SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0);
|
||||
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0);
|
||||
|
||||
|
||||
|
||||
COMPONENT altpll
|
||||
GENERIC (
|
||||
bandwidth_type : STRING;
|
||||
clk0_divide_by : NATURAL;
|
||||
clk0_duty_cycle : NATURAL;
|
||||
clk0_multiply_by : NATURAL;
|
||||
clk0_phase_shift : STRING;
|
||||
clk1_divide_by : NATURAL;
|
||||
clk1_duty_cycle : NATURAL;
|
||||
clk1_multiply_by : NATURAL;
|
||||
clk1_phase_shift : STRING;
|
||||
clk2_divide_by : NATURAL;
|
||||
clk2_duty_cycle : NATURAL;
|
||||
clk2_multiply_by : NATURAL;
|
||||
clk2_phase_shift : STRING;
|
||||
compensate_clock : STRING;
|
||||
inclk0_input_frequency : NATURAL;
|
||||
intended_device_family : STRING;
|
||||
lpm_type : STRING;
|
||||
operation_mode : STRING;
|
||||
pll_type : STRING;
|
||||
port_activeclock : STRING;
|
||||
port_areset : STRING;
|
||||
port_clkbad0 : STRING;
|
||||
port_clkbad1 : STRING;
|
||||
port_clkloss : STRING;
|
||||
port_clkswitch : STRING;
|
||||
port_configupdate : STRING;
|
||||
port_fbin : STRING;
|
||||
port_inclk0 : STRING;
|
||||
port_inclk1 : STRING;
|
||||
port_locked : STRING;
|
||||
port_pfdena : STRING;
|
||||
port_phasecounterselect : STRING;
|
||||
port_phasedone : STRING;
|
||||
port_phasestep : STRING;
|
||||
port_phaseupdown : STRING;
|
||||
port_pllena : STRING;
|
||||
port_scanaclr : STRING;
|
||||
port_scanclk : STRING;
|
||||
port_scanclkena : STRING;
|
||||
port_scandata : STRING;
|
||||
port_scandataout : STRING;
|
||||
port_scandone : STRING;
|
||||
port_scanread : STRING;
|
||||
port_scanwrite : STRING;
|
||||
port_clk0 : STRING;
|
||||
port_clk1 : STRING;
|
||||
port_clk2 : STRING;
|
||||
port_clk3 : STRING;
|
||||
port_clk4 : STRING;
|
||||
port_clk5 : STRING;
|
||||
port_clkena0 : STRING;
|
||||
port_clkena1 : STRING;
|
||||
port_clkena2 : STRING;
|
||||
port_clkena3 : STRING;
|
||||
port_clkena4 : STRING;
|
||||
port_clkena5 : STRING;
|
||||
port_extclk0 : STRING;
|
||||
port_extclk1 : STRING;
|
||||
port_extclk2 : STRING;
|
||||
port_extclk3 : STRING;
|
||||
self_reset_on_loss_lock : STRING;
|
||||
width_clock : NATURAL
|
||||
);
|
||||
PORT (
|
||||
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
|
||||
locked : OUT STD_LOGIC ;
|
||||
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
BEGIN
|
||||
sub_wire7_bv(0 DOWNTO 0) <= "0";
|
||||
sub_wire7 <= To_stdlogicvector(sub_wire7_bv);
|
||||
sub_wire3 <= sub_wire0(2);
|
||||
sub_wire2 <= sub_wire0(1);
|
||||
sub_wire1 <= sub_wire0(0);
|
||||
c0 <= sub_wire1;
|
||||
c1 <= sub_wire2;
|
||||
c2 <= sub_wire3;
|
||||
locked <= sub_wire4;
|
||||
sub_wire5 <= inclk0;
|
||||
sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5;
|
||||
|
||||
altpll_component : altpll
|
||||
GENERIC MAP (
|
||||
bandwidth_type => "AUTO",
|
||||
clk0_divide_by => 66,
|
||||
clk0_duty_cycle => 50,
|
||||
clk0_multiply_by => 1,
|
||||
clk0_phase_shift => "0",
|
||||
clk1_divide_by => 900,
|
||||
clk1_duty_cycle => 50,
|
||||
clk1_multiply_by => 67,
|
||||
clk1_phase_shift => "0",
|
||||
clk2_divide_by => 90,
|
||||
clk2_duty_cycle => 50,
|
||||
clk2_multiply_by => 67,
|
||||
clk2_phase_shift => "0",
|
||||
compensate_clock => "CLK0",
|
||||
inclk0_input_frequency => 30303,
|
||||
intended_device_family => "Cyclone III",
|
||||
lpm_type => "altpll",
|
||||
operation_mode => "SOURCE_SYNCHRONOUS",
|
||||
pll_type => "AUTO",
|
||||
port_activeclock => "PORT_UNUSED",
|
||||
port_areset => "PORT_UNUSED",
|
||||
port_clkbad0 => "PORT_UNUSED",
|
||||
port_clkbad1 => "PORT_UNUSED",
|
||||
port_clkloss => "PORT_UNUSED",
|
||||
port_clkswitch => "PORT_UNUSED",
|
||||
port_configupdate => "PORT_UNUSED",
|
||||
port_fbin => "PORT_UNUSED",
|
||||
port_inclk0 => "PORT_USED",
|
||||
port_inclk1 => "PORT_UNUSED",
|
||||
port_locked => "PORT_USED",
|
||||
port_pfdena => "PORT_UNUSED",
|
||||
port_phasecounterselect => "PORT_UNUSED",
|
||||
port_phasedone => "PORT_UNUSED",
|
||||
port_phasestep => "PORT_UNUSED",
|
||||
port_phaseupdown => "PORT_UNUSED",
|
||||
port_pllena => "PORT_UNUSED",
|
||||
port_scanaclr => "PORT_UNUSED",
|
||||
port_scanclk => "PORT_UNUSED",
|
||||
port_scanclkena => "PORT_UNUSED",
|
||||
port_scandata => "PORT_UNUSED",
|
||||
port_scandataout => "PORT_UNUSED",
|
||||
port_scandone => "PORT_UNUSED",
|
||||
port_scanread => "PORT_UNUSED",
|
||||
port_scanwrite => "PORT_UNUSED",
|
||||
port_clk0 => "PORT_USED",
|
||||
port_clk1 => "PORT_USED",
|
||||
port_clk2 => "PORT_USED",
|
||||
port_clk3 => "PORT_UNUSED",
|
||||
port_clk4 => "PORT_UNUSED",
|
||||
port_clk5 => "PORT_UNUSED",
|
||||
port_clkena0 => "PORT_UNUSED",
|
||||
port_clkena1 => "PORT_UNUSED",
|
||||
port_clkena2 => "PORT_UNUSED",
|
||||
port_clkena3 => "PORT_UNUSED",
|
||||
port_clkena4 => "PORT_UNUSED",
|
||||
port_clkena5 => "PORT_UNUSED",
|
||||
port_extclk0 => "PORT_UNUSED",
|
||||
port_extclk1 => "PORT_UNUSED",
|
||||
port_extclk2 => "PORT_UNUSED",
|
||||
port_extclk3 => "PORT_UNUSED",
|
||||
self_reset_on_loss_lock => "OFF",
|
||||
width_clock => 5
|
||||
)
|
||||
PORT MAP (
|
||||
inclk => sub_wire6,
|
||||
clk => sub_wire0,
|
||||
locked => sub_wire4
|
||||
);
|
||||
|
||||
|
||||
|
||||
END SYN;
|
||||
|
||||
-- ============================================================
|
||||
-- CNX file retrieval info
|
||||
-- ============================================================
|
||||
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
|
||||
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
|
||||
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
|
||||
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
|
||||
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "90"
|
||||
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "900"
|
||||
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "90"
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "0.500000"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "2.456667"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "24.566668"
|
||||
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||||
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
|
||||
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
|
||||
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
|
||||
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.000"
|
||||
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
|
||||
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
|
||||
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
|
||||
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000"
|
||||
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
|
||||
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||||
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
|
||||
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
|
||||
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "67"
|
||||
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "67"
|
||||
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "67"
|
||||
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "0.50000000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "2.45760000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "24.57600000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
|
||||
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll1.mif"
|
||||
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
|
||||
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
|
||||
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
|
||||
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
|
||||
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
|
||||
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
|
||||
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1"
|
||||
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||||
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
|
||||
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
|
||||
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
||||
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
|
||||
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
|
||||
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
|
||||
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "66"
|
||||
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
|
||||
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
|
||||
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "900"
|
||||
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "67"
|
||||
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
||||
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "90"
|
||||
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "67"
|
||||
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
|
||||
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303"
|
||||
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
|
||||
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS"
|
||||
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
|
||||
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
|
||||
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
|
||||
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
|
||||
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
|
||||
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||||
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
|
||||
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
|
||||
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
|
||||
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
||||
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
|
||||
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.vhd TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.ppf TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.inc TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.cmp TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.bsf TRUE FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_inst.vhd FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_waveforms.html TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_wave*.jpg FALSE
|
||||
-- Retrieval info: LIB_FILE: altera_mf
|
||||
117
FPGA_quartus_GE/altip_orig/altpll2.bsf
Normal file
117
FPGA_quartus_GE/altip_orig/altpll2.bsf
Normal file
@@ -0,0 +1,117 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2010 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 0 0 304 248)
|
||||
(text "altpll2" (rect 132 1 179 20)(font "Arial" (font_size 10)))
|
||||
(text "inst" (rect 8 229 31 244)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 72)
|
||||
(input)
|
||||
(text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8)))
|
||||
(text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 72)(pt 48 72)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 304 72)
|
||||
(output)
|
||||
(text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8)))
|
||||
(text "c0" (rect 287 56 301 72)(font "Arial" (font_size 8)))
|
||||
(line (pt 304 72)(pt 272 72)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 304 96)
|
||||
(output)
|
||||
(text "c1" (rect 0 0 16 16)(font "Arial" (font_size 8)))
|
||||
(text "c1" (rect 287 80 301 96)(font "Arial" (font_size 8)))
|
||||
(line (pt 304 96)(pt 272 96)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 304 120)
|
||||
(output)
|
||||
(text "c2" (rect 0 0 16 16)(font "Arial" (font_size 8)))
|
||||
(text "c2" (rect 287 104 301 120)(font "Arial" (font_size 8)))
|
||||
(line (pt 304 120)(pt 272 120)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 304 144)
|
||||
(output)
|
||||
(text "c3" (rect 0 0 16 16)(font "Arial" (font_size 8)))
|
||||
(text "c3" (rect 287 128 301 144)(font "Arial" (font_size 8)))
|
||||
(line (pt 304 144)(pt 272 144)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 304 168)
|
||||
(output)
|
||||
(text "c4" (rect 0 0 16 16)(font "Arial" (font_size 8)))
|
||||
(text "c4" (rect 287 152 301 168)(font "Arial" (font_size 8)))
|
||||
(line (pt 304 168)(pt 272 168)(line_width 1))
|
||||
)
|
||||
(drawing
|
||||
(text "Cyclone III" (rect 229 230 277 244)(font "Arial" ))
|
||||
(text "inclk0 frequency: 33.000 MHz" (rect 58 67 201 81)(font "Arial" ))
|
||||
(text "Operation Mode: Src Sync Comp" (rect 58 84 215 98)(font "Arial" ))
|
||||
(text "Clk " (rect 59 111 76 125)(font "Arial" ))
|
||||
(text "Ratio" (rect 85 111 109 125)(font "Arial" ))
|
||||
(text "Ph (dg)" (rect 119 111 154 125)(font "Arial" ))
|
||||
(text "DC (%)" (rect 164 111 199 125)(font "Arial" ))
|
||||
(text "c0" (rect 63 129 75 143)(font "Arial" ))
|
||||
(text "4/1" (rect 91 129 106 143)(font "Arial" ))
|
||||
(text "240.00" (rect 120 129 153 143)(font "Arial" ))
|
||||
(text "50.00" (rect 169 129 196 143)(font "Arial" ))
|
||||
(text "c1" (rect 63 147 75 161)(font "Arial" ))
|
||||
(text "4/1" (rect 91 147 106 161)(font "Arial" ))
|
||||
(text "0.00" (rect 127 147 148 161)(font "Arial" ))
|
||||
(text "50.00" (rect 169 147 196 161)(font "Arial" ))
|
||||
(text "c2" (rect 63 165 75 179)(font "Arial" ))
|
||||
(text "4/1" (rect 91 165 106 179)(font "Arial" ))
|
||||
(text "180.00" (rect 120 165 153 179)(font "Arial" ))
|
||||
(text "50.00" (rect 169 165 196 179)(font "Arial" ))
|
||||
(text "c3" (rect 63 183 75 197)(font "Arial" ))
|
||||
(text "4/1" (rect 91 183 106 197)(font "Arial" ))
|
||||
(text "105.00" (rect 120 183 153 197)(font "Arial" ))
|
||||
(text "50.00" (rect 169 183 196 197)(font "Arial" ))
|
||||
(text "c4" (rect 63 201 75 215)(font "Arial" ))
|
||||
(text "2/1" (rect 91 201 106 215)(font "Arial" ))
|
||||
(text "270.00" (rect 120 201 153 215)(font "Arial" ))
|
||||
(text "50.00" (rect 169 201 196 215)(font "Arial" ))
|
||||
(line (pt 0 0)(pt 305 0)(line_width 1))
|
||||
(line (pt 305 0)(pt 305 249)(line_width 1))
|
||||
(line (pt 0 249)(pt 305 249)(line_width 1))
|
||||
(line (pt 0 0)(pt 0 249)(line_width 1))
|
||||
(line (pt 56 108)(pt 206 108)(line_width 1))
|
||||
(line (pt 56 125)(pt 206 125)(line_width 1))
|
||||
(line (pt 56 143)(pt 206 143)(line_width 1))
|
||||
(line (pt 56 161)(pt 206 161)(line_width 1))
|
||||
(line (pt 56 179)(pt 206 179)(line_width 1))
|
||||
(line (pt 56 197)(pt 206 197)(line_width 1))
|
||||
(line (pt 56 215)(pt 206 215)(line_width 1))
|
||||
(line (pt 56 108)(pt 56 215)(line_width 1))
|
||||
(line (pt 82 108)(pt 82 215)(line_width 3))
|
||||
(line (pt 116 108)(pt 116 215)(line_width 3))
|
||||
(line (pt 161 108)(pt 161 215)(line_width 3))
|
||||
(line (pt 205 108)(pt 205 215)(line_width 1))
|
||||
(line (pt 48 56)(pt 272 56)(line_width 1))
|
||||
(line (pt 272 56)(pt 272 232)(line_width 1))
|
||||
(line (pt 48 232)(pt 272 232)(line_width 1))
|
||||
(line (pt 48 56)(pt 48 232)(line_width 1))
|
||||
)
|
||||
)
|
||||
27
FPGA_quartus_GE/altip_orig/altpll2.inc
Normal file
27
FPGA_quartus_GE/altip_orig/altpll2.inc
Normal file
@@ -0,0 +1,27 @@
|
||||
--Copyright (C) 1991-2010 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
FUNCTION altpll2
|
||||
(
|
||||
inclk0
|
||||
)
|
||||
|
||||
RETURNS (
|
||||
c0,
|
||||
c1,
|
||||
c2,
|
||||
c3,
|
||||
c4
|
||||
);
|
||||
13
FPGA_quartus_GE/altip_orig/altpll2.ppf
Normal file
13
FPGA_quartus_GE/altip_orig/altpll2.ppf
Normal file
@@ -0,0 +1,13 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<!DOCTYPE pinplan>
|
||||
<pinplan intended_family="Cyclone III" variation_name="altpll2" megafunction_name="ALTPLL" specifies="all_ports">
|
||||
<global>
|
||||
<pin name="inclk0" direction="input" scope="external" source="clock" />
|
||||
<pin name="c0" direction="output" scope="external" source="clock" />
|
||||
<pin name="c1" direction="output" scope="external" source="clock" />
|
||||
<pin name="c2" direction="output" scope="external" source="clock" />
|
||||
<pin name="c3" direction="output" scope="external" source="clock" />
|
||||
<pin name="c4" direction="output" scope="external" source="clock" />
|
||||
|
||||
</global>
|
||||
</pinplan>
|
||||
7
FPGA_quartus_GE/altip_orig/altpll2.qip
Normal file
7
FPGA_quartus_GE/altip_orig/altpll2.qip
Normal file
@@ -0,0 +1,7 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
|
||||
set_global_assignment -name IP_TOOL_VERSION "9.1"
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll2.vhd"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.bsf"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.inc"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.cmp"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.ppf"]
|
||||
477
FPGA_quartus_GE/altip_orig/altpll2.vhd
Normal file
477
FPGA_quartus_GE/altip_orig/altpll2.vhd
Normal file
@@ -0,0 +1,477 @@
|
||||
-- megafunction wizard: %ALTPLL%
|
||||
-- GENERATION: STANDARD
|
||||
-- VERSION: WM1.0
|
||||
-- MODULE: altpll
|
||||
|
||||
-- ============================================================
|
||||
-- File Name: altpll2.vhd
|
||||
-- Megafunction Name(s):
|
||||
-- altpll
|
||||
--
|
||||
-- Simulation Library Files(s):
|
||||
-- altera_mf
|
||||
-- ============================================================
|
||||
-- ************************************************************
|
||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
--
|
||||
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
|
||||
-- ************************************************************
|
||||
|
||||
|
||||
--Copyright (C) 1991-2010 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
|
||||
LIBRARY altera_mf;
|
||||
USE altera_mf.all;
|
||||
|
||||
ENTITY altpll2 IS
|
||||
PORT
|
||||
(
|
||||
inclk0 : IN STD_LOGIC := '0';
|
||||
c0 : OUT STD_LOGIC ;
|
||||
c1 : OUT STD_LOGIC ;
|
||||
c2 : OUT STD_LOGIC ;
|
||||
c3 : OUT STD_LOGIC ;
|
||||
c4 : OUT STD_LOGIC
|
||||
);
|
||||
END altpll2;
|
||||
|
||||
|
||||
ARCHITECTURE SYN OF altpll2 IS
|
||||
|
||||
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
|
||||
SIGNAL sub_wire1 : STD_LOGIC ;
|
||||
SIGNAL sub_wire2 : STD_LOGIC ;
|
||||
SIGNAL sub_wire3 : STD_LOGIC ;
|
||||
SIGNAL sub_wire4 : STD_LOGIC ;
|
||||
SIGNAL sub_wire5 : STD_LOGIC ;
|
||||
SIGNAL sub_wire6 : STD_LOGIC ;
|
||||
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (1 DOWNTO 0);
|
||||
SIGNAL sub_wire8_bv : BIT_VECTOR (0 DOWNTO 0);
|
||||
SIGNAL sub_wire8 : STD_LOGIC_VECTOR (0 DOWNTO 0);
|
||||
|
||||
|
||||
|
||||
COMPONENT altpll
|
||||
GENERIC (
|
||||
bandwidth_type : STRING;
|
||||
clk0_divide_by : NATURAL;
|
||||
clk0_duty_cycle : NATURAL;
|
||||
clk0_multiply_by : NATURAL;
|
||||
clk0_phase_shift : STRING;
|
||||
clk1_divide_by : NATURAL;
|
||||
clk1_duty_cycle : NATURAL;
|
||||
clk1_multiply_by : NATURAL;
|
||||
clk1_phase_shift : STRING;
|
||||
clk2_divide_by : NATURAL;
|
||||
clk2_duty_cycle : NATURAL;
|
||||
clk2_multiply_by : NATURAL;
|
||||
clk2_phase_shift : STRING;
|
||||
clk3_divide_by : NATURAL;
|
||||
clk3_duty_cycle : NATURAL;
|
||||
clk3_multiply_by : NATURAL;
|
||||
clk3_phase_shift : STRING;
|
||||
clk4_divide_by : NATURAL;
|
||||
clk4_duty_cycle : NATURAL;
|
||||
clk4_multiply_by : NATURAL;
|
||||
clk4_phase_shift : STRING;
|
||||
compensate_clock : STRING;
|
||||
inclk0_input_frequency : NATURAL;
|
||||
intended_device_family : STRING;
|
||||
lpm_type : STRING;
|
||||
operation_mode : STRING;
|
||||
pll_type : STRING;
|
||||
port_activeclock : STRING;
|
||||
port_areset : STRING;
|
||||
port_clkbad0 : STRING;
|
||||
port_clkbad1 : STRING;
|
||||
port_clkloss : STRING;
|
||||
port_clkswitch : STRING;
|
||||
port_configupdate : STRING;
|
||||
port_fbin : STRING;
|
||||
port_inclk0 : STRING;
|
||||
port_inclk1 : STRING;
|
||||
port_locked : STRING;
|
||||
port_pfdena : STRING;
|
||||
port_phasecounterselect : STRING;
|
||||
port_phasedone : STRING;
|
||||
port_phasestep : STRING;
|
||||
port_phaseupdown : STRING;
|
||||
port_pllena : STRING;
|
||||
port_scanaclr : STRING;
|
||||
port_scanclk : STRING;
|
||||
port_scanclkena : STRING;
|
||||
port_scandata : STRING;
|
||||
port_scandataout : STRING;
|
||||
port_scandone : STRING;
|
||||
port_scanread : STRING;
|
||||
port_scanwrite : STRING;
|
||||
port_clk0 : STRING;
|
||||
port_clk1 : STRING;
|
||||
port_clk2 : STRING;
|
||||
port_clk3 : STRING;
|
||||
port_clk4 : STRING;
|
||||
port_clk5 : STRING;
|
||||
port_clkena0 : STRING;
|
||||
port_clkena1 : STRING;
|
||||
port_clkena2 : STRING;
|
||||
port_clkena3 : STRING;
|
||||
port_clkena4 : STRING;
|
||||
port_clkena5 : STRING;
|
||||
port_extclk0 : STRING;
|
||||
port_extclk1 : STRING;
|
||||
port_extclk2 : STRING;
|
||||
port_extclk3 : STRING;
|
||||
width_clock : NATURAL
|
||||
);
|
||||
PORT (
|
||||
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
|
||||
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
BEGIN
|
||||
sub_wire8_bv(0 DOWNTO 0) <= "0";
|
||||
sub_wire8 <= To_stdlogicvector(sub_wire8_bv);
|
||||
sub_wire5 <= sub_wire0(4);
|
||||
sub_wire4 <= sub_wire0(3);
|
||||
sub_wire3 <= sub_wire0(2);
|
||||
sub_wire2 <= sub_wire0(1);
|
||||
sub_wire1 <= sub_wire0(0);
|
||||
c0 <= sub_wire1;
|
||||
c1 <= sub_wire2;
|
||||
c2 <= sub_wire3;
|
||||
c3 <= sub_wire4;
|
||||
c4 <= sub_wire5;
|
||||
sub_wire6 <= inclk0;
|
||||
sub_wire7 <= sub_wire8(0 DOWNTO 0) & sub_wire6;
|
||||
|
||||
altpll_component : altpll
|
||||
GENERIC MAP (
|
||||
bandwidth_type => "AUTO",
|
||||
clk0_divide_by => 1,
|
||||
clk0_duty_cycle => 50,
|
||||
clk0_multiply_by => 4,
|
||||
clk0_phase_shift => "5051",
|
||||
clk1_divide_by => 1,
|
||||
clk1_duty_cycle => 50,
|
||||
clk1_multiply_by => 4,
|
||||
clk1_phase_shift => "0",
|
||||
clk2_divide_by => 1,
|
||||
clk2_duty_cycle => 50,
|
||||
clk2_multiply_by => 4,
|
||||
clk2_phase_shift => "3788",
|
||||
clk3_divide_by => 1,
|
||||
clk3_duty_cycle => 50,
|
||||
clk3_multiply_by => 4,
|
||||
clk3_phase_shift => "2210",
|
||||
clk4_divide_by => 1,
|
||||
clk4_duty_cycle => 50,
|
||||
clk4_multiply_by => 2,
|
||||
clk4_phase_shift => "11364",
|
||||
compensate_clock => "CLK0",
|
||||
inclk0_input_frequency => 30303,
|
||||
intended_device_family => "Cyclone III",
|
||||
lpm_type => "altpll",
|
||||
operation_mode => "SOURCE_SYNCHRONOUS",
|
||||
pll_type => "AUTO",
|
||||
port_activeclock => "PORT_UNUSED",
|
||||
port_areset => "PORT_UNUSED",
|
||||
port_clkbad0 => "PORT_UNUSED",
|
||||
port_clkbad1 => "PORT_UNUSED",
|
||||
port_clkloss => "PORT_UNUSED",
|
||||
port_clkswitch => "PORT_UNUSED",
|
||||
port_configupdate => "PORT_UNUSED",
|
||||
port_fbin => "PORT_UNUSED",
|
||||
port_inclk0 => "PORT_USED",
|
||||
port_inclk1 => "PORT_UNUSED",
|
||||
port_locked => "PORT_UNUSED",
|
||||
port_pfdena => "PORT_UNUSED",
|
||||
port_phasecounterselect => "PORT_UNUSED",
|
||||
port_phasedone => "PORT_UNUSED",
|
||||
port_phasestep => "PORT_UNUSED",
|
||||
port_phaseupdown => "PORT_UNUSED",
|
||||
port_pllena => "PORT_UNUSED",
|
||||
port_scanaclr => "PORT_UNUSED",
|
||||
port_scanclk => "PORT_UNUSED",
|
||||
port_scanclkena => "PORT_UNUSED",
|
||||
port_scandata => "PORT_UNUSED",
|
||||
port_scandataout => "PORT_UNUSED",
|
||||
port_scandone => "PORT_UNUSED",
|
||||
port_scanread => "PORT_UNUSED",
|
||||
port_scanwrite => "PORT_UNUSED",
|
||||
port_clk0 => "PORT_USED",
|
||||
port_clk1 => "PORT_USED",
|
||||
port_clk2 => "PORT_USED",
|
||||
port_clk3 => "PORT_USED",
|
||||
port_clk4 => "PORT_USED",
|
||||
port_clk5 => "PORT_UNUSED",
|
||||
port_clkena0 => "PORT_UNUSED",
|
||||
port_clkena1 => "PORT_UNUSED",
|
||||
port_clkena2 => "PORT_UNUSED",
|
||||
port_clkena3 => "PORT_UNUSED",
|
||||
port_clkena4 => "PORT_UNUSED",
|
||||
port_clkena5 => "PORT_UNUSED",
|
||||
port_extclk0 => "PORT_UNUSED",
|
||||
port_extclk1 => "PORT_UNUSED",
|
||||
port_extclk2 => "PORT_UNUSED",
|
||||
port_extclk3 => "PORT_UNUSED",
|
||||
width_clock => 5
|
||||
)
|
||||
PORT MAP (
|
||||
inclk => sub_wire7,
|
||||
clk => sub_wire0
|
||||
);
|
||||
|
||||
|
||||
|
||||
END SYN;
|
||||
|
||||
-- ============================================================
|
||||
-- CNX file retrieval info
|
||||
-- ============================================================
|
||||
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
|
||||
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
|
||||
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
|
||||
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
|
||||
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "132.000000"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "132.000000"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "132.000000"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "132.000000"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "66.000000"
|
||||
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||||
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
|
||||
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
|
||||
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
|
||||
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.000"
|
||||
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
|
||||
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
|
||||
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000"
|
||||
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "ps"
|
||||
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
|
||||
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||||
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
|
||||
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
|
||||
-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
|
||||
-- Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0"
|
||||
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "4"
|
||||
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4"
|
||||
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4"
|
||||
-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "4"
|
||||
-- Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "2"
|
||||
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "133.33333000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "133.33330000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "133.33330000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "133.33330000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "100.00000000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "0"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "240.00000000"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "180.00000000"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "105.00000000"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "270.00000000"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
|
||||
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll2.mif"
|
||||
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
|
||||
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
|
||||
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
|
||||
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
|
||||
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
|
||||
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
|
||||
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1"
|
||||
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||||
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
|
||||
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
|
||||
-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
|
||||
-- Retrieval info: PRIVATE: STICKY_CLK4 STRING "1"
|
||||
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
||||
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
|
||||
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
|
||||
-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
|
||||
-- Retrieval info: PRIVATE: USE_CLK4 STRING "1"
|
||||
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_CLKENA4 STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
|
||||
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
|
||||
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4"
|
||||
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "5051"
|
||||
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
|
||||
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4"
|
||||
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
||||
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1"
|
||||
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4"
|
||||
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "3788"
|
||||
-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "1"
|
||||
-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "4"
|
||||
-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "2210"
|
||||
-- Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "1"
|
||||
-- Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "2"
|
||||
-- Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "11364"
|
||||
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303"
|
||||
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
|
||||
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS"
|
||||
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
|
||||
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
|
||||
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
|
||||
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
|
||||
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||||
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
|
||||
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
|
||||
-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
|
||||
-- Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
|
||||
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
||||
-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
|
||||
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
|
||||
-- Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
|
||||
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.vhd TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.ppf TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.inc TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.cmp TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.bsf TRUE FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_inst.vhd FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_waveforms.html TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_wave*.jpg FALSE
|
||||
-- Retrieval info: LIB_FILE: altera_mf
|
||||
105
FPGA_quartus_GE/altip_orig/altpll3.bsf
Normal file
105
FPGA_quartus_GE/altip_orig/altpll3.bsf
Normal file
@@ -0,0 +1,105 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2010 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 0 0 304 232)
|
||||
(text "altpll3" (rect 132 1 179 20)(font "Arial" (font_size 10)))
|
||||
(text "inst" (rect 8 213 31 228)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 72)
|
||||
(input)
|
||||
(text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8)))
|
||||
(text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 72)(pt 48 72)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 304 72)
|
||||
(output)
|
||||
(text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8)))
|
||||
(text "c0" (rect 287 56 301 72)(font "Arial" (font_size 8)))
|
||||
(line (pt 304 72)(pt 272 72)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 304 96)
|
||||
(output)
|
||||
(text "c1" (rect 0 0 16 16)(font "Arial" (font_size 8)))
|
||||
(text "c1" (rect 287 80 301 96)(font "Arial" (font_size 8)))
|
||||
(line (pt 304 96)(pt 272 96)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 304 120)
|
||||
(output)
|
||||
(text "c2" (rect 0 0 16 16)(font "Arial" (font_size 8)))
|
||||
(text "c2" (rect 287 104 301 120)(font "Arial" (font_size 8)))
|
||||
(line (pt 304 120)(pt 272 120)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 304 144)
|
||||
(output)
|
||||
(text "c3" (rect 0 0 16 16)(font "Arial" (font_size 8)))
|
||||
(text "c3" (rect 287 128 301 144)(font "Arial" (font_size 8)))
|
||||
(line (pt 304 144)(pt 272 144)(line_width 1))
|
||||
)
|
||||
(drawing
|
||||
(text "Cyclone III" (rect 229 214 277 228)(font "Arial" ))
|
||||
(text "inclk0 frequency: 33.000 MHz" (rect 58 67 201 81)(font "Arial" ))
|
||||
(text "Operation Mode: Src Sync Comp" (rect 58 84 215 98)(font "Arial" ))
|
||||
(text "Clk " (rect 59 111 76 125)(font "Arial" ))
|
||||
(text "Ratio" (rect 86 111 110 125)(font "Arial" ))
|
||||
(text "Ph (dg)" (rect 121 111 156 125)(font "Arial" ))
|
||||
(text "DC (%)" (rect 166 111 201 125)(font "Arial" ))
|
||||
(text "c0" (rect 63 129 75 143)(font "Arial" ))
|
||||
(text "2/33" (rect 88 129 109 143)(font "Arial" ))
|
||||
(text "0.00" (rect 129 129 150 143)(font "Arial" ))
|
||||
(text "50.00" (rect 171 129 198 143)(font "Arial" ))
|
||||
(text "c1" (rect 63 147 75 161)(font "Arial" ))
|
||||
(text "16/33" (rect 85 147 112 161)(font "Arial" ))
|
||||
(text "0.00" (rect 129 147 150 161)(font "Arial" ))
|
||||
(text "50.00" (rect 171 147 198 161)(font "Arial" ))
|
||||
(text "c2" (rect 63 165 75 179)(font "Arial" ))
|
||||
(text "25/33" (rect 85 165 112 179)(font "Arial" ))
|
||||
(text "0.00" (rect 129 165 150 179)(font "Arial" ))
|
||||
(text "50.00" (rect 171 165 198 179)(font "Arial" ))
|
||||
(text "c3" (rect 63 183 75 197)(font "Arial" ))
|
||||
(text "16/11" (rect 85 183 112 197)(font "Arial" ))
|
||||
(text "0.00" (rect 129 183 150 197)(font "Arial" ))
|
||||
(text "50.00" (rect 171 183 198 197)(font "Arial" ))
|
||||
(line (pt 0 0)(pt 305 0)(line_width 1))
|
||||
(line (pt 305 0)(pt 305 233)(line_width 1))
|
||||
(line (pt 0 233)(pt 305 233)(line_width 1))
|
||||
(line (pt 0 0)(pt 0 233)(line_width 1))
|
||||
(line (pt 56 108)(pt 208 108)(line_width 1))
|
||||
(line (pt 56 125)(pt 208 125)(line_width 1))
|
||||
(line (pt 56 143)(pt 208 143)(line_width 1))
|
||||
(line (pt 56 161)(pt 208 161)(line_width 1))
|
||||
(line (pt 56 179)(pt 208 179)(line_width 1))
|
||||
(line (pt 56 197)(pt 208 197)(line_width 1))
|
||||
(line (pt 56 108)(pt 56 197)(line_width 1))
|
||||
(line (pt 82 108)(pt 82 197)(line_width 3))
|
||||
(line (pt 118 108)(pt 118 197)(line_width 3))
|
||||
(line (pt 163 108)(pt 163 197)(line_width 3))
|
||||
(line (pt 207 108)(pt 207 197)(line_width 1))
|
||||
(line (pt 48 56)(pt 272 56)(line_width 1))
|
||||
(line (pt 272 56)(pt 272 216)(line_width 1))
|
||||
(line (pt 48 216)(pt 272 216)(line_width 1))
|
||||
(line (pt 48 56)(pt 48 216)(line_width 1))
|
||||
)
|
||||
)
|
||||
26
FPGA_quartus_GE/altip_orig/altpll3.inc
Normal file
26
FPGA_quartus_GE/altip_orig/altpll3.inc
Normal file
@@ -0,0 +1,26 @@
|
||||
--Copyright (C) 1991-2010 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
FUNCTION altpll3
|
||||
(
|
||||
inclk0
|
||||
)
|
||||
|
||||
RETURNS (
|
||||
c0,
|
||||
c1,
|
||||
c2,
|
||||
c3
|
||||
);
|
||||
12
FPGA_quartus_GE/altip_orig/altpll3.ppf
Normal file
12
FPGA_quartus_GE/altip_orig/altpll3.ppf
Normal file
@@ -0,0 +1,12 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<!DOCTYPE pinplan>
|
||||
<pinplan intended_family="Cyclone III" variation_name="altpll3" megafunction_name="ALTPLL" specifies="all_ports">
|
||||
<global>
|
||||
<pin name="inclk0" direction="input" scope="external" source="clock" />
|
||||
<pin name="c0" direction="output" scope="external" source="clock" />
|
||||
<pin name="c1" direction="output" scope="external" source="clock" />
|
||||
<pin name="c2" direction="output" scope="external" source="clock" />
|
||||
<pin name="c3" direction="output" scope="external" source="clock" />
|
||||
|
||||
</global>
|
||||
</pinplan>
|
||||
7
FPGA_quartus_GE/altip_orig/altpll3.qip
Normal file
7
FPGA_quartus_GE/altip_orig/altpll3.qip
Normal file
@@ -0,0 +1,7 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
|
||||
set_global_assignment -name IP_TOOL_VERSION "9.1"
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll3.vhd"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll3.bsf"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll3.inc"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll3.cmp"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll3.ppf"]
|
||||
445
FPGA_quartus_GE/altip_orig/altpll3.vhd
Normal file
445
FPGA_quartus_GE/altip_orig/altpll3.vhd
Normal file
@@ -0,0 +1,445 @@
|
||||
-- megafunction wizard: %ALTPLL%
|
||||
-- GENERATION: STANDARD
|
||||
-- VERSION: WM1.0
|
||||
-- MODULE: altpll
|
||||
|
||||
-- ============================================================
|
||||
-- File Name: altpll3.vhd
|
||||
-- Megafunction Name(s):
|
||||
-- altpll
|
||||
--
|
||||
-- Simulation Library Files(s):
|
||||
-- altera_mf
|
||||
-- ============================================================
|
||||
-- ************************************************************
|
||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
--
|
||||
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
|
||||
-- ************************************************************
|
||||
|
||||
|
||||
--Copyright (C) 1991-2010 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
|
||||
LIBRARY altera_mf;
|
||||
USE altera_mf.all;
|
||||
|
||||
ENTITY altpll3 IS
|
||||
PORT
|
||||
(
|
||||
inclk0 : IN STD_LOGIC := '0';
|
||||
c0 : OUT STD_LOGIC ;
|
||||
c1 : OUT STD_LOGIC ;
|
||||
c2 : OUT STD_LOGIC ;
|
||||
c3 : OUT STD_LOGIC
|
||||
);
|
||||
END altpll3;
|
||||
|
||||
|
||||
ARCHITECTURE SYN OF altpll3 IS
|
||||
|
||||
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
|
||||
SIGNAL sub_wire1 : STD_LOGIC ;
|
||||
SIGNAL sub_wire2 : STD_LOGIC ;
|
||||
SIGNAL sub_wire3 : STD_LOGIC ;
|
||||
SIGNAL sub_wire4 : STD_LOGIC ;
|
||||
SIGNAL sub_wire5 : STD_LOGIC ;
|
||||
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0);
|
||||
SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0);
|
||||
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0);
|
||||
|
||||
|
||||
|
||||
COMPONENT altpll
|
||||
GENERIC (
|
||||
bandwidth_type : STRING;
|
||||
clk0_divide_by : NATURAL;
|
||||
clk0_duty_cycle : NATURAL;
|
||||
clk0_multiply_by : NATURAL;
|
||||
clk0_phase_shift : STRING;
|
||||
clk1_divide_by : NATURAL;
|
||||
clk1_duty_cycle : NATURAL;
|
||||
clk1_multiply_by : NATURAL;
|
||||
clk1_phase_shift : STRING;
|
||||
clk2_divide_by : NATURAL;
|
||||
clk2_duty_cycle : NATURAL;
|
||||
clk2_multiply_by : NATURAL;
|
||||
clk2_phase_shift : STRING;
|
||||
clk3_divide_by : NATURAL;
|
||||
clk3_duty_cycle : NATURAL;
|
||||
clk3_multiply_by : NATURAL;
|
||||
clk3_phase_shift : STRING;
|
||||
compensate_clock : STRING;
|
||||
inclk0_input_frequency : NATURAL;
|
||||
intended_device_family : STRING;
|
||||
lpm_type : STRING;
|
||||
operation_mode : STRING;
|
||||
pll_type : STRING;
|
||||
port_activeclock : STRING;
|
||||
port_areset : STRING;
|
||||
port_clkbad0 : STRING;
|
||||
port_clkbad1 : STRING;
|
||||
port_clkloss : STRING;
|
||||
port_clkswitch : STRING;
|
||||
port_configupdate : STRING;
|
||||
port_fbin : STRING;
|
||||
port_inclk0 : STRING;
|
||||
port_inclk1 : STRING;
|
||||
port_locked : STRING;
|
||||
port_pfdena : STRING;
|
||||
port_phasecounterselect : STRING;
|
||||
port_phasedone : STRING;
|
||||
port_phasestep : STRING;
|
||||
port_phaseupdown : STRING;
|
||||
port_pllena : STRING;
|
||||
port_scanaclr : STRING;
|
||||
port_scanclk : STRING;
|
||||
port_scanclkena : STRING;
|
||||
port_scandata : STRING;
|
||||
port_scandataout : STRING;
|
||||
port_scandone : STRING;
|
||||
port_scanread : STRING;
|
||||
port_scanwrite : STRING;
|
||||
port_clk0 : STRING;
|
||||
port_clk1 : STRING;
|
||||
port_clk2 : STRING;
|
||||
port_clk3 : STRING;
|
||||
port_clk4 : STRING;
|
||||
port_clk5 : STRING;
|
||||
port_clkena0 : STRING;
|
||||
port_clkena1 : STRING;
|
||||
port_clkena2 : STRING;
|
||||
port_clkena3 : STRING;
|
||||
port_clkena4 : STRING;
|
||||
port_clkena5 : STRING;
|
||||
port_extclk0 : STRING;
|
||||
port_extclk1 : STRING;
|
||||
port_extclk2 : STRING;
|
||||
port_extclk3 : STRING;
|
||||
width_clock : NATURAL
|
||||
);
|
||||
PORT (
|
||||
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
|
||||
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
BEGIN
|
||||
sub_wire7_bv(0 DOWNTO 0) <= "0";
|
||||
sub_wire7 <= To_stdlogicvector(sub_wire7_bv);
|
||||
sub_wire4 <= sub_wire0(3);
|
||||
sub_wire3 <= sub_wire0(2);
|
||||
sub_wire2 <= sub_wire0(1);
|
||||
sub_wire1 <= sub_wire0(0);
|
||||
c0 <= sub_wire1;
|
||||
c1 <= sub_wire2;
|
||||
c2 <= sub_wire3;
|
||||
c3 <= sub_wire4;
|
||||
sub_wire5 <= inclk0;
|
||||
sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5;
|
||||
|
||||
altpll_component : altpll
|
||||
GENERIC MAP (
|
||||
bandwidth_type => "AUTO",
|
||||
clk0_divide_by => 33,
|
||||
clk0_duty_cycle => 50,
|
||||
clk0_multiply_by => 2,
|
||||
clk0_phase_shift => "0",
|
||||
clk1_divide_by => 33,
|
||||
clk1_duty_cycle => 50,
|
||||
clk1_multiply_by => 16,
|
||||
clk1_phase_shift => "0",
|
||||
clk2_divide_by => 33,
|
||||
clk2_duty_cycle => 50,
|
||||
clk2_multiply_by => 25,
|
||||
clk2_phase_shift => "0",
|
||||
clk3_divide_by => 11,
|
||||
clk3_duty_cycle => 50,
|
||||
clk3_multiply_by => 16,
|
||||
clk3_phase_shift => "0",
|
||||
compensate_clock => "CLK1",
|
||||
inclk0_input_frequency => 30303,
|
||||
intended_device_family => "Cyclone III",
|
||||
lpm_type => "altpll",
|
||||
operation_mode => "SOURCE_SYNCHRONOUS",
|
||||
pll_type => "AUTO",
|
||||
port_activeclock => "PORT_UNUSED",
|
||||
port_areset => "PORT_UNUSED",
|
||||
port_clkbad0 => "PORT_UNUSED",
|
||||
port_clkbad1 => "PORT_UNUSED",
|
||||
port_clkloss => "PORT_UNUSED",
|
||||
port_clkswitch => "PORT_UNUSED",
|
||||
port_configupdate => "PORT_UNUSED",
|
||||
port_fbin => "PORT_UNUSED",
|
||||
port_inclk0 => "PORT_USED",
|
||||
port_inclk1 => "PORT_UNUSED",
|
||||
port_locked => "PORT_UNUSED",
|
||||
port_pfdena => "PORT_UNUSED",
|
||||
port_phasecounterselect => "PORT_UNUSED",
|
||||
port_phasedone => "PORT_UNUSED",
|
||||
port_phasestep => "PORT_UNUSED",
|
||||
port_phaseupdown => "PORT_UNUSED",
|
||||
port_pllena => "PORT_UNUSED",
|
||||
port_scanaclr => "PORT_UNUSED",
|
||||
port_scanclk => "PORT_UNUSED",
|
||||
port_scanclkena => "PORT_UNUSED",
|
||||
port_scandata => "PORT_UNUSED",
|
||||
port_scandataout => "PORT_UNUSED",
|
||||
port_scandone => "PORT_UNUSED",
|
||||
port_scanread => "PORT_UNUSED",
|
||||
port_scanwrite => "PORT_UNUSED",
|
||||
port_clk0 => "PORT_USED",
|
||||
port_clk1 => "PORT_USED",
|
||||
port_clk2 => "PORT_USED",
|
||||
port_clk3 => "PORT_USED",
|
||||
port_clk4 => "PORT_UNUSED",
|
||||
port_clk5 => "PORT_UNUSED",
|
||||
port_clkena0 => "PORT_UNUSED",
|
||||
port_clkena1 => "PORT_UNUSED",
|
||||
port_clkena2 => "PORT_UNUSED",
|
||||
port_clkena3 => "PORT_UNUSED",
|
||||
port_clkena4 => "PORT_UNUSED",
|
||||
port_clkena5 => "PORT_UNUSED",
|
||||
port_extclk0 => "PORT_UNUSED",
|
||||
port_extclk1 => "PORT_UNUSED",
|
||||
port_extclk2 => "PORT_UNUSED",
|
||||
port_extclk3 => "PORT_UNUSED",
|
||||
width_clock => 5
|
||||
)
|
||||
PORT MAP (
|
||||
inclk => sub_wire6,
|
||||
clk => sub_wire0
|
||||
);
|
||||
|
||||
|
||||
|
||||
END SYN;
|
||||
|
||||
-- ============================================================
|
||||
-- CNX file retrieval info
|
||||
-- ============================================================
|
||||
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
|
||||
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c1"
|
||||
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
|
||||
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
|
||||
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "33"
|
||||
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "33"
|
||||
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "33"
|
||||
-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "33"
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "2.000000"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "16.000000"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "25.000000"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "48.000000"
|
||||
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||||
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
|
||||
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
|
||||
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
|
||||
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.000"
|
||||
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
|
||||
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
|
||||
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000"
|
||||
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
|
||||
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
|
||||
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||||
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
|
||||
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
|
||||
-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
|
||||
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
|
||||
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "16"
|
||||
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "25"
|
||||
-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "48"
|
||||
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "2.00000000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "16.00000000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "25.00000000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "160.00000000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
|
||||
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
|
||||
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll3.mif"
|
||||
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
|
||||
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
|
||||
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
|
||||
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
|
||||
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
|
||||
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
|
||||
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1"
|
||||
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||||
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
|
||||
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
|
||||
-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
|
||||
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
||||
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
|
||||
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
|
||||
-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
|
||||
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
|
||||
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "33"
|
||||
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
|
||||
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
|
||||
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "33"
|
||||
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "16"
|
||||
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
||||
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "33"
|
||||
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "25"
|
||||
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
|
||||
-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "11"
|
||||
-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "16"
|
||||
-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
|
||||
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK1"
|
||||
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303"
|
||||
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
|
||||
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS"
|
||||
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
|
||||
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
|
||||
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
|
||||
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
|
||||
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||||
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
|
||||
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
|
||||
-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
|
||||
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
||||
-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
|
||||
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
|
||||
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.vhd TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.ppf TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.inc TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.cmp TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.bsf TRUE FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_inst.vhd FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_waveforms.html TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_wave*.jpg FALSE
|
||||
-- Retrieval info: LIB_FILE: altera_mf
|
||||
125
FPGA_quartus_GE/altip_orig/altpll4.bsf
Normal file
125
FPGA_quartus_GE/altip_orig/altpll4.bsf
Normal file
@@ -0,0 +1,125 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2010 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 0 0 376 232)
|
||||
(text "altpll4" (rect 168 1 215 20)(font "Arial" (font_size 10)))
|
||||
(text "inst" (rect 8 213 31 228)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 72)
|
||||
(input)
|
||||
(text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8)))
|
||||
(text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 72)(pt 88 72)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 96)
|
||||
(input)
|
||||
(text "areset" (rect 0 0 42 16)(font "Arial" (font_size 8)))
|
||||
(text "areset" (rect 4 80 40 96)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 96)(pt 88 96)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 120)
|
||||
(input)
|
||||
(text "scanclk" (rect 0 0 53 16)(font "Arial" (font_size 8)))
|
||||
(text "scanclk" (rect 4 104 49 120)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 120)(pt 88 120)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 144)
|
||||
(input)
|
||||
(text "scandata" (rect 0 0 62 16)(font "Arial" (font_size 8)))
|
||||
(text "scandata" (rect 4 128 57 144)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 144)(pt 88 144)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 168)
|
||||
(input)
|
||||
(text "scanclkena" (rect 0 0 77 16)(font "Arial" (font_size 8)))
|
||||
(text "scanclkena" (rect 4 152 70 168)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 168)(pt 88 168)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 192)
|
||||
(input)
|
||||
(text "configupdate" (rect 0 0 86 16)(font "Arial" (font_size 8)))
|
||||
(text "configupdate" (rect 4 176 77 192)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 192)(pt 88 192)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 376 72)
|
||||
(output)
|
||||
(text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8)))
|
||||
(text "c0" (rect 359 56 373 72)(font "Arial" (font_size 8)))
|
||||
(line (pt 376 72)(pt 288 72)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 376 96)
|
||||
(output)
|
||||
(text "scandataout" (rect 0 0 83 16)(font "Arial" (font_size 8)))
|
||||
(text "scandataout" (rect 302 80 373 96)(font "Arial" (font_size 8)))
|
||||
(line (pt 376 96)(pt 288 96)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 376 120)
|
||||
(output)
|
||||
(text "scandone" (rect 0 0 66 16)(font "Arial" (font_size 8)))
|
||||
(text "scandone" (rect 317 104 373 120)(font "Arial" (font_size 8)))
|
||||
(line (pt 376 120)(pt 288 120)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 376 144)
|
||||
(output)
|
||||
(text "locked" (rect 0 0 44 16)(font "Arial" (font_size 8)))
|
||||
(text "locked" (rect 335 128 373 144)(font "Arial" (font_size 8)))
|
||||
(line (pt 376 144)(pt 288 144)(line_width 1))
|
||||
)
|
||||
(drawing
|
||||
(text "Cyclone III" (rect 301 214 349 228)(font "Arial" ))
|
||||
(text "inclk0 frequency: 48.000 MHz" (rect 98 123 241 137)(font "Arial" ))
|
||||
(text "Operation Mode: Normal" (rect 98 140 213 154)(font "Arial" ))
|
||||
(text "Clk " (rect 99 167 116 181)(font "Arial" ))
|
||||
(text "Ratio" (rect 125 167 149 181)(font "Arial" ))
|
||||
(text "Ph (dg)" (rect 159 167 194 181)(font "Arial" ))
|
||||
(text "DC (%)" (rect 204 167 239 181)(font "Arial" ))
|
||||
(text "c0" (rect 103 185 115 199)(font "Arial" ))
|
||||
(text "2/1" (rect 131 185 146 199)(font "Arial" ))
|
||||
(text "0.00" (rect 167 185 188 199)(font "Arial" ))
|
||||
(text "50.00" (rect 209 185 236 199)(font "Arial" ))
|
||||
(line (pt 0 0)(pt 377 0)(line_width 1))
|
||||
(line (pt 377 0)(pt 377 233)(line_width 1))
|
||||
(line (pt 0 233)(pt 377 233)(line_width 1))
|
||||
(line (pt 0 0)(pt 0 233)(line_width 1))
|
||||
(line (pt 96 164)(pt 246 164)(line_width 1))
|
||||
(line (pt 96 181)(pt 246 181)(line_width 1))
|
||||
(line (pt 96 199)(pt 246 199)(line_width 1))
|
||||
(line (pt 96 164)(pt 96 199)(line_width 1))
|
||||
(line (pt 122 164)(pt 122 199)(line_width 3))
|
||||
(line (pt 156 164)(pt 156 199)(line_width 3))
|
||||
(line (pt 201 164)(pt 201 199)(line_width 3))
|
||||
(line (pt 245 164)(pt 245 199)(line_width 1))
|
||||
(line (pt 88 56)(pt 288 56)(line_width 1))
|
||||
(line (pt 288 56)(pt 288 216)(line_width 1))
|
||||
(line (pt 88 216)(pt 288 216)(line_width 1))
|
||||
(line (pt 88 56)(pt 88 216)(line_width 1))
|
||||
)
|
||||
)
|
||||
31
FPGA_quartus_GE/altip_orig/altpll4.inc
Normal file
31
FPGA_quartus_GE/altip_orig/altpll4.inc
Normal file
@@ -0,0 +1,31 @@
|
||||
--Copyright (C) 1991-2010 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
FUNCTION altpll4
|
||||
(
|
||||
areset,
|
||||
configupdate,
|
||||
inclk0,
|
||||
scanclk,
|
||||
scanclkena,
|
||||
scandata
|
||||
)
|
||||
|
||||
RETURNS (
|
||||
c0,
|
||||
locked,
|
||||
scandataout,
|
||||
scandone
|
||||
);
|
||||
174
FPGA_quartus_GE/altip_orig/altpll4.mif
Normal file
174
FPGA_quartus_GE/altip_orig/altpll4.mif
Normal file
@@ -0,0 +1,174 @@
|
||||
-- Copyright (C) 1991-2010 Altera Corporation
|
||||
-- Your use of Altera Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Altera Program License
|
||||
-- Subscription Agreement, Altera MegaCore Function License
|
||||
-- Agreement, or other applicable license agreement, including,
|
||||
-- without limitation, that your use is for the sole purpose of
|
||||
-- programming logic devices manufactured by Altera and sold by
|
||||
-- Altera or its authorized distributors. Please refer to the
|
||||
-- applicable agreement for further details.
|
||||
|
||||
-- MIF file representing initial state of PLL Scan Chain
|
||||
-- Device Family: Cyclone III
|
||||
-- Device Part: -
|
||||
-- Device Speed Grade: 8
|
||||
-- PLL Scan Chain: Fast PLL (144 bits)
|
||||
-- File Name: C:\FireBee\FPGA\altpll4.mif
|
||||
-- Generated: Mon Dec 06 01:47:24 2010
|
||||
|
||||
WIDTH=1;
|
||||
DEPTH=144;
|
||||
|
||||
ADDRESS_RADIX=UNS;
|
||||
DATA_RADIX=UNS;
|
||||
|
||||
CONTENT BEGIN
|
||||
0 : 0; -- Reserved Bits = 0 (1 bit(s))
|
||||
1 : 0; -- Reserved Bits = 0 (1 bit(s))
|
||||
2 : 0; -- Loop Filter Capacitance = 0 (2 bit(s)) (Setting 0)
|
||||
3 : 0;
|
||||
4 : 1; -- Loop Filter Resistance = 27 (5 bit(s)) (Setting 27)
|
||||
5 : 1;
|
||||
6 : 0;
|
||||
7 : 1;
|
||||
8 : 1;
|
||||
9 : 0; -- VCO Post Scale = 0 (1 bit(s)) (VCO post-scale divider counter value = 2)
|
||||
10 : 0; -- Reserved Bits = 0 (5 bit(s))
|
||||
11 : 0;
|
||||
12 : 0;
|
||||
13 : 0;
|
||||
14 : 0;
|
||||
15 : 0; -- Charge Pump Current = 1 (3 bit(s)) (Setting 1)
|
||||
16 : 0;
|
||||
17 : 1;
|
||||
18 : 1; -- N counter: Bypass = 1 (1 bit(s))
|
||||
19 : 0; -- N counter: High Count = 0 (8 bit(s))
|
||||
20 : 0;
|
||||
21 : 0;
|
||||
22 : 0;
|
||||
23 : 0;
|
||||
24 : 0;
|
||||
25 : 0;
|
||||
26 : 0;
|
||||
27 : 0; -- N counter: Odd Division = 0 (1 bit(s))
|
||||
28 : 0; -- N counter: Low Count = 0 (8 bit(s))
|
||||
29 : 0;
|
||||
30 : 0;
|
||||
31 : 0;
|
||||
32 : 0;
|
||||
33 : 0;
|
||||
34 : 0;
|
||||
35 : 0;
|
||||
36 : 0; -- M counter: Bypass = 0 (1 bit(s))
|
||||
37 : 0; -- M counter: High Count = 6 (8 bit(s))
|
||||
38 : 0;
|
||||
39 : 0;
|
||||
40 : 0;
|
||||
41 : 0;
|
||||
42 : 1;
|
||||
43 : 1;
|
||||
44 : 0;
|
||||
45 : 0; -- M counter: Odd Division = 0 (1 bit(s))
|
||||
46 : 0; -- M counter: Low Count = 6 (8 bit(s))
|
||||
47 : 0;
|
||||
48 : 0;
|
||||
49 : 0;
|
||||
50 : 0;
|
||||
51 : 1;
|
||||
52 : 1;
|
||||
53 : 0;
|
||||
54 : 0; -- clk0 counter: Bypass = 0 (1 bit(s))
|
||||
55 : 0; -- clk0 counter: High Count = 3 (8 bit(s))
|
||||
56 : 0;
|
||||
57 : 0;
|
||||
58 : 0;
|
||||
59 : 0;
|
||||
60 : 0;
|
||||
61 : 1;
|
||||
62 : 1;
|
||||
63 : 0; -- clk0 counter: Odd Division = 0 (1 bit(s))
|
||||
64 : 0; -- clk0 counter: Low Count = 3 (8 bit(s))
|
||||
65 : 0;
|
||||
66 : 0;
|
||||
67 : 0;
|
||||
68 : 0;
|
||||
69 : 0;
|
||||
70 : 1;
|
||||
71 : 1;
|
||||
72 : 1; -- clk1 counter: Bypass = 1 (1 bit(s))
|
||||
73 : 0; -- clk1 counter: High Count = 0 (8 bit(s))
|
||||
74 : 0;
|
||||
75 : 0;
|
||||
76 : 0;
|
||||
77 : 0;
|
||||
78 : 0;
|
||||
79 : 0;
|
||||
80 : 0;
|
||||
81 : 0; -- clk1 counter: Odd Division = 0 (1 bit(s))
|
||||
82 : 0; -- clk1 counter: Low Count = 0 (8 bit(s))
|
||||
83 : 0;
|
||||
84 : 0;
|
||||
85 : 0;
|
||||
86 : 0;
|
||||
87 : 0;
|
||||
88 : 0;
|
||||
89 : 0;
|
||||
90 : 1; -- clk2 counter: Bypass = 1 (1 bit(s))
|
||||
91 : 0; -- clk2 counter: High Count = 0 (8 bit(s))
|
||||
92 : 0;
|
||||
93 : 0;
|
||||
94 : 0;
|
||||
95 : 0;
|
||||
96 : 0;
|
||||
97 : 0;
|
||||
98 : 0;
|
||||
99 : 0; -- clk2 counter: Odd Division = 0 (1 bit(s))
|
||||
100 : 0; -- clk2 counter: Low Count = 0 (8 bit(s))
|
||||
101 : 0;
|
||||
102 : 0;
|
||||
103 : 0;
|
||||
104 : 0;
|
||||
105 : 0;
|
||||
106 : 0;
|
||||
107 : 0;
|
||||
108 : 1; -- clk3 counter: Bypass = 1 (1 bit(s))
|
||||
109 : 0; -- clk3 counter: High Count = 0 (8 bit(s))
|
||||
110 : 0;
|
||||
111 : 0;
|
||||
112 : 0;
|
||||
113 : 0;
|
||||
114 : 0;
|
||||
115 : 0;
|
||||
116 : 0;
|
||||
117 : 0; -- clk3 counter: Odd Division = 0 (1 bit(s))
|
||||
118 : 0; -- clk3 counter: Low Count = 0 (8 bit(s))
|
||||
119 : 0;
|
||||
120 : 0;
|
||||
121 : 0;
|
||||
122 : 0;
|
||||
123 : 0;
|
||||
124 : 0;
|
||||
125 : 0;
|
||||
126 : 1; -- clk4 counter: Bypass = 1 (1 bit(s))
|
||||
127 : 0; -- clk4 counter: High Count = 0 (8 bit(s))
|
||||
128 : 0;
|
||||
129 : 0;
|
||||
130 : 0;
|
||||
131 : 0;
|
||||
132 : 0;
|
||||
133 : 0;
|
||||
134 : 0;
|
||||
135 : 0; -- clk4 counter: Odd Division = 0 (1 bit(s))
|
||||
136 : 0; -- clk4 counter: Low Count = 0 (8 bit(s))
|
||||
137 : 0;
|
||||
138 : 0;
|
||||
139 : 0;
|
||||
140 : 0;
|
||||
141 : 0;
|
||||
142 : 0;
|
||||
143 : 0;
|
||||
END;
|
||||
17
FPGA_quartus_GE/altip_orig/altpll4.ppf
Normal file
17
FPGA_quartus_GE/altip_orig/altpll4.ppf
Normal file
@@ -0,0 +1,17 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<!DOCTYPE pinplan>
|
||||
<pinplan intended_family="Cyclone III" variation_name="altpll4" megafunction_name="ALTPLL" specifies="all_ports">
|
||||
<global>
|
||||
<pin name="areset" direction="input" scope="external" />
|
||||
<pin name="configupdate" direction="input" scope="external" />
|
||||
<pin name="inclk0" direction="input" scope="external" source="clock" />
|
||||
<pin name="scanclk" direction="input" scope="external" source="clock" />
|
||||
<pin name="scanclkena" direction="input" scope="external" />
|
||||
<pin name="scandata" direction="input" scope="external" />
|
||||
<pin name="c0" direction="output" scope="external" source="clock" />
|
||||
<pin name="locked" direction="output" scope="external" />
|
||||
<pin name="scandataout" direction="output" scope="external" />
|
||||
<pin name="scandone" direction="output" scope="external" />
|
||||
|
||||
</global>
|
||||
</pinplan>
|
||||
7
FPGA_quartus_GE/altip_orig/altpll4.qip
Normal file
7
FPGA_quartus_GE/altip_orig/altpll4.qip
Normal file
@@ -0,0 +1,7 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
|
||||
set_global_assignment -name IP_TOOL_VERSION "9.1"
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.tdf"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.bsf"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.inc"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.cmp"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.ppf"]
|
||||
298
FPGA_quartus_GE/altip_orig/altpll4.tdf
Normal file
298
FPGA_quartus_GE/altip_orig/altpll4.tdf
Normal file
@@ -0,0 +1,298 @@
|
||||
-- megafunction wizard: %ALTPLL%
|
||||
-- GENERATION: STANDARD
|
||||
-- VERSION: WM1.0
|
||||
-- MODULE: altpll
|
||||
|
||||
-- ============================================================
|
||||
-- File Name: altpll4.tdf
|
||||
-- Megafunction Name(s):
|
||||
-- altpll
|
||||
--
|
||||
-- Simulation Library Files(s):
|
||||
-- altera_mf
|
||||
-- ============================================================
|
||||
-- ************************************************************
|
||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
--
|
||||
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
|
||||
-- ************************************************************
|
||||
|
||||
|
||||
--Copyright (C) 1991-2010 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
INCLUDE "altpll.inc";
|
||||
|
||||
|
||||
|
||||
SUBDESIGN altpll4
|
||||
(
|
||||
areset : INPUT = GND;
|
||||
configupdate : INPUT = GND;
|
||||
inclk0 : INPUT = GND;
|
||||
scanclk : INPUT = VCC;
|
||||
scanclkena : INPUT = GND;
|
||||
scandata : INPUT = GND;
|
||||
c0 : OUTPUT;
|
||||
locked : OUTPUT;
|
||||
scandataout : OUTPUT;
|
||||
scandone : OUTPUT;
|
||||
)
|
||||
|
||||
VARIABLE
|
||||
|
||||
altpll_component : altpll WITH (
|
||||
BANDWIDTH_TYPE = "AUTO",
|
||||
CLK0_DIVIDE_BY = 1,
|
||||
CLK0_DUTY_CYCLE = 50,
|
||||
CLK0_MULTIPLY_BY = 2,
|
||||
CLK0_PHASE_SHIFT = "0",
|
||||
COMPENSATE_CLOCK = "CLK0",
|
||||
INCLK0_INPUT_FREQUENCY = 20833,
|
||||
INTENDED_DEVICE_FAMILY = "Cyclone III",
|
||||
LPM_TYPE = "altpll",
|
||||
OPERATION_MODE = "NORMAL",
|
||||
PLL_TYPE = "AUTO",
|
||||
PORT_ACTIVECLOCK = "PORT_UNUSED",
|
||||
PORT_ARESET = "PORT_USED",
|
||||
PORT_CLKBAD0 = "PORT_UNUSED",
|
||||
PORT_CLKBAD1 = "PORT_UNUSED",
|
||||
PORT_CLKLOSS = "PORT_UNUSED",
|
||||
PORT_CLKSWITCH = "PORT_UNUSED",
|
||||
PORT_CONFIGUPDATE = "PORT_USED",
|
||||
PORT_FBIN = "PORT_UNUSED",
|
||||
PORT_INCLK0 = "PORT_USED",
|
||||
PORT_INCLK1 = "PORT_UNUSED",
|
||||
PORT_LOCKED = "PORT_USED",
|
||||
PORT_PFDENA = "PORT_UNUSED",
|
||||
PORT_PHASECOUNTERSELECT = "PORT_UNUSED",
|
||||
PORT_PHASEDONE = "PORT_UNUSED",
|
||||
PORT_PHASESTEP = "PORT_UNUSED",
|
||||
PORT_PHASEUPDOWN = "PORT_UNUSED",
|
||||
PORT_PLLENA = "PORT_UNUSED",
|
||||
PORT_SCANACLR = "PORT_UNUSED",
|
||||
PORT_SCANCLK = "PORT_USED",
|
||||
PORT_SCANCLKENA = "PORT_USED",
|
||||
PORT_SCANDATA = "PORT_USED",
|
||||
PORT_SCANDATAOUT = "PORT_USED",
|
||||
PORT_SCANDONE = "PORT_USED",
|
||||
PORT_SCANREAD = "PORT_UNUSED",
|
||||
PORT_SCANWRITE = "PORT_UNUSED",
|
||||
PORT_clk0 = "PORT_USED",
|
||||
PORT_clk1 = "PORT_UNUSED",
|
||||
PORT_clk2 = "PORT_UNUSED",
|
||||
PORT_clk3 = "PORT_UNUSED",
|
||||
PORT_clk4 = "PORT_UNUSED",
|
||||
PORT_clk5 = "PORT_UNUSED",
|
||||
PORT_clkena0 = "PORT_UNUSED",
|
||||
PORT_clkena1 = "PORT_UNUSED",
|
||||
PORT_clkena2 = "PORT_UNUSED",
|
||||
PORT_clkena3 = "PORT_UNUSED",
|
||||
PORT_clkena4 = "PORT_UNUSED",
|
||||
PORT_clkena5 = "PORT_UNUSED",
|
||||
PORT_extclk0 = "PORT_UNUSED",
|
||||
PORT_extclk1 = "PORT_UNUSED",
|
||||
PORT_extclk2 = "PORT_UNUSED",
|
||||
PORT_extclk3 = "PORT_UNUSED",
|
||||
SELF_RESET_ON_LOSS_LOCK = "OFF",
|
||||
WIDTH_CLOCK = 5,
|
||||
scan_chain_mif_file = "altpll4.mif"
|
||||
);
|
||||
|
||||
BEGIN
|
||||
|
||||
c0 = altpll_component.clk[0..0];
|
||||
scandone = altpll_component.scandone;
|
||||
scandataout = altpll_component.scandataout;
|
||||
locked = altpll_component.locked;
|
||||
altpll_component.scanclkena = scanclkena;
|
||||
altpll_component.inclk[0..0] = inclk0;
|
||||
altpll_component.inclk[1..1] = GND;
|
||||
altpll_component.scandata = scandata;
|
||||
altpll_component.areset = areset;
|
||||
altpll_component.scanclk = scanclk;
|
||||
altpll_component.configupdate = configupdate;
|
||||
END;
|
||||
|
||||
|
||||
|
||||
-- ============================================================
|
||||
-- CNX file retrieval info
|
||||
-- ============================================================
|
||||
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
|
||||
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
|
||||
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
|
||||
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
|
||||
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "96.000000"
|
||||
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||||
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
|
||||
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
|
||||
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
|
||||
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.000"
|
||||
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
|
||||
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
|
||||
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
|
||||
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "336.000"
|
||||
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
|
||||
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||||
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
|
||||
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "144.00000000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
|
||||
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
|
||||
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll4.mif"
|
||||
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "1"
|
||||
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
|
||||
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
|
||||
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
|
||||
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
|
||||
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
|
||||
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
|
||||
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||||
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
||||
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
|
||||
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
|
||||
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
|
||||
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
|
||||
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20833"
|
||||
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
|
||||
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
|
||||
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
|
||||
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
|
||||
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
|
||||
-- Retrieval info: CONSTANT: scan_chain_mif_file STRING "altpll4.mif"
|
||||
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
|
||||
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
|
||||
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||||
-- Retrieval info: USED_PORT: configupdate 0 0 0 0 INPUT GND "configupdate"
|
||||
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
|
||||
-- Retrieval info: USED_PORT: scanclk 0 0 0 0 INPUT_CLK_EXT VCC "scanclk"
|
||||
-- Retrieval info: USED_PORT: scanclkena 0 0 0 0 INPUT GND "scanclkena"
|
||||
-- Retrieval info: USED_PORT: scandata 0 0 0 0 INPUT GND "scandata"
|
||||
-- Retrieval info: USED_PORT: scandataout 0 0 0 0 OUTPUT VCC "scandataout"
|
||||
-- Retrieval info: USED_PORT: scandone 0 0 0 0 OUTPUT VCC "scandone"
|
||||
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
|
||||
-- Retrieval info: CONNECT: scandone 0 0 0 0 @scandone 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
-- Retrieval info: CONNECT: @scandata 0 0 0 0 scandata 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @scanclkena 0 0 0 0 scanclkena 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @configupdate 0 0 0 0 configupdate 0 0 0 0
|
||||
-- Retrieval info: CONNECT: scandataout 0 0 0 0 @scandataout 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.tdf TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.ppf TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.inc TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.cmp TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.bsf TRUE FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4_inst.tdf FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.mif TRUE
|
||||
-- Retrieval info: LIB_FILE: altera_mf
|
||||
162
FPGA_quartus_GE/altip_orig/altpll_reconfig0.bsf
Normal file
162
FPGA_quartus_GE/altip_orig/altpll_reconfig0.bsf
Normal file
@@ -0,0 +1,162 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2010 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 0 0 216 296)
|
||||
(text "altpll_reconfig0" (rect 54 1 182 20)(font "Arial" (font_size 10)))
|
||||
(text "inst" (rect 8 277 31 292)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 40)
|
||||
(input)
|
||||
(text "reconfig" (rect 0 0 53 16)(font "Arial" (font_size 8)))
|
||||
(text "reconfig" (rect 20 32 65 48)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 40)(pt 16 40)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 56)
|
||||
(input)
|
||||
(text "read_param" (rect 0 0 80 16)(font "Arial" (font_size 8)))
|
||||
(text "read_param" (rect 20 48 88 64)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 56)(pt 16 56)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 72)
|
||||
(input)
|
||||
(text "write_param" (rect 0 0 82 16)(font "Arial" (font_size 8)))
|
||||
(text "write_param" (rect 20 64 90 80)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 72)(pt 16 72)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 96)
|
||||
(input)
|
||||
(text "data_in[8..0]" (rect 0 0 84 16)(font "Arial" (font_size 8)))
|
||||
(text "data_in[8..0]" (rect 20 88 92 104)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 96)(pt 16 96)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 112)
|
||||
(input)
|
||||
(text "counter_type[3..0]" (rect 0 0 123 16)(font "Arial" (font_size 8)))
|
||||
(text "counter_type[3..0]" (rect 20 104 125 120)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 112)(pt 16 112)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 128)
|
||||
(input)
|
||||
(text "counter_param[2..0]" (rect 0 0 136 16)(font "Arial" (font_size 8)))
|
||||
(text "counter_param[2..0]" (rect 20 120 136 136)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 128)(pt 16 128)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 168)
|
||||
(input)
|
||||
(text "pll_scandataout" (rect 0 0 107 16)(font "Arial" (font_size 8)))
|
||||
(text "pll_scandataout" (rect 20 160 111 176)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 168)(pt 16 168)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 184)
|
||||
(input)
|
||||
(text "pll_scandone" (rect 0 0 89 16)(font "Arial" (font_size 8)))
|
||||
(text "pll_scandone" (rect 20 176 96 192)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 184)(pt 16 184)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 208)
|
||||
(input)
|
||||
(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
|
||||
(text "clock" (rect 20 200 51 216)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 208)(pt 16 208)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 224)
|
||||
(input)
|
||||
(text "reset" (rect 0 0 34 16)(font "Arial" (font_size 8)))
|
||||
(text "reset" (rect 20 216 49 232)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 224)(pt 16 224)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 248)
|
||||
(input)
|
||||
(text "pll_areset_in" (rect 0 0 86 16)(font "Arial" (font_size 8)))
|
||||
(text "pll_areset_in" (rect 20 240 93 256)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 248)(pt 16 248)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 216 40)
|
||||
(output)
|
||||
(text "busy" (rect 0 0 33 16)(font "Arial" (font_size 8)))
|
||||
(text "busy" (rect 169 32 197 48)(font "Arial" (font_size 8)))
|
||||
(line (pt 216 40)(pt 200 40)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 216 96)
|
||||
(output)
|
||||
(text "data_out[8..0]" (rect 0 0 94 16)(font "Arial" (font_size 8)))
|
||||
(text "data_out[8..0]" (rect 117 88 197 104)(font "Arial" (font_size 8)))
|
||||
(line (pt 216 96)(pt 200 96)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 216 152)
|
||||
(output)
|
||||
(text "pll_scandata" (rect 0 0 86 16)(font "Arial" (font_size 8)))
|
||||
(text "pll_scandata" (rect 124 144 197 160)(font "Arial" (font_size 8)))
|
||||
(line (pt 216 152)(pt 200 152)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 216 168)
|
||||
(output)
|
||||
(text "pll_scanclk" (rect 0 0 76 16)(font "Arial" (font_size 8)))
|
||||
(text "pll_scanclk" (rect 132 160 197 176)(font "Arial" (font_size 8)))
|
||||
(line (pt 216 168)(pt 200 168)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 216 200)
|
||||
(output)
|
||||
(text "pll_scanclkena" (rect 0 0 101 16)(font "Arial" (font_size 8)))
|
||||
(text "pll_scanclkena" (rect 111 192 197 208)(font "Arial" (font_size 8)))
|
||||
(line (pt 216 200)(pt 200 200)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 216 216)
|
||||
(output)
|
||||
(text "pll_configupdate" (rect 0 0 109 16)(font "Arial" (font_size 8)))
|
||||
(text "pll_configupdate" (rect 104 208 197 224)(font "Arial" (font_size 8)))
|
||||
(line (pt 216 216)(pt 200 216)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 216 248)
|
||||
(output)
|
||||
(text "pll_areset" (rect 0 0 66 16)(font "Arial" (font_size 8)))
|
||||
(text "pll_areset" (rect 141 240 197 256)(font "Arial" (font_size 8)))
|
||||
(line (pt 216 248)(pt 200 248)(line_width 1))
|
||||
)
|
||||
(drawing
|
||||
(line (pt 0 0)(pt 217 0)(line_width 1))
|
||||
(line (pt 217 0)(pt 217 297)(line_width 1))
|
||||
(line (pt 0 297)(pt 217 297)(line_width 1))
|
||||
(line (pt 0 0)(pt 0 297)(line_width 1))
|
||||
(line (pt 16 24)(pt 201 24)(line_width 1))
|
||||
(line (pt 201 24)(pt 201 273)(line_width 1))
|
||||
(line (pt 16 273)(pt 201 273)(line_width 1))
|
||||
(line (pt 16 24)(pt 16 273)(line_width 1))
|
||||
)
|
||||
)
|
||||
5
FPGA_quartus_GE/altip_orig/altpll_reconfig0.qip
Normal file
5
FPGA_quartus_GE/altip_orig/altpll_reconfig0.qip
Normal file
@@ -0,0 +1,5 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ALTPLL_RECONFIG"
|
||||
set_global_assignment -name IP_TOOL_VERSION "9.1"
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll_reconfig0.tdf"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll_reconfig0.bsf"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll_reconfig0.cmp"]
|
||||
162
FPGA_quartus_GE/altip_orig/altpll_reconfig1.bsf
Normal file
162
FPGA_quartus_GE/altip_orig/altpll_reconfig1.bsf
Normal file
@@ -0,0 +1,162 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2010 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 0 0 216 296)
|
||||
(text "altpll_reconfig1" (rect 54 1 182 20)(font "Arial" (font_size 10)))
|
||||
(text "inst" (rect 8 277 31 292)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 40)
|
||||
(input)
|
||||
(text "reconfig" (rect 0 0 53 16)(font "Arial" (font_size 8)))
|
||||
(text "reconfig" (rect 20 32 65 48)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 40)(pt 16 40)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 56)
|
||||
(input)
|
||||
(text "read_param" (rect 0 0 80 16)(font "Arial" (font_size 8)))
|
||||
(text "read_param" (rect 20 48 88 64)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 56)(pt 16 56)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 72)
|
||||
(input)
|
||||
(text "write_param" (rect 0 0 82 16)(font "Arial" (font_size 8)))
|
||||
(text "write_param" (rect 20 64 90 80)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 72)(pt 16 72)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 96)
|
||||
(input)
|
||||
(text "data_in[8..0]" (rect 0 0 84 16)(font "Arial" (font_size 8)))
|
||||
(text "data_in[8..0]" (rect 20 88 92 104)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 96)(pt 16 96)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 112)
|
||||
(input)
|
||||
(text "counter_type[3..0]" (rect 0 0 123 16)(font "Arial" (font_size 8)))
|
||||
(text "counter_type[3..0]" (rect 20 104 125 120)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 112)(pt 16 112)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 128)
|
||||
(input)
|
||||
(text "counter_param[2..0]" (rect 0 0 136 16)(font "Arial" (font_size 8)))
|
||||
(text "counter_param[2..0]" (rect 20 120 136 136)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 128)(pt 16 128)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 168)
|
||||
(input)
|
||||
(text "pll_scandataout" (rect 0 0 107 16)(font "Arial" (font_size 8)))
|
||||
(text "pll_scandataout" (rect 20 160 111 176)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 168)(pt 16 168)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 184)
|
||||
(input)
|
||||
(text "pll_scandone" (rect 0 0 89 16)(font "Arial" (font_size 8)))
|
||||
(text "pll_scandone" (rect 20 176 96 192)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 184)(pt 16 184)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 208)
|
||||
(input)
|
||||
(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
|
||||
(text "clock" (rect 20 200 51 216)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 208)(pt 16 208)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 224)
|
||||
(input)
|
||||
(text "reset" (rect 0 0 34 16)(font "Arial" (font_size 8)))
|
||||
(text "reset" (rect 20 216 49 232)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 224)(pt 16 224)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 248)
|
||||
(input)
|
||||
(text "pll_areset_in" (rect 0 0 86 16)(font "Arial" (font_size 8)))
|
||||
(text "pll_areset_in" (rect 20 240 93 256)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 248)(pt 16 248)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 216 40)
|
||||
(output)
|
||||
(text "busy" (rect 0 0 33 16)(font "Arial" (font_size 8)))
|
||||
(text "busy" (rect 169 32 197 48)(font "Arial" (font_size 8)))
|
||||
(line (pt 216 40)(pt 200 40)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 216 96)
|
||||
(output)
|
||||
(text "data_out[8..0]" (rect 0 0 94 16)(font "Arial" (font_size 8)))
|
||||
(text "data_out[8..0]" (rect 117 88 197 104)(font "Arial" (font_size 8)))
|
||||
(line (pt 216 96)(pt 200 96)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 216 152)
|
||||
(output)
|
||||
(text "pll_scandata" (rect 0 0 86 16)(font "Arial" (font_size 8)))
|
||||
(text "pll_scandata" (rect 124 144 197 160)(font "Arial" (font_size 8)))
|
||||
(line (pt 216 152)(pt 200 152)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 216 168)
|
||||
(output)
|
||||
(text "pll_scanclk" (rect 0 0 76 16)(font "Arial" (font_size 8)))
|
||||
(text "pll_scanclk" (rect 132 160 197 176)(font "Arial" (font_size 8)))
|
||||
(line (pt 216 168)(pt 200 168)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 216 200)
|
||||
(output)
|
||||
(text "pll_scanclkena" (rect 0 0 101 16)(font "Arial" (font_size 8)))
|
||||
(text "pll_scanclkena" (rect 111 192 197 208)(font "Arial" (font_size 8)))
|
||||
(line (pt 216 200)(pt 200 200)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 216 216)
|
||||
(output)
|
||||
(text "pll_configupdate" (rect 0 0 109 16)(font "Arial" (font_size 8)))
|
||||
(text "pll_configupdate" (rect 104 208 197 224)(font "Arial" (font_size 8)))
|
||||
(line (pt 216 216)(pt 200 216)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 216 248)
|
||||
(output)
|
||||
(text "pll_areset" (rect 0 0 66 16)(font "Arial" (font_size 8)))
|
||||
(text "pll_areset" (rect 141 240 197 256)(font "Arial" (font_size 8)))
|
||||
(line (pt 216 248)(pt 200 248)(line_width 1))
|
||||
)
|
||||
(drawing
|
||||
(line (pt 0 0)(pt 217 0)(line_width 1))
|
||||
(line (pt 217 0)(pt 217 297)(line_width 1))
|
||||
(line (pt 0 297)(pt 217 297)(line_width 1))
|
||||
(line (pt 0 0)(pt 0 297)(line_width 1))
|
||||
(line (pt 16 24)(pt 201 24)(line_width 1))
|
||||
(line (pt 201 24)(pt 201 273)(line_width 1))
|
||||
(line (pt 16 273)(pt 201 273)(line_width 1))
|
||||
(line (pt 16 24)(pt 16 273)(line_width 1))
|
||||
)
|
||||
)
|
||||
39
FPGA_quartus_GE/altip_orig/altpll_reconfig1.inc
Normal file
39
FPGA_quartus_GE/altip_orig/altpll_reconfig1.inc
Normal file
@@ -0,0 +1,39 @@
|
||||
--Copyright (C) 1991-2010 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
FUNCTION altpll_reconfig1
|
||||
(
|
||||
clock,
|
||||
counter_param[2..0],
|
||||
counter_type[3..0],
|
||||
data_in[8..0],
|
||||
pll_areset_in,
|
||||
pll_scandataout,
|
||||
pll_scandone,
|
||||
read_param,
|
||||
reconfig,
|
||||
reset,
|
||||
write_param
|
||||
)
|
||||
|
||||
RETURNS (
|
||||
busy,
|
||||
data_out[8..0],
|
||||
pll_areset,
|
||||
pll_configupdate,
|
||||
pll_scanclk,
|
||||
pll_scanclkena,
|
||||
pll_scandata
|
||||
);
|
||||
6
FPGA_quartus_GE/altip_orig/altpll_reconfig1.qip
Normal file
6
FPGA_quartus_GE/altip_orig/altpll_reconfig1.qip
Normal file
@@ -0,0 +1,6 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ALTPLL_RECONFIG"
|
||||
set_global_assignment -name IP_TOOL_VERSION "9.1"
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll_reconfig1.tdf"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll_reconfig1.bsf"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll_reconfig1.inc"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll_reconfig1.cmp"]
|
||||
144
FPGA_quartus_GE/altip_orig/altpll_reconfig1.tdf
Normal file
144
FPGA_quartus_GE/altip_orig/altpll_reconfig1.tdf
Normal file
@@ -0,0 +1,144 @@
|
||||
-- megafunction wizard: %ALTPLL_RECONFIG%
|
||||
-- GENERATION: STANDARD
|
||||
-- VERSION: WM1.0
|
||||
-- MODULE: altpll_reconfig
|
||||
|
||||
-- ============================================================
|
||||
-- File Name: altpll_reconfig1.tdf
|
||||
-- Megafunction Name(s):
|
||||
-- altpll_reconfig
|
||||
--
|
||||
-- Simulation Library Files(s):
|
||||
-- altera_mf;cycloneiii;lpm
|
||||
-- ============================================================
|
||||
-- ************************************************************
|
||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
--
|
||||
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
|
||||
-- ************************************************************
|
||||
|
||||
|
||||
--Copyright (C) 1991-2010 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
-- Clearbox generated function header
|
||||
FUNCTION altpll_reconfig1_pllrcfg_t4q (clock, counter_param[2..0], counter_type[3..0], data_in[8..0], pll_areset_in, pll_scandataout, pll_scandone, read_param, reconfig, reset, write_param)
|
||||
RETURNS ( busy, data_out[8..0], pll_areset, pll_configupdate, pll_scanclk, pll_scanclkena, pll_scandata);
|
||||
|
||||
|
||||
|
||||
|
||||
SUBDESIGN altpll_reconfig1
|
||||
(
|
||||
clock : INPUT;
|
||||
counter_param[2..0] : INPUT;
|
||||
counter_type[3..0] : INPUT;
|
||||
data_in[8..0] : INPUT;
|
||||
pll_areset_in : INPUT = GND;
|
||||
pll_scandataout : INPUT;
|
||||
pll_scandone : INPUT;
|
||||
read_param : INPUT;
|
||||
reconfig : INPUT;
|
||||
reset : INPUT;
|
||||
write_param : INPUT;
|
||||
busy : OUTPUT;
|
||||
data_out[8..0] : OUTPUT;
|
||||
pll_areset : OUTPUT;
|
||||
pll_configupdate : OUTPUT;
|
||||
pll_scanclk : OUTPUT;
|
||||
pll_scanclkena : OUTPUT;
|
||||
pll_scandata : OUTPUT;
|
||||
)
|
||||
|
||||
VARIABLE
|
||||
|
||||
altpll_reconfig1_pllrcfg_t4q_component : altpll_reconfig1_pllrcfg_t4q;
|
||||
|
||||
BEGIN
|
||||
|
||||
pll_areset = altpll_reconfig1_pllrcfg_t4q_component.pll_areset;
|
||||
pll_scanclkena = altpll_reconfig1_pllrcfg_t4q_component.pll_scanclkena;
|
||||
pll_scanclk = altpll_reconfig1_pllrcfg_t4q_component.pll_scanclk;
|
||||
busy = altpll_reconfig1_pllrcfg_t4q_component.busy;
|
||||
data_out[8..0] = altpll_reconfig1_pllrcfg_t4q_component.data_out[8..0];
|
||||
pll_scandata = altpll_reconfig1_pllrcfg_t4q_component.pll_scandata;
|
||||
pll_configupdate = altpll_reconfig1_pllrcfg_t4q_component.pll_configupdate;
|
||||
altpll_reconfig1_pllrcfg_t4q_component.reconfig = reconfig;
|
||||
altpll_reconfig1_pllrcfg_t4q_component.counter_type[3..0] = counter_type[3..0];
|
||||
altpll_reconfig1_pllrcfg_t4q_component.pll_scandone = pll_scandone;
|
||||
altpll_reconfig1_pllrcfg_t4q_component.pll_scandataout = pll_scandataout;
|
||||
altpll_reconfig1_pllrcfg_t4q_component.pll_areset_in = pll_areset_in;
|
||||
altpll_reconfig1_pllrcfg_t4q_component.read_param = read_param;
|
||||
altpll_reconfig1_pllrcfg_t4q_component.reset = reset;
|
||||
altpll_reconfig1_pllrcfg_t4q_component.data_in[8..0] = data_in[8..0];
|
||||
altpll_reconfig1_pllrcfg_t4q_component.clock = clock;
|
||||
altpll_reconfig1_pllrcfg_t4q_component.counter_param[2..0] = counter_param[2..0];
|
||||
altpll_reconfig1_pllrcfg_t4q_component.write_param = write_param;
|
||||
END;
|
||||
|
||||
|
||||
|
||||
-- ============================================================
|
||||
-- CNX file retrieval info
|
||||
-- ============================================================
|
||||
-- Retrieval info: PRIVATE: CHAIN_TYPE NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: INIT_FILE_NAME STRING "./altpll4.mif"
|
||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_INIT_FILE STRING "0"
|
||||
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: USED_PORT: busy 0 0 0 0 OUTPUT NODEFVAL "busy"
|
||||
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
|
||||
-- Retrieval info: USED_PORT: counter_param 0 0 3 0 INPUT NODEFVAL "counter_param[2..0]"
|
||||
-- Retrieval info: USED_PORT: counter_type 0 0 4 0 INPUT NODEFVAL "counter_type[3..0]"
|
||||
-- Retrieval info: USED_PORT: data_in 0 0 9 0 INPUT NODEFVAL "data_in[8..0]"
|
||||
-- Retrieval info: USED_PORT: data_out 0 0 9 0 OUTPUT NODEFVAL "data_out[8..0]"
|
||||
-- Retrieval info: USED_PORT: pll_areset 0 0 0 0 OUTPUT NODEFVAL "pll_areset"
|
||||
-- Retrieval info: USED_PORT: pll_areset_in 0 0 0 0 INPUT GND "pll_areset_in"
|
||||
-- Retrieval info: USED_PORT: pll_configupdate 0 0 0 0 OUTPUT NODEFVAL "pll_configupdate"
|
||||
-- Retrieval info: USED_PORT: pll_scanclk 0 0 0 0 OUTPUT NODEFVAL "pll_scanclk"
|
||||
-- Retrieval info: USED_PORT: pll_scanclkena 0 0 0 0 OUTPUT NODEFVAL "pll_scanclkena"
|
||||
-- Retrieval info: USED_PORT: pll_scandata 0 0 0 0 OUTPUT NODEFVAL "pll_scandata"
|
||||
-- Retrieval info: USED_PORT: pll_scandataout 0 0 0 0 INPUT NODEFVAL "pll_scandataout"
|
||||
-- Retrieval info: USED_PORT: pll_scandone 0 0 0 0 INPUT NODEFVAL "pll_scandone"
|
||||
-- Retrieval info: USED_PORT: read_param 0 0 0 0 INPUT NODEFVAL "read_param"
|
||||
-- Retrieval info: USED_PORT: reconfig 0 0 0 0 INPUT NODEFVAL "reconfig"
|
||||
-- Retrieval info: USED_PORT: reset 0 0 0 0 INPUT NODEFVAL "reset"
|
||||
-- Retrieval info: USED_PORT: write_param 0 0 0 0 INPUT NODEFVAL "write_param"
|
||||
-- Retrieval info: CONNECT: @data_in 0 0 9 0 data_in 0 0 9 0
|
||||
-- Retrieval info: CONNECT: @reset 0 0 0 0 reset 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @pll_scandone 0 0 0 0 pll_scandone 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @read_param 0 0 0 0 read_param 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @counter_type 0 0 4 0 counter_type 0 0 4 0
|
||||
-- Retrieval info: CONNECT: @pll_areset_in 0 0 0 0 pll_areset_in 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @pll_scandataout 0 0 0 0 pll_scandataout 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @write_param 0 0 0 0 write_param 0 0 0 0
|
||||
-- Retrieval info: CONNECT: pll_areset 0 0 0 0 @pll_areset 0 0 0 0
|
||||
-- Retrieval info: CONNECT: pll_configupdate 0 0 0 0 @pll_configupdate 0 0 0 0
|
||||
-- Retrieval info: CONNECT: data_out 0 0 9 0 @data_out 0 0 9 0
|
||||
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
|
||||
-- Retrieval info: CONNECT: pll_scanclkena 0 0 0 0 @pll_scanclkena 0 0 0 0
|
||||
-- Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @counter_param 0 0 3 0 counter_param 0 0 3 0
|
||||
-- Retrieval info: CONNECT: @reconfig 0 0 0 0 reconfig 0 0 0 0
|
||||
-- Retrieval info: CONNECT: pll_scandata 0 0 0 0 @pll_scandata 0 0 0 0
|
||||
-- Retrieval info: CONNECT: pll_scanclk 0 0 0 0 @pll_scanclk 0 0 0 0
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll_reconfig1.tdf TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll_reconfig1.inc TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll_reconfig1.cmp TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll_reconfig1.bsf TRUE FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll_reconfig1_inst.tdf FALSE
|
||||
-- Retrieval info: LIB_FILE: altera_mf
|
||||
-- Retrieval info: LIB_FILE: cycloneiii
|
||||
-- Retrieval info: LIB_FILE: lpm
|
||||
583
FPGA_quartus_GE/altip_orig/altpll_reconfig1_pllrcfg_bju.tdf
Normal file
583
FPGA_quartus_GE/altip_orig/altpll_reconfig1_pllrcfg_bju.tdf
Normal file
File diff suppressed because one or more lines are too long
582
FPGA_quartus_GE/altip_orig/altpll_reconfig1_pllrcfg_t4q.tdf
Normal file
582
FPGA_quartus_GE/altip_orig/altpll_reconfig1_pllrcfg_t4q.tdf
Normal file
File diff suppressed because one or more lines are too long
95
FPGA_quartus_GE/altip_orig/dcfifo0.bsf
Normal file
95
FPGA_quartus_GE/altip_orig/dcfifo0.bsf
Normal file
@@ -0,0 +1,95 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2009 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 0 0 160 168)
|
||||
(text "dcfifo0" (rect 62 1 105 17)(font "Arial" (font_size 10)))
|
||||
(text "inst" (rect 8 152 25 164)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "data[7..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
|
||||
(text "data[7..0]" (rect 20 26 65 39)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 32)(pt 16 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 56)
|
||||
(input)
|
||||
(text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8)))
|
||||
(text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 56)(pt 16 56)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 72)
|
||||
(input)
|
||||
(text "wrclk" (rect 0 0 31 14)(font "Arial" (font_size 8)))
|
||||
(text "wrclk" (rect 26 66 48 79)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 72)(pt 16 72)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 104)
|
||||
(input)
|
||||
(text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8)))
|
||||
(text "rdreq" (rect 20 98 44 111)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 104)(pt 16 104)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 120)
|
||||
(input)
|
||||
(text "rdclk" (rect 0 0 27 14)(font "Arial" (font_size 8)))
|
||||
(text "rdclk" (rect 26 114 47 127)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 120)(pt 16 120)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 144)
|
||||
(input)
|
||||
(text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8)))
|
||||
(text "aclr" (rect 20 138 37 151)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 144)(pt 16 144)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 160 72)
|
||||
(output)
|
||||
(text "wrusedw[9..0]" (rect 0 0 84 14)(font "Arial" (font_size 8)))
|
||||
(text "wrusedw[9..0]" (rect 69 66 132 79)(font "Arial" (font_size 8)))
|
||||
(line (pt 160 72)(pt 144 72)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 160 96)
|
||||
(output)
|
||||
(text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
|
||||
(text "q[31..0]" (rect 105 90 141 103)(font "Arial" (font_size 8)))
|
||||
(line (pt 160 96)(pt 144 96)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(text "8 bits x 1024 words" (rect 63 140 144 152)(font "Arial" ))
|
||||
(line (pt 16 16)(pt 144 16)(line_width 1))
|
||||
(line (pt 144 16)(pt 144 152)(line_width 1))
|
||||
(line (pt 144 152)(pt 16 152)(line_width 1))
|
||||
(line (pt 16 152)(pt 16 16)(line_width 1))
|
||||
(line (pt 16 84)(pt 144 84)(line_width 1))
|
||||
(line (pt 16 132)(pt 144 132)(line_width 1))
|
||||
(line (pt 16 66)(pt 22 72)(line_width 1))
|
||||
(line (pt 22 72)(pt 16 78)(line_width 1))
|
||||
(line (pt 16 114)(pt 22 120)(line_width 1))
|
||||
(line (pt 22 120)(pt 16 126)(line_width 1))
|
||||
)
|
||||
)
|
||||
28
FPGA_quartus_GE/altip_orig/dcfifo0.cmp
Normal file
28
FPGA_quartus_GE/altip_orig/dcfifo0.cmp
Normal file
@@ -0,0 +1,28 @@
|
||||
--Copyright (C) 1991-2009 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
component dcfifo0
|
||||
PORT
|
||||
(
|
||||
aclr : IN STD_LOGIC := '0';
|
||||
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
|
||||
rdclk : IN STD_LOGIC ;
|
||||
rdreq : IN STD_LOGIC ;
|
||||
wrclk : IN STD_LOGIC ;
|
||||
wrreq : IN STD_LOGIC ;
|
||||
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
|
||||
wrusedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
|
||||
);
|
||||
end component;
|
||||
5
FPGA_quartus_GE/altip_orig/dcfifo0.qip
Normal file
5
FPGA_quartus_GE/altip_orig/dcfifo0.qip
Normal file
@@ -0,0 +1,5 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "LPM_FIFO+"
|
||||
set_global_assignment -name IP_TOOL_VERSION "9.1"
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "dcfifo0.vhd"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dcfifo0.bsf"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dcfifo0.cmp"]
|
||||
202
FPGA_quartus_GE/altip_orig/dcfifo0.vhd
Normal file
202
FPGA_quartus_GE/altip_orig/dcfifo0.vhd
Normal file
@@ -0,0 +1,202 @@
|
||||
-- megafunction wizard: %LPM_FIFO+%
|
||||
-- GENERATION: STANDARD
|
||||
-- VERSION: WM1.0
|
||||
-- MODULE: dcfifo_mixed_widths
|
||||
|
||||
-- ============================================================
|
||||
-- File Name: dcfifo0.vhd
|
||||
-- Megafunction Name(s):
|
||||
-- dcfifo_mixed_widths
|
||||
--
|
||||
-- Simulation Library Files(s):
|
||||
-- altera_mf
|
||||
-- ============================================================
|
||||
-- ************************************************************
|
||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
--
|
||||
-- 9.1 Build 222 10/21/2009 SJ Web Edition
|
||||
-- ************************************************************
|
||||
|
||||
|
||||
--Copyright (C) 1991-2009 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
|
||||
LIBRARY altera_mf;
|
||||
USE altera_mf.all;
|
||||
|
||||
ENTITY dcfifo0 IS
|
||||
PORT
|
||||
(
|
||||
aclr : IN STD_LOGIC := '0';
|
||||
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
|
||||
rdclk : IN STD_LOGIC ;
|
||||
rdreq : IN STD_LOGIC ;
|
||||
wrclk : IN STD_LOGIC ;
|
||||
wrreq : IN STD_LOGIC ;
|
||||
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
|
||||
wrusedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
|
||||
);
|
||||
END dcfifo0;
|
||||
|
||||
|
||||
ARCHITECTURE SYN OF dcfifo0 IS
|
||||
|
||||
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (9 DOWNTO 0);
|
||||
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
|
||||
|
||||
|
||||
|
||||
COMPONENT dcfifo_mixed_widths
|
||||
GENERIC (
|
||||
intended_device_family : STRING;
|
||||
lpm_numwords : NATURAL;
|
||||
lpm_showahead : STRING;
|
||||
lpm_type : STRING;
|
||||
lpm_width : NATURAL;
|
||||
lpm_widthu : NATURAL;
|
||||
lpm_widthu_r : NATURAL;
|
||||
lpm_width_r : NATURAL;
|
||||
overflow_checking : STRING;
|
||||
rdsync_delaypipe : NATURAL;
|
||||
underflow_checking : STRING;
|
||||
use_eab : STRING;
|
||||
write_aclr_synch : STRING;
|
||||
wrsync_delaypipe : NATURAL
|
||||
);
|
||||
PORT (
|
||||
wrclk : IN STD_LOGIC ;
|
||||
rdreq : IN STD_LOGIC ;
|
||||
wrusedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
|
||||
aclr : IN STD_LOGIC ;
|
||||
rdclk : IN STD_LOGIC ;
|
||||
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
|
||||
wrreq : IN STD_LOGIC ;
|
||||
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
BEGIN
|
||||
wrusedw <= sub_wire0(9 DOWNTO 0);
|
||||
q <= sub_wire1(31 DOWNTO 0);
|
||||
|
||||
dcfifo_mixed_widths_component : dcfifo_mixed_widths
|
||||
GENERIC MAP (
|
||||
intended_device_family => "Cyclone III",
|
||||
lpm_numwords => 1024,
|
||||
lpm_showahead => "OFF",
|
||||
lpm_type => "dcfifo",
|
||||
lpm_width => 8,
|
||||
lpm_widthu => 10,
|
||||
lpm_widthu_r => 8,
|
||||
lpm_width_r => 32,
|
||||
overflow_checking => "ON",
|
||||
rdsync_delaypipe => 5,
|
||||
underflow_checking => "ON",
|
||||
use_eab => "ON",
|
||||
write_aclr_synch => "OFF",
|
||||
wrsync_delaypipe => 5
|
||||
)
|
||||
PORT MAP (
|
||||
wrclk => wrclk,
|
||||
rdreq => rdreq,
|
||||
aclr => aclr,
|
||||
rdclk => rdclk,
|
||||
wrreq => wrreq,
|
||||
data => data,
|
||||
wrusedw => sub_wire0,
|
||||
q => sub_wire1
|
||||
);
|
||||
|
||||
|
||||
|
||||
END SYN;
|
||||
|
||||
-- ============================================================
|
||||
-- CNX file retrieval info
|
||||
-- ============================================================
|
||||
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
|
||||
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
|
||||
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: Clock NUMERIC "4"
|
||||
-- Retrieval info: PRIVATE: Depth NUMERIC "1024"
|
||||
-- Retrieval info: PRIVATE: Empty NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: Full NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: Optimize NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: Width NUMERIC "8"
|
||||
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: diff_widths NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: output_width NUMERIC "32"
|
||||
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: wsFull NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
|
||||
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
|
||||
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
|
||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
|
||||
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
|
||||
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
|
||||
-- Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "8"
|
||||
-- Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "32"
|
||||
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
|
||||
-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
|
||||
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
|
||||
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
|
||||
-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
|
||||
-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
|
||||
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
|
||||
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
|
||||
-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
|
||||
-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
|
||||
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
|
||||
-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
|
||||
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
|
||||
-- Retrieval info: USED_PORT: wrusedw 0 0 10 0 OUTPUT NODEFVAL wrusedw[9..0]
|
||||
-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
|
||||
-- Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
|
||||
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
|
||||
-- Retrieval info: CONNECT: wrusedw 0 0 10 0 @wrusedw 0 0 10 0
|
||||
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
|
||||
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.vhd TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.inc FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.cmp TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.bsf TRUE FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0_inst.vhd FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0_waveforms.html FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0_wave*.jpg FALSE
|
||||
-- Retrieval info: LIB_FILE: altera_mf
|
||||
95
FPGA_quartus_GE/altip_orig/dcfifo1.bsf
Normal file
95
FPGA_quartus_GE/altip_orig/dcfifo1.bsf
Normal file
@@ -0,0 +1,95 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2009 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 0 0 160 168)
|
||||
(text "dcfifo1" (rect 62 1 105 17)(font "Arial" (font_size 10)))
|
||||
(text "inst" (rect 8 152 25 164)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
|
||||
(text "data[31..0]" (rect 20 26 71 39)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 32)(pt 16 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 56)
|
||||
(input)
|
||||
(text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8)))
|
||||
(text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 56)(pt 16 56)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 72)
|
||||
(input)
|
||||
(text "wrclk" (rect 0 0 31 14)(font "Arial" (font_size 8)))
|
||||
(text "wrclk" (rect 26 66 48 79)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 72)(pt 16 72)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 104)
|
||||
(input)
|
||||
(text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8)))
|
||||
(text "rdreq" (rect 20 98 44 111)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 104)(pt 16 104)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 120)
|
||||
(input)
|
||||
(text "rdclk" (rect 0 0 27 14)(font "Arial" (font_size 8)))
|
||||
(text "rdclk" (rect 26 114 47 127)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 120)(pt 16 120)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 144)
|
||||
(input)
|
||||
(text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8)))
|
||||
(text "aclr" (rect 20 138 37 151)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 144)(pt 16 144)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 160 96)
|
||||
(output)
|
||||
(text "q[7..0]" (rect 0 0 35 14)(font "Arial" (font_size 8)))
|
||||
(text "q[7..0]" (rect 111 90 141 103)(font "Arial" (font_size 8)))
|
||||
(line (pt 160 96)(pt 144 96)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 160 120)
|
||||
(output)
|
||||
(text "rdusedw[9..0]" (rect 0 0 80 14)(font "Arial" (font_size 8)))
|
||||
(text "rdusedw[9..0]" (rect 73 114 135 127)(font "Arial" (font_size 8)))
|
||||
(line (pt 160 120)(pt 144 120)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(text "32 bits x 256 words" (rect 63 140 144 152)(font "Arial" ))
|
||||
(line (pt 16 16)(pt 144 16)(line_width 1))
|
||||
(line (pt 144 16)(pt 144 152)(line_width 1))
|
||||
(line (pt 144 152)(pt 16 152)(line_width 1))
|
||||
(line (pt 16 152)(pt 16 16)(line_width 1))
|
||||
(line (pt 16 84)(pt 144 84)(line_width 1))
|
||||
(line (pt 16 132)(pt 144 132)(line_width 1))
|
||||
(line (pt 16 66)(pt 22 72)(line_width 1))
|
||||
(line (pt 22 72)(pt 16 78)(line_width 1))
|
||||
(line (pt 16 114)(pt 22 120)(line_width 1))
|
||||
(line (pt 22 120)(pt 16 126)(line_width 1))
|
||||
)
|
||||
)
|
||||
28
FPGA_quartus_GE/altip_orig/dcfifo1.cmp
Normal file
28
FPGA_quartus_GE/altip_orig/dcfifo1.cmp
Normal file
@@ -0,0 +1,28 @@
|
||||
--Copyright (C) 1991-2009 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
component dcfifo1
|
||||
PORT
|
||||
(
|
||||
aclr : IN STD_LOGIC := '0';
|
||||
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
|
||||
rdclk : IN STD_LOGIC ;
|
||||
rdreq : IN STD_LOGIC ;
|
||||
wrclk : IN STD_LOGIC ;
|
||||
wrreq : IN STD_LOGIC ;
|
||||
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
|
||||
rdusedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
|
||||
);
|
||||
end component;
|
||||
5
FPGA_quartus_GE/altip_orig/dcfifo1.qip
Normal file
5
FPGA_quartus_GE/altip_orig/dcfifo1.qip
Normal file
@@ -0,0 +1,5 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "LPM_FIFO+"
|
||||
set_global_assignment -name IP_TOOL_VERSION "9.1"
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "dcfifo1.vhd"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dcfifo1.bsf"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dcfifo1.cmp"]
|
||||
202
FPGA_quartus_GE/altip_orig/dcfifo1.vhd
Normal file
202
FPGA_quartus_GE/altip_orig/dcfifo1.vhd
Normal file
@@ -0,0 +1,202 @@
|
||||
-- megafunction wizard: %LPM_FIFO+%
|
||||
-- GENERATION: STANDARD
|
||||
-- VERSION: WM1.0
|
||||
-- MODULE: dcfifo_mixed_widths
|
||||
|
||||
-- ============================================================
|
||||
-- File Name: dcfifo1.vhd
|
||||
-- Megafunction Name(s):
|
||||
-- dcfifo_mixed_widths
|
||||
--
|
||||
-- Simulation Library Files(s):
|
||||
-- altera_mf
|
||||
-- ============================================================
|
||||
-- ************************************************************
|
||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
--
|
||||
-- 9.1 Build 222 10/21/2009 SJ Web Edition
|
||||
-- ************************************************************
|
||||
|
||||
|
||||
--Copyright (C) 1991-2009 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
|
||||
LIBRARY altera_mf;
|
||||
USE altera_mf.all;
|
||||
|
||||
ENTITY dcfifo1 IS
|
||||
PORT
|
||||
(
|
||||
aclr : IN STD_LOGIC := '0';
|
||||
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
|
||||
rdclk : IN STD_LOGIC ;
|
||||
rdreq : IN STD_LOGIC ;
|
||||
wrclk : IN STD_LOGIC ;
|
||||
wrreq : IN STD_LOGIC ;
|
||||
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
|
||||
rdusedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
|
||||
);
|
||||
END dcfifo1;
|
||||
|
||||
|
||||
ARCHITECTURE SYN OF dcfifo1 IS
|
||||
|
||||
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
|
||||
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (9 DOWNTO 0);
|
||||
|
||||
|
||||
|
||||
COMPONENT dcfifo_mixed_widths
|
||||
GENERIC (
|
||||
intended_device_family : STRING;
|
||||
lpm_numwords : NATURAL;
|
||||
lpm_showahead : STRING;
|
||||
lpm_type : STRING;
|
||||
lpm_width : NATURAL;
|
||||
lpm_widthu : NATURAL;
|
||||
lpm_widthu_r : NATURAL;
|
||||
lpm_width_r : NATURAL;
|
||||
overflow_checking : STRING;
|
||||
rdsync_delaypipe : NATURAL;
|
||||
underflow_checking : STRING;
|
||||
use_eab : STRING;
|
||||
write_aclr_synch : STRING;
|
||||
wrsync_delaypipe : NATURAL
|
||||
);
|
||||
PORT (
|
||||
wrclk : IN STD_LOGIC ;
|
||||
rdreq : IN STD_LOGIC ;
|
||||
aclr : IN STD_LOGIC ;
|
||||
rdclk : IN STD_LOGIC ;
|
||||
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
|
||||
wrreq : IN STD_LOGIC ;
|
||||
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
|
||||
rdusedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
BEGIN
|
||||
q <= sub_wire0(7 DOWNTO 0);
|
||||
rdusedw <= sub_wire1(9 DOWNTO 0);
|
||||
|
||||
dcfifo_mixed_widths_component : dcfifo_mixed_widths
|
||||
GENERIC MAP (
|
||||
intended_device_family => "Cyclone III",
|
||||
lpm_numwords => 256,
|
||||
lpm_showahead => "OFF",
|
||||
lpm_type => "dcfifo",
|
||||
lpm_width => 32,
|
||||
lpm_widthu => 8,
|
||||
lpm_widthu_r => 10,
|
||||
lpm_width_r => 8,
|
||||
overflow_checking => "ON",
|
||||
rdsync_delaypipe => 5,
|
||||
underflow_checking => "ON",
|
||||
use_eab => "ON",
|
||||
write_aclr_synch => "OFF",
|
||||
wrsync_delaypipe => 5
|
||||
)
|
||||
PORT MAP (
|
||||
wrclk => wrclk,
|
||||
rdreq => rdreq,
|
||||
aclr => aclr,
|
||||
rdclk => rdclk,
|
||||
wrreq => wrreq,
|
||||
data => data,
|
||||
q => sub_wire0,
|
||||
rdusedw => sub_wire1
|
||||
);
|
||||
|
||||
|
||||
|
||||
END SYN;
|
||||
|
||||
-- ============================================================
|
||||
-- CNX file retrieval info
|
||||
-- ============================================================
|
||||
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
|
||||
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
|
||||
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: Clock NUMERIC "4"
|
||||
-- Retrieval info: PRIVATE: Depth NUMERIC "256"
|
||||
-- Retrieval info: PRIVATE: Empty NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: Full NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: Optimize NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: Width NUMERIC "32"
|
||||
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: diff_widths NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: output_width NUMERIC "8"
|
||||
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: wsFull NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
|
||||
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
|
||||
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
|
||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
|
||||
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
|
||||
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
|
||||
-- Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "10"
|
||||
-- Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "8"
|
||||
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
|
||||
-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
|
||||
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
|
||||
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
|
||||
-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
|
||||
-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
|
||||
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
|
||||
-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
|
||||
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
|
||||
-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
|
||||
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
|
||||
-- Retrieval info: USED_PORT: rdusedw 0 0 10 0 OUTPUT NODEFVAL rdusedw[9..0]
|
||||
-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
|
||||
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
|
||||
-- Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
|
||||
-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
|
||||
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
|
||||
-- Retrieval info: CONNECT: rdusedw 0 0 10 0 @rdusedw 0 0 10 0
|
||||
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
|
||||
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.vhd TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.inc FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.cmp TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.bsf TRUE FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_inst.vhd FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_waveforms.html FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_wave*.jpg FALSE
|
||||
-- Retrieval info: LIB_FILE: altera_mf
|
||||
56
FPGA_quartus_GE/altip_orig/lpm_bustri0.bsf
Normal file
56
FPGA_quartus_GE/altip_orig/lpm_bustri0.bsf
Normal file
@@ -0,0 +1,56 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2008 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 0 0 80 40)
|
||||
(text "lpm_bustri0" (rect 7 1 86 17)(font "Arial" (font_size 10)))
|
||||
(text "inst" (rect 8 24 25 36)(font "Arial" ))
|
||||
(port
|
||||
(pt 40 40)
|
||||
(input)
|
||||
(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
|
||||
(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
|
||||
(line (pt 40 40)(pt 40 28)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 24)
|
||||
(input)
|
||||
(text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
|
||||
(text "data[31..0]" (rect -3 -27 10 24)(font "Arial" (font_size 8))(invisible))
|
||||
(line (pt 0 24)(pt 32 24)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 80 24)
|
||||
(bidir)
|
||||
(text "tridata[31..0]" (rect 0 0 70 14)(font "Arial" (font_size 8)))
|
||||
(text "tridata[31..0]" (rect 84 -36 97 24)(font "Arial" (font_size 8))(invisible))
|
||||
(line (pt 80 24)(pt 48 24)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(text "32" (rect 61 25 71 37)(font "Arial" ))
|
||||
(text "32" (rect 13 25 23 37)(font "Arial" ))
|
||||
(line (pt 32 16)(pt 48 24)(line_width 1))
|
||||
(line (pt 48 24)(pt 32 32)(line_width 1))
|
||||
(line (pt 32 32)(pt 32 16)(line_width 1))
|
||||
(line (pt 56 28)(pt 64 20)(line_width 1))
|
||||
(line (pt 8 28)(pt 16 20)(line_width 1))
|
||||
)
|
||||
)
|
||||
24
FPGA_quartus_GE/altip_orig/lpm_bustri0.inc
Normal file
24
FPGA_quartus_GE/altip_orig/lpm_bustri0.inc
Normal file
@@ -0,0 +1,24 @@
|
||||
--Copyright (C) 1991-2008 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
FUNCTION lpm_bustri0
|
||||
(
|
||||
data[31..0],
|
||||
enabledt
|
||||
)
|
||||
|
||||
RETURNS (
|
||||
tridata[31..0]
|
||||
);
|
||||
6
FPGA_quartus_GE/altip_orig/lpm_bustri0.qip
Normal file
6
FPGA_quartus_GE/altip_orig/lpm_bustri0.qip
Normal file
@@ -0,0 +1,6 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI"
|
||||
set_global_assignment -name IP_TOOL_VERSION "8.1"
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri0.vhd"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri0.bsf"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri0.inc"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri0.cmp"]
|
||||
107
FPGA_quartus_GE/altip_orig/lpm_bustri0.vhd
Normal file
107
FPGA_quartus_GE/altip_orig/lpm_bustri0.vhd
Normal file
@@ -0,0 +1,107 @@
|
||||
-- megafunction wizard: %LPM_BUSTRI%
|
||||
-- GENERATION: STANDARD
|
||||
-- VERSION: WM1.0
|
||||
-- MODULE: lpm_bustri
|
||||
|
||||
-- ============================================================
|
||||
-- File Name: lpm_bustri0.vhd
|
||||
-- Megafunction Name(s):
|
||||
-- lpm_bustri
|
||||
--
|
||||
-- Simulation Library Files(s):
|
||||
-- lpm
|
||||
-- ============================================================
|
||||
-- ************************************************************
|
||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
--
|
||||
-- 8.1 Build 163 10/28/2008 SJ Web Edition
|
||||
-- ************************************************************
|
||||
|
||||
|
||||
--Copyright (C) 1991-2008 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
|
||||
LIBRARY lpm;
|
||||
USE lpm.all;
|
||||
|
||||
ENTITY lpm_bustri0 IS
|
||||
PORT
|
||||
(
|
||||
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
|
||||
enabledt : IN STD_LOGIC ;
|
||||
tridata : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0)
|
||||
);
|
||||
END lpm_bustri0;
|
||||
|
||||
|
||||
ARCHITECTURE SYN OF lpm_bustri0 IS
|
||||
|
||||
|
||||
|
||||
|
||||
COMPONENT lpm_bustri
|
||||
GENERIC (
|
||||
lpm_type : STRING;
|
||||
lpm_width : NATURAL
|
||||
);
|
||||
PORT (
|
||||
enabledt : IN STD_LOGIC ;
|
||||
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
|
||||
tridata : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
BEGIN
|
||||
|
||||
lpm_bustri_component : lpm_bustri
|
||||
GENERIC MAP (
|
||||
lpm_type => "LPM_BUSTRI",
|
||||
lpm_width => 32
|
||||
)
|
||||
PORT MAP (
|
||||
enabledt => enabledt,
|
||||
data => data,
|
||||
tridata => tridata
|
||||
);
|
||||
|
||||
|
||||
|
||||
END SYN;
|
||||
|
||||
-- ============================================================
|
||||
-- CNX file retrieval info
|
||||
-- ============================================================
|
||||
-- Retrieval info: PRIVATE: BiDir NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
-- Retrieval info: PRIVATE: nBit NUMERIC "32"
|
||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
|
||||
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
|
||||
-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
|
||||
-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
|
||||
-- Retrieval info: USED_PORT: tridata 0 0 32 0 BIDIR NODEFVAL tridata[31..0]
|
||||
-- Retrieval info: CONNECT: tridata 0 0 32 0 @tridata 0 0 32 0
|
||||
-- Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
|
||||
-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
|
||||
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri0.vhd TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri0.inc TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri0.cmp TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri0.bsf TRUE FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri0_inst.vhd FALSE
|
||||
-- Retrieval info: LIB_FILE: lpm
|
||||
56
FPGA_quartus_GE/altip_orig/lpm_bustri1.bsf
Normal file
56
FPGA_quartus_GE/altip_orig/lpm_bustri1.bsf
Normal file
@@ -0,0 +1,56 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2008 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 0 0 80 40)
|
||||
(text "lpm_bustri1" (rect 7 1 86 17)(font "Arial" (font_size 10)))
|
||||
(text "inst" (rect 8 24 25 36)(font "Arial" ))
|
||||
(port
|
||||
(pt 40 40)
|
||||
(input)
|
||||
(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
|
||||
(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
|
||||
(line (pt 40 40)(pt 40 28)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 24)
|
||||
(input)
|
||||
(text "data[2..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
|
||||
(text "data[2..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible))
|
||||
(line (pt 0 24)(pt 32 24)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 80 24)
|
||||
(bidir)
|
||||
(text "tridata[2..0]" (rect 0 0 63 14)(font "Arial" (font_size 8)))
|
||||
(text "tridata[2..0]" (rect 84 -30 97 24)(font "Arial" (font_size 8))(invisible))
|
||||
(line (pt 80 24)(pt 48 24)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(text "3" (rect 63 25 68 37)(font "Arial" ))
|
||||
(text "3" (rect 15 25 20 37)(font "Arial" ))
|
||||
(line (pt 32 16)(pt 48 24)(line_width 1))
|
||||
(line (pt 48 24)(pt 32 32)(line_width 1))
|
||||
(line (pt 32 32)(pt 32 16)(line_width 1))
|
||||
(line (pt 58 28)(pt 66 20)(line_width 1))
|
||||
(line (pt 10 28)(pt 18 20)(line_width 1))
|
||||
)
|
||||
)
|
||||
5
FPGA_quartus_GE/altip_orig/lpm_bustri1.qip
Normal file
5
FPGA_quartus_GE/altip_orig/lpm_bustri1.qip
Normal file
@@ -0,0 +1,5 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI"
|
||||
set_global_assignment -name IP_TOOL_VERSION "8.1"
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri1.vhd"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri1.bsf"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri1.cmp"]
|
||||
107
FPGA_quartus_GE/altip_orig/lpm_bustri1.vhd
Normal file
107
FPGA_quartus_GE/altip_orig/lpm_bustri1.vhd
Normal file
@@ -0,0 +1,107 @@
|
||||
-- megafunction wizard: %LPM_BUSTRI%
|
||||
-- GENERATION: STANDARD
|
||||
-- VERSION: WM1.0
|
||||
-- MODULE: lpm_bustri
|
||||
|
||||
-- ============================================================
|
||||
-- File Name: lpm_bustri1.vhd
|
||||
-- Megafunction Name(s):
|
||||
-- lpm_bustri
|
||||
--
|
||||
-- Simulation Library Files(s):
|
||||
-- lpm
|
||||
-- ============================================================
|
||||
-- ************************************************************
|
||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
--
|
||||
-- 8.1 Build 163 10/28/2008 SJ Web Edition
|
||||
-- ************************************************************
|
||||
|
||||
|
||||
--Copyright (C) 1991-2008 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
|
||||
LIBRARY lpm;
|
||||
USE lpm.all;
|
||||
|
||||
ENTITY lpm_bustri1 IS
|
||||
PORT
|
||||
(
|
||||
data : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
|
||||
enabledt : IN STD_LOGIC ;
|
||||
tridata : INOUT STD_LOGIC_VECTOR (2 DOWNTO 0)
|
||||
);
|
||||
END lpm_bustri1;
|
||||
|
||||
|
||||
ARCHITECTURE SYN OF lpm_bustri1 IS
|
||||
|
||||
|
||||
|
||||
|
||||
COMPONENT lpm_bustri
|
||||
GENERIC (
|
||||
lpm_type : STRING;
|
||||
lpm_width : NATURAL
|
||||
);
|
||||
PORT (
|
||||
enabledt : IN STD_LOGIC ;
|
||||
data : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
|
||||
tridata : INOUT STD_LOGIC_VECTOR (2 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
BEGIN
|
||||
|
||||
lpm_bustri_component : lpm_bustri
|
||||
GENERIC MAP (
|
||||
lpm_type => "LPM_BUSTRI",
|
||||
lpm_width => 3
|
||||
)
|
||||
PORT MAP (
|
||||
enabledt => enabledt,
|
||||
data => data,
|
||||
tridata => tridata
|
||||
);
|
||||
|
||||
|
||||
|
||||
END SYN;
|
||||
|
||||
-- ============================================================
|
||||
-- CNX file retrieval info
|
||||
-- ============================================================
|
||||
-- Retrieval info: PRIVATE: BiDir NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
-- Retrieval info: PRIVATE: nBit NUMERIC "3"
|
||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
|
||||
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "3"
|
||||
-- Retrieval info: USED_PORT: data 0 0 3 0 INPUT NODEFVAL data[2..0]
|
||||
-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
|
||||
-- Retrieval info: USED_PORT: tridata 0 0 3 0 BIDIR NODEFVAL tridata[2..0]
|
||||
-- Retrieval info: CONNECT: tridata 0 0 3 0 @tridata 0 0 3 0
|
||||
-- Retrieval info: CONNECT: @data 0 0 3 0 data 0 0 3 0
|
||||
-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
|
||||
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri1.vhd TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri1.inc FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri1.cmp TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri1.bsf TRUE FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri1_inst.vhd FALSE
|
||||
-- Retrieval info: LIB_FILE: lpm
|
||||
56
FPGA_quartus_GE/altip_orig/lpm_bustri2.bsf
Normal file
56
FPGA_quartus_GE/altip_orig/lpm_bustri2.bsf
Normal file
@@ -0,0 +1,56 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2008 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 0 0 80 40)
|
||||
(text "lpm_bustri2" (rect 7 1 86 17)(font "Arial" (font_size 10)))
|
||||
(text "inst" (rect 8 24 25 36)(font "Arial" ))
|
||||
(port
|
||||
(pt 40 40)
|
||||
(input)
|
||||
(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
|
||||
(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
|
||||
(line (pt 40 40)(pt 40 28)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 24)
|
||||
(input)
|
||||
(text "data[17..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
|
||||
(text "data[17..0]" (rect -3 -27 10 24)(font "Arial" (font_size 8))(invisible))
|
||||
(line (pt 0 24)(pt 32 24)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 80 24)
|
||||
(bidir)
|
||||
(text "tridata[17..0]" (rect 0 0 70 14)(font "Arial" (font_size 8)))
|
||||
(text "tridata[17..0]" (rect 84 -36 97 24)(font "Arial" (font_size 8))(invisible))
|
||||
(line (pt 80 24)(pt 48 24)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(text "18" (rect 61 25 71 37)(font "Arial" ))
|
||||
(text "18" (rect 13 25 23 37)(font "Arial" ))
|
||||
(line (pt 32 16)(pt 48 24)(line_width 1))
|
||||
(line (pt 48 24)(pt 32 32)(line_width 1))
|
||||
(line (pt 32 32)(pt 32 16)(line_width 1))
|
||||
(line (pt 56 28)(pt 64 20)(line_width 1))
|
||||
(line (pt 8 28)(pt 16 20)(line_width 1))
|
||||
)
|
||||
)
|
||||
5
FPGA_quartus_GE/altip_orig/lpm_bustri2.qip
Normal file
5
FPGA_quartus_GE/altip_orig/lpm_bustri2.qip
Normal file
@@ -0,0 +1,5 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI"
|
||||
set_global_assignment -name IP_TOOL_VERSION "8.1"
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri2.vhd"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri2.bsf"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri2.cmp"]
|
||||
107
FPGA_quartus_GE/altip_orig/lpm_bustri2.vhd
Normal file
107
FPGA_quartus_GE/altip_orig/lpm_bustri2.vhd
Normal file
@@ -0,0 +1,107 @@
|
||||
-- megafunction wizard: %LPM_BUSTRI%
|
||||
-- GENERATION: STANDARD
|
||||
-- VERSION: WM1.0
|
||||
-- MODULE: lpm_bustri
|
||||
|
||||
-- ============================================================
|
||||
-- File Name: lpm_bustri2.vhd
|
||||
-- Megafunction Name(s):
|
||||
-- lpm_bustri
|
||||
--
|
||||
-- Simulation Library Files(s):
|
||||
-- lpm
|
||||
-- ============================================================
|
||||
-- ************************************************************
|
||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
--
|
||||
-- 8.1 Build 163 10/28/2008 SJ Web Edition
|
||||
-- ************************************************************
|
||||
|
||||
|
||||
--Copyright (C) 1991-2008 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
|
||||
LIBRARY lpm;
|
||||
USE lpm.all;
|
||||
|
||||
ENTITY lpm_bustri2 IS
|
||||
PORT
|
||||
(
|
||||
data : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
|
||||
enabledt : IN STD_LOGIC ;
|
||||
tridata : INOUT STD_LOGIC_VECTOR (17 DOWNTO 0)
|
||||
);
|
||||
END lpm_bustri2;
|
||||
|
||||
|
||||
ARCHITECTURE SYN OF lpm_bustri2 IS
|
||||
|
||||
|
||||
|
||||
|
||||
COMPONENT lpm_bustri
|
||||
GENERIC (
|
||||
lpm_type : STRING;
|
||||
lpm_width : NATURAL
|
||||
);
|
||||
PORT (
|
||||
enabledt : IN STD_LOGIC ;
|
||||
data : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
|
||||
tridata : INOUT STD_LOGIC_VECTOR (17 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
BEGIN
|
||||
|
||||
lpm_bustri_component : lpm_bustri
|
||||
GENERIC MAP (
|
||||
lpm_type => "LPM_BUSTRI",
|
||||
lpm_width => 18
|
||||
)
|
||||
PORT MAP (
|
||||
enabledt => enabledt,
|
||||
data => data,
|
||||
tridata => tridata
|
||||
);
|
||||
|
||||
|
||||
|
||||
END SYN;
|
||||
|
||||
-- ============================================================
|
||||
-- CNX file retrieval info
|
||||
-- ============================================================
|
||||
-- Retrieval info: PRIVATE: BiDir NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
-- Retrieval info: PRIVATE: nBit NUMERIC "18"
|
||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
|
||||
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "18"
|
||||
-- Retrieval info: USED_PORT: data 0 0 18 0 INPUT NODEFVAL data[17..0]
|
||||
-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
|
||||
-- Retrieval info: USED_PORT: tridata 0 0 18 0 BIDIR NODEFVAL tridata[17..0]
|
||||
-- Retrieval info: CONNECT: tridata 0 0 18 0 @tridata 0 0 18 0
|
||||
-- Retrieval info: CONNECT: @data 0 0 18 0 data 0 0 18 0
|
||||
-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
|
||||
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri2.vhd TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri2.inc FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri2.cmp TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri2.bsf TRUE FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri2_inst.vhd FALSE
|
||||
-- Retrieval info: LIB_FILE: lpm
|
||||
56
FPGA_quartus_GE/altip_orig/lpm_bustri3.bsf
Normal file
56
FPGA_quartus_GE/altip_orig/lpm_bustri3.bsf
Normal file
@@ -0,0 +1,56 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2008 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 0 0 80 40)
|
||||
(text "lpm_bustri3" (rect 7 1 86 17)(font "Arial" (font_size 10)))
|
||||
(text "inst" (rect 8 24 25 36)(font "Arial" ))
|
||||
(port
|
||||
(pt 40 40)
|
||||
(input)
|
||||
(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
|
||||
(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
|
||||
(line (pt 40 40)(pt 40 28)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 24)
|
||||
(input)
|
||||
(text "data[5..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
|
||||
(text "data[5..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible))
|
||||
(line (pt 0 24)(pt 32 24)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 80 24)
|
||||
(bidir)
|
||||
(text "tridata[5..0]" (rect 0 0 63 14)(font "Arial" (font_size 8)))
|
||||
(text "tridata[5..0]" (rect 84 -30 97 24)(font "Arial" (font_size 8))(invisible))
|
||||
(line (pt 80 24)(pt 48 24)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(text "6" (rect 63 25 68 37)(font "Arial" ))
|
||||
(text "6" (rect 15 25 20 37)(font "Arial" ))
|
||||
(line (pt 32 16)(pt 48 24)(line_width 1))
|
||||
(line (pt 48 24)(pt 32 32)(line_width 1))
|
||||
(line (pt 32 32)(pt 32 16)(line_width 1))
|
||||
(line (pt 58 28)(pt 66 20)(line_width 1))
|
||||
(line (pt 10 28)(pt 18 20)(line_width 1))
|
||||
)
|
||||
)
|
||||
5
FPGA_quartus_GE/altip_orig/lpm_bustri3.qip
Normal file
5
FPGA_quartus_GE/altip_orig/lpm_bustri3.qip
Normal file
@@ -0,0 +1,5 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI"
|
||||
set_global_assignment -name IP_TOOL_VERSION "8.1"
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri3.vhd"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri3.bsf"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri3.cmp"]
|
||||
107
FPGA_quartus_GE/altip_orig/lpm_bustri3.vhd
Normal file
107
FPGA_quartus_GE/altip_orig/lpm_bustri3.vhd
Normal file
@@ -0,0 +1,107 @@
|
||||
-- megafunction wizard: %LPM_BUSTRI%
|
||||
-- GENERATION: STANDARD
|
||||
-- VERSION: WM1.0
|
||||
-- MODULE: lpm_bustri
|
||||
|
||||
-- ============================================================
|
||||
-- File Name: lpm_bustri3.vhd
|
||||
-- Megafunction Name(s):
|
||||
-- lpm_bustri
|
||||
--
|
||||
-- Simulation Library Files(s):
|
||||
-- lpm
|
||||
-- ============================================================
|
||||
-- ************************************************************
|
||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
--
|
||||
-- 8.1 Build 163 10/28/2008 SJ Web Edition
|
||||
-- ************************************************************
|
||||
|
||||
|
||||
--Copyright (C) 1991-2008 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
|
||||
LIBRARY lpm;
|
||||
USE lpm.all;
|
||||
|
||||
ENTITY lpm_bustri3 IS
|
||||
PORT
|
||||
(
|
||||
data : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
|
||||
enabledt : IN STD_LOGIC ;
|
||||
tridata : INOUT STD_LOGIC_VECTOR (5 DOWNTO 0)
|
||||
);
|
||||
END lpm_bustri3;
|
||||
|
||||
|
||||
ARCHITECTURE SYN OF lpm_bustri3 IS
|
||||
|
||||
|
||||
|
||||
|
||||
COMPONENT lpm_bustri
|
||||
GENERIC (
|
||||
lpm_type : STRING;
|
||||
lpm_width : NATURAL
|
||||
);
|
||||
PORT (
|
||||
enabledt : IN STD_LOGIC ;
|
||||
data : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
|
||||
tridata : INOUT STD_LOGIC_VECTOR (5 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
BEGIN
|
||||
|
||||
lpm_bustri_component : lpm_bustri
|
||||
GENERIC MAP (
|
||||
lpm_type => "LPM_BUSTRI",
|
||||
lpm_width => 6
|
||||
)
|
||||
PORT MAP (
|
||||
enabledt => enabledt,
|
||||
data => data,
|
||||
tridata => tridata
|
||||
);
|
||||
|
||||
|
||||
|
||||
END SYN;
|
||||
|
||||
-- ============================================================
|
||||
-- CNX file retrieval info
|
||||
-- ============================================================
|
||||
-- Retrieval info: PRIVATE: BiDir NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
-- Retrieval info: PRIVATE: nBit NUMERIC "6"
|
||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
|
||||
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "6"
|
||||
-- Retrieval info: USED_PORT: data 0 0 6 0 INPUT NODEFVAL data[5..0]
|
||||
-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
|
||||
-- Retrieval info: USED_PORT: tridata 0 0 6 0 BIDIR NODEFVAL tridata[5..0]
|
||||
-- Retrieval info: CONNECT: tridata 0 0 6 0 @tridata 0 0 6 0
|
||||
-- Retrieval info: CONNECT: @data 0 0 6 0 data 0 0 6 0
|
||||
-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
|
||||
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri3.vhd TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri3.inc FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri3.cmp TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri3.bsf TRUE FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri3_inst.vhd FALSE
|
||||
-- Retrieval info: LIB_FILE: lpm
|
||||
56
FPGA_quartus_GE/altip_orig/lpm_bustri4.bsf
Normal file
56
FPGA_quartus_GE/altip_orig/lpm_bustri4.bsf
Normal file
@@ -0,0 +1,56 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2008 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 0 0 80 40)
|
||||
(text "lpm_bustri4" (rect 7 1 86 17)(font "Arial" (font_size 10)))
|
||||
(text "inst" (rect 8 24 25 36)(font "Arial" ))
|
||||
(port
|
||||
(pt 40 40)
|
||||
(input)
|
||||
(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
|
||||
(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
|
||||
(line (pt 40 40)(pt 40 28)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 24)
|
||||
(input)
|
||||
(text "data[4..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
|
||||
(text "data[4..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible))
|
||||
(line (pt 0 24)(pt 32 24)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 80 24)
|
||||
(bidir)
|
||||
(text "tridata[4..0]" (rect 0 0 63 14)(font "Arial" (font_size 8)))
|
||||
(text "tridata[4..0]" (rect 84 -30 97 24)(font "Arial" (font_size 8))(invisible))
|
||||
(line (pt 80 24)(pt 48 24)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(text "5" (rect 63 25 68 37)(font "Arial" ))
|
||||
(text "5" (rect 15 25 20 37)(font "Arial" ))
|
||||
(line (pt 32 16)(pt 48 24)(line_width 1))
|
||||
(line (pt 48 24)(pt 32 32)(line_width 1))
|
||||
(line (pt 32 32)(pt 32 16)(line_width 1))
|
||||
(line (pt 58 28)(pt 66 20)(line_width 1))
|
||||
(line (pt 10 28)(pt 18 20)(line_width 1))
|
||||
)
|
||||
)
|
||||
5
FPGA_quartus_GE/altip_orig/lpm_bustri4.qip
Normal file
5
FPGA_quartus_GE/altip_orig/lpm_bustri4.qip
Normal file
@@ -0,0 +1,5 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI"
|
||||
set_global_assignment -name IP_TOOL_VERSION "8.1"
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri4.vhd"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri4.bsf"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri4.cmp"]
|
||||
107
FPGA_quartus_GE/altip_orig/lpm_bustri4.vhd
Normal file
107
FPGA_quartus_GE/altip_orig/lpm_bustri4.vhd
Normal file
@@ -0,0 +1,107 @@
|
||||
-- megafunction wizard: %LPM_BUSTRI%
|
||||
-- GENERATION: STANDARD
|
||||
-- VERSION: WM1.0
|
||||
-- MODULE: lpm_bustri
|
||||
|
||||
-- ============================================================
|
||||
-- File Name: lpm_bustri4.vhd
|
||||
-- Megafunction Name(s):
|
||||
-- lpm_bustri
|
||||
--
|
||||
-- Simulation Library Files(s):
|
||||
-- lpm
|
||||
-- ============================================================
|
||||
-- ************************************************************
|
||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
--
|
||||
-- 8.1 Build 163 10/28/2008 SJ Web Edition
|
||||
-- ************************************************************
|
||||
|
||||
|
||||
--Copyright (C) 1991-2008 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
|
||||
LIBRARY lpm;
|
||||
USE lpm.all;
|
||||
|
||||
ENTITY lpm_bustri4 IS
|
||||
PORT
|
||||
(
|
||||
data : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
|
||||
enabledt : IN STD_LOGIC ;
|
||||
tridata : INOUT STD_LOGIC_VECTOR (4 DOWNTO 0)
|
||||
);
|
||||
END lpm_bustri4;
|
||||
|
||||
|
||||
ARCHITECTURE SYN OF lpm_bustri4 IS
|
||||
|
||||
|
||||
|
||||
|
||||
COMPONENT lpm_bustri
|
||||
GENERIC (
|
||||
lpm_type : STRING;
|
||||
lpm_width : NATURAL
|
||||
);
|
||||
PORT (
|
||||
enabledt : IN STD_LOGIC ;
|
||||
data : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
|
||||
tridata : INOUT STD_LOGIC_VECTOR (4 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
BEGIN
|
||||
|
||||
lpm_bustri_component : lpm_bustri
|
||||
GENERIC MAP (
|
||||
lpm_type => "LPM_BUSTRI",
|
||||
lpm_width => 5
|
||||
)
|
||||
PORT MAP (
|
||||
enabledt => enabledt,
|
||||
data => data,
|
||||
tridata => tridata
|
||||
);
|
||||
|
||||
|
||||
|
||||
END SYN;
|
||||
|
||||
-- ============================================================
|
||||
-- CNX file retrieval info
|
||||
-- ============================================================
|
||||
-- Retrieval info: PRIVATE: BiDir NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
-- Retrieval info: PRIVATE: nBit NUMERIC "5"
|
||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
|
||||
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5"
|
||||
-- Retrieval info: USED_PORT: data 0 0 5 0 INPUT NODEFVAL data[4..0]
|
||||
-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
|
||||
-- Retrieval info: USED_PORT: tridata 0 0 5 0 BIDIR NODEFVAL tridata[4..0]
|
||||
-- Retrieval info: CONNECT: tridata 0 0 5 0 @tridata 0 0 5 0
|
||||
-- Retrieval info: CONNECT: @data 0 0 5 0 data 0 0 5 0
|
||||
-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
|
||||
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri4.vhd TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri4.inc FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri4.cmp TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri4.bsf TRUE FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri4_inst.vhd FALSE
|
||||
-- Retrieval info: LIB_FILE: lpm
|
||||
56
FPGA_quartus_GE/altip_orig/lpm_bustri5.bsf
Normal file
56
FPGA_quartus_GE/altip_orig/lpm_bustri5.bsf
Normal file
@@ -0,0 +1,56 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2008 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 0 0 80 40)
|
||||
(text "lpm_bustri5" (rect 7 1 86 17)(font "Arial" (font_size 10)))
|
||||
(text "inst" (rect 8 24 25 36)(font "Arial" ))
|
||||
(port
|
||||
(pt 40 40)
|
||||
(input)
|
||||
(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
|
||||
(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
|
||||
(line (pt 40 40)(pt 40 28)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 24)
|
||||
(input)
|
||||
(text "data[7..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
|
||||
(text "data[7..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible))
|
||||
(line (pt 0 24)(pt 32 24)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 80 24)
|
||||
(bidir)
|
||||
(text "tridata[7..0]" (rect 0 0 63 14)(font "Arial" (font_size 8)))
|
||||
(text "tridata[7..0]" (rect 84 -30 97 24)(font "Arial" (font_size 8))(invisible))
|
||||
(line (pt 80 24)(pt 48 24)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(text "8" (rect 63 25 68 37)(font "Arial" ))
|
||||
(text "8" (rect 15 25 20 37)(font "Arial" ))
|
||||
(line (pt 32 16)(pt 48 24)(line_width 1))
|
||||
(line (pt 48 24)(pt 32 32)(line_width 1))
|
||||
(line (pt 32 32)(pt 32 16)(line_width 1))
|
||||
(line (pt 58 28)(pt 66 20)(line_width 1))
|
||||
(line (pt 10 28)(pt 18 20)(line_width 1))
|
||||
)
|
||||
)
|
||||
24
FPGA_quartus_GE/altip_orig/lpm_bustri5.inc
Normal file
24
FPGA_quartus_GE/altip_orig/lpm_bustri5.inc
Normal file
@@ -0,0 +1,24 @@
|
||||
--Copyright (C) 1991-2008 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
FUNCTION lpm_bustri5
|
||||
(
|
||||
data[7..0],
|
||||
enabledt
|
||||
)
|
||||
|
||||
RETURNS (
|
||||
tridata[7..0]
|
||||
);
|
||||
6
FPGA_quartus_GE/altip_orig/lpm_bustri5.qip
Normal file
6
FPGA_quartus_GE/altip_orig/lpm_bustri5.qip
Normal file
@@ -0,0 +1,6 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI"
|
||||
set_global_assignment -name IP_TOOL_VERSION "8.1"
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri5.vhd"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri5.bsf"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri5.inc"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri5.cmp"]
|
||||
107
FPGA_quartus_GE/altip_orig/lpm_bustri5.vhd
Normal file
107
FPGA_quartus_GE/altip_orig/lpm_bustri5.vhd
Normal file
@@ -0,0 +1,107 @@
|
||||
-- megafunction wizard: %LPM_BUSTRI%
|
||||
-- GENERATION: STANDARD
|
||||
-- VERSION: WM1.0
|
||||
-- MODULE: lpm_bustri
|
||||
|
||||
-- ============================================================
|
||||
-- File Name: lpm_bustri5.vhd
|
||||
-- Megafunction Name(s):
|
||||
-- lpm_bustri
|
||||
--
|
||||
-- Simulation Library Files(s):
|
||||
-- lpm
|
||||
-- ============================================================
|
||||
-- ************************************************************
|
||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
--
|
||||
-- 8.1 Build 163 10/28/2008 SJ Web Edition
|
||||
-- ************************************************************
|
||||
|
||||
|
||||
--Copyright (C) 1991-2008 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
|
||||
LIBRARY lpm;
|
||||
USE lpm.all;
|
||||
|
||||
ENTITY lpm_bustri5 IS
|
||||
PORT
|
||||
(
|
||||
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
|
||||
enabledt : IN STD_LOGIC ;
|
||||
tridata : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0)
|
||||
);
|
||||
END lpm_bustri5;
|
||||
|
||||
|
||||
ARCHITECTURE SYN OF lpm_bustri5 IS
|
||||
|
||||
|
||||
|
||||
|
||||
COMPONENT lpm_bustri
|
||||
GENERIC (
|
||||
lpm_type : STRING;
|
||||
lpm_width : NATURAL
|
||||
);
|
||||
PORT (
|
||||
enabledt : IN STD_LOGIC ;
|
||||
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
|
||||
tridata : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
BEGIN
|
||||
|
||||
lpm_bustri_component : lpm_bustri
|
||||
GENERIC MAP (
|
||||
lpm_type => "LPM_BUSTRI",
|
||||
lpm_width => 8
|
||||
)
|
||||
PORT MAP (
|
||||
enabledt => enabledt,
|
||||
data => data,
|
||||
tridata => tridata
|
||||
);
|
||||
|
||||
|
||||
|
||||
END SYN;
|
||||
|
||||
-- ============================================================
|
||||
-- CNX file retrieval info
|
||||
-- ============================================================
|
||||
-- Retrieval info: PRIVATE: BiDir NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
-- Retrieval info: PRIVATE: nBit NUMERIC "8"
|
||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
|
||||
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
|
||||
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
|
||||
-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
|
||||
-- Retrieval info: USED_PORT: tridata 0 0 8 0 BIDIR NODEFVAL tridata[7..0]
|
||||
-- Retrieval info: CONNECT: tridata 0 0 8 0 @tridata 0 0 8 0
|
||||
-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
|
||||
-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
|
||||
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri5.vhd TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri5.inc TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri5.cmp TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri5.bsf TRUE FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri5_inst.vhd FALSE
|
||||
-- Retrieval info: LIB_FILE: lpm
|
||||
56
FPGA_quartus_GE/altip_orig/lpm_bustri6.bsf
Normal file
56
FPGA_quartus_GE/altip_orig/lpm_bustri6.bsf
Normal file
@@ -0,0 +1,56 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2008 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 0 0 80 40)
|
||||
(text "lpm_bustri6" (rect 7 1 86 17)(font "Arial" (font_size 10)))
|
||||
(text "inst" (rect 8 24 25 36)(font "Arial" ))
|
||||
(port
|
||||
(pt 40 40)
|
||||
(input)
|
||||
(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
|
||||
(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
|
||||
(line (pt 40 40)(pt 40 28)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 24)
|
||||
(input)
|
||||
(text "data[23..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
|
||||
(text "data[23..0]" (rect -3 -27 10 24)(font "Arial" (font_size 8))(invisible))
|
||||
(line (pt 0 24)(pt 32 24)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 80 24)
|
||||
(bidir)
|
||||
(text "tridata[23..0]" (rect 0 0 70 14)(font "Arial" (font_size 8)))
|
||||
(text "tridata[23..0]" (rect 84 -36 97 24)(font "Arial" (font_size 8))(invisible))
|
||||
(line (pt 80 24)(pt 48 24)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(text "24" (rect 61 25 71 37)(font "Arial" ))
|
||||
(text "24" (rect 13 25 23 37)(font "Arial" ))
|
||||
(line (pt 32 16)(pt 48 24)(line_width 1))
|
||||
(line (pt 48 24)(pt 32 32)(line_width 1))
|
||||
(line (pt 32 32)(pt 32 16)(line_width 1))
|
||||
(line (pt 56 28)(pt 64 20)(line_width 1))
|
||||
(line (pt 8 28)(pt 16 20)(line_width 1))
|
||||
)
|
||||
)
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user