IP migration and cleanup - again

2014-03-07 21:03:00 +00:00
parent a5a899af74
commit 1387bde100
441 changed files with 163358 additions and 0 deletions
--- a/FPGA_quartus_GE/altip/lpm_shiftreg2.v
+++ b/FPGA_quartus_GE/altip/lpm_shiftreg2.v
@@ -0,0 +1,112 @@
+// megafunction wizard: %LPM_SHIFTREG%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: LPM_SHIFTREG 
+
+// ============================================================
+// File Name: lpm_shiftreg2.v
+// Megafunction Name(s):
+// 			LPM_SHIFTREG
+//
+// Simulation Library Files(s):
+// 			lpm
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.1.0 Build 162 10/23/2013 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2013 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module lpm_shiftreg2 (
+	clock,
+	shiftin,
+	shiftout);
+
+	input	  clock;
+	input	  shiftin;
+	output	  shiftout;
+
+	wire  sub_wire0;
+	wire  shiftout = sub_wire0;
+
+	lpm_shiftreg	LPM_SHIFTREG_component (
+				.clock (clock),
+				.shiftin (shiftin),
+				.shiftout (sub_wire0)
+				// synopsys translate_off
+				,
+				.aclr (),
+				.aset (),
+				.data (),
+				.enable (),
+				.load (),
+				.q (),
+				.sclr (),
+				.sset ()
+				// synopsys translate_on
+				);
+	defparam
+		LPM_SHIFTREG_component.lpm_direction = "RIGHT",
+		LPM_SHIFTREG_component.lpm_type = "LPM_SHIFTREG",
+		LPM_SHIFTREG_component.lpm_width = 4;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACLR NUMERIC "0"
+// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
+// Retrieval info: PRIVATE: ASET NUMERIC "0"
+// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
+// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: PRIVATE: LeftShift NUMERIC "0"
+// Retrieval info: PRIVATE: ParallelDataInput NUMERIC "0"
+// Retrieval info: PRIVATE: Q_OUT NUMERIC "0"
+// Retrieval info: PRIVATE: SCLR NUMERIC "0"
+// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
+// Retrieval info: PRIVATE: SSET NUMERIC "0"
+// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1"
+// Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "1"
+// Retrieval info: PRIVATE: nBit NUMERIC "4"
+// Retrieval info: PRIVATE: new_diagram STRING "1"
+// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+// Retrieval info: CONSTANT: LPM_DIRECTION STRING "RIGHT"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "4"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
+// Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL "shiftin"
+// Retrieval info: USED_PORT: shiftout 0 0 0 0 OUTPUT NODEFVAL "shiftout"
+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0
+// Retrieval info: CONNECT: shiftout 0 0 0 0 @shiftout 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg2.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg2.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg2.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg2.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg2_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg2_bb.v FALSE
+// Retrieval info: LIB_FILE: lpm