IP migration and cleanup - again

2014-03-07 21:03:00 +00:00
parent a5a899af74
commit 1387bde100
441 changed files with 163358 additions and 0 deletions
--- a/FPGA_quartus_GE/altip/lpm_muxDZ.v
+++ b/FPGA_quartus_GE/altip/lpm_muxDZ.v
@@ -0,0 +1,120 @@
+// megafunction wizard: %LPM_MUX%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: LPM_MUX 
+
+// ============================================================
+// File Name: lpm_muxDZ.v
+// Megafunction Name(s):
+// 			LPM_MUX
+//
+// Simulation Library Files(s):
+// 			lpm
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.1.0 Build 162 10/23/2013 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2013 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module lpm_muxDZ (
+	clken,
+	clock,
+	data0x,
+	data1x,
+	sel,
+	result);
+
+	input	  clken;
+	input	  clock;
+	input	[127:0]  data0x;
+	input	[127:0]  data1x;
+	input	  sel;
+	output	[127:0]  result;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1	  clken;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [127:0] sub_wire0;
+	wire [127:0] sub_wire3 = data1x[127:0];
+	wire [127:0] result = sub_wire0[127:0];
+	wire [127:0] sub_wire1 = data0x[127:0];
+	wire [255:0] sub_wire2 = {sub_wire3, sub_wire1};
+	wire  sub_wire4 = sel;
+	wire  sub_wire5 = sub_wire4;
+
+	lpm_mux	LPM_MUX_component (
+				.clock (clock),
+				.data (sub_wire2),
+				.sel (sub_wire5),
+				.clken (clken),
+				.result (sub_wire0)
+				// synopsys translate_off
+				,
+				.aclr ()
+				// synopsys translate_on
+				);
+	defparam
+		LPM_MUX_component.lpm_pipeline = 1,
+		LPM_MUX_component.lpm_size = 2,
+		LPM_MUX_component.lpm_type = "LPM_MUX",
+		LPM_MUX_component.lpm_width = 128,
+		LPM_MUX_component.lpm_widths = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: new_diagram STRING "1"
+// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
+// Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128"
+// Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1"
+// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC "clken"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
+// Retrieval info: USED_PORT: data0x 0 0 128 0 INPUT NODEFVAL "data0x[127..0]"
+// Retrieval info: USED_PORT: data1x 0 0 128 0 INPUT NODEFVAL "data1x[127..0]"
+// Retrieval info: USED_PORT: result 0 0 128 0 OUTPUT NODEFVAL "result[127..0]"
+// Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL "sel"
+// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @data 0 0 128 0 data0x 0 0 128 0
+// Retrieval info: CONNECT: @data 0 0 128 128 data1x 0 0 128 0
+// Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0
+// Retrieval info: CONNECT: result 0 0 128 0 @result 0 0 128 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ_bb.v FALSE
+// Retrieval info: LIB_FILE: lpm