IP migration and cleanup - again
This commit is contained in:
torlus
16
FPGA_quartus_GE/altip/altddio_bidir0.ppf
Normal file
16
FPGA_quartus_GE/altip/altddio_bidir0.ppf
Normal file
@@ -0,0 +1,16 @@
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<?xml version="1.0" encoding="UTF-8" ?>
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<!DOCTYPE pinplan>
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<pinplan intended_family="Cyclone III" variation_name="altddio_bidir0" megafunction_name="ALTDDIO_BIDIR" specifies="all_ports">
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<global>
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<pin name="datain_h[31..0]" direction="input" scope="external" />
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<pin name="datain_l[31..0]" direction="input" scope="external" />
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<pin name="inclock" direction="input" scope="external" source="clock" />
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<pin name="oe" direction="input" scope="external" />
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<pin name="outclock" direction="input" scope="external" source="clock" />
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<pin name="combout[31..0]" direction="output" scope="external" />
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<pin name="dataout_h[31..0]" direction="output" scope="external" />
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<pin name="dataout_l[31..0]" direction="output" scope="external" />
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<pin name="padio[31..0]" direction="bidir" scope="external" />
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</global>
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</pinplan>
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4
FPGA_quartus_GE/altip/altddio_bidir0.qip
Normal file
4
FPGA_quartus_GE/altip/altddio_bidir0.qip
Normal file
@@ -0,0 +1,4 @@
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set_global_assignment -name IP_TOOL_NAME "ALTDDIO_BIDIR"
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set_global_assignment -name IP_TOOL_VERSION "13.1"
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "altddio_bidir0.v"]
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set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.ppf"]
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139
FPGA_quartus_GE/altip/altddio_bidir0.v
Normal file
139
FPGA_quartus_GE/altip/altddio_bidir0.v
Normal file
@@ -0,0 +1,139 @@
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// megafunction wizard: %ALTDDIO_BIDIR%
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// GENERATION: STANDARD
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// VERSION: WM1.0
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// MODULE: ALTDDIO_BIDIR
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// ============================================================
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// File Name: altddio_bidir0.v
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// Megafunction Name(s):
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// ALTDDIO_BIDIR
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//
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// Simulation Library Files(s):
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// altera_mf
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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||||
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
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//Copyright (C) 1991-2013 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
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||||
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// synopsys translate_off
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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module altddio_bidir0 (
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datain_h,
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datain_l,
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inclock,
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oe,
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outclock,
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combout,
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dataout_h,
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dataout_l,
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padio);
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input [31:0] datain_h;
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input [31:0] datain_l;
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input inclock;
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input oe;
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input outclock;
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output [31:0] combout;
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output [31:0] dataout_h;
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output [31:0] dataout_l;
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inout [31:0] padio;
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wire [31:0] sub_wire0;
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wire [31:0] sub_wire1;
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wire [31:0] sub_wire2;
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wire [31:0] combout = sub_wire0[31:0];
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wire [31:0] dataout_h = sub_wire1[31:0];
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wire [31:0] dataout_l = sub_wire2[31:0];
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altddio_bidir ALTDDIO_BIDIR_component (
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.padio (padio),
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.datain_h (datain_h),
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.datain_l (datain_l),
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.oe (oe),
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.outclock (outclock),
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.inclock (inclock),
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.combout (sub_wire0),
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.dataout_h (sub_wire1),
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.dataout_l (sub_wire2),
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.aclr (1'b0),
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.aset (1'b0),
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.dqsundelayedout (),
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.inclocken (1'b1),
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.oe_out (),
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.outclocken (1'b1),
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.sclr (1'b0),
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.sset (1'b0));
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defparam
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ALTDDIO_BIDIR_component.extend_oe_disable = "OFF",
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ALTDDIO_BIDIR_component.implement_input_in_lcell = "ON",
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ALTDDIO_BIDIR_component.intended_device_family = "Cyclone III",
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ALTDDIO_BIDIR_component.invert_output = "OFF",
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ALTDDIO_BIDIR_component.lpm_hint = "UNUSED",
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ALTDDIO_BIDIR_component.lpm_type = "altddio_bidir",
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ALTDDIO_BIDIR_component.oe_reg = "UNREGISTERED",
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ALTDDIO_BIDIR_component.power_up_high = "OFF",
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ALTDDIO_BIDIR_component.width = 32;
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endmodule
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// ============================================================
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// CNX file retrieval info
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||||
// ============================================================
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||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
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// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF"
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// Retrieval info: CONSTANT: IMPLEMENT_INPUT_IN_LCELL STRING "ON"
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// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
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// Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
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// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
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// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_bidir"
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// Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED"
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// Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
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// Retrieval info: CONSTANT: WIDTH NUMERIC "32"
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// Retrieval info: USED_PORT: combout 0 0 32 0 OUTPUT NODEFVAL "combout[31..0]"
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// Retrieval info: CONNECT: combout 0 0 32 0 @combout 0 0 32 0
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// Retrieval info: USED_PORT: datain_h 0 0 32 0 INPUT NODEFVAL "datain_h[31..0]"
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||||
// Retrieval info: CONNECT: @datain_h 0 0 32 0 datain_h 0 0 32 0
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||||
// Retrieval info: USED_PORT: datain_l 0 0 32 0 INPUT NODEFVAL "datain_l[31..0]"
|
||||
// Retrieval info: CONNECT: @datain_l 0 0 32 0 datain_l 0 0 32 0
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||||
// Retrieval info: USED_PORT: dataout_h 0 0 32 0 OUTPUT NODEFVAL "dataout_h[31..0]"
|
||||
// Retrieval info: CONNECT: dataout_h 0 0 32 0 @dataout_h 0 0 32 0
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||||
// Retrieval info: USED_PORT: dataout_l 0 0 32 0 OUTPUT NODEFVAL "dataout_l[31..0]"
|
||||
// Retrieval info: CONNECT: dataout_l 0 0 32 0 @dataout_l 0 0 32 0
|
||||
// Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "inclock"
|
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// Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0
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||||
// Retrieval info: USED_PORT: oe 0 0 0 0 INPUT NODEFVAL "oe"
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// Retrieval info: CONNECT: @oe 0 0 0 0 oe 0 0 0 0
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// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock"
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||||
// Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
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// Retrieval info: USED_PORT: padio 0 0 32 0 BIDIR NODEFVAL "padio[31..0]"
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||||
// Retrieval info: CONNECT: padio 0 0 32 0 @padio 0 0 32 0
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||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.v TRUE FALSE
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||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.qip TRUE FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.bsf FALSE TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0_inst.v FALSE TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0_bb.v FALSE TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.inc FALSE TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.cmp FALSE TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.ppf TRUE FALSE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
11
FPGA_quartus_GE/altip/altddio_out0.ppf
Normal file
11
FPGA_quartus_GE/altip/altddio_out0.ppf
Normal file
@@ -0,0 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<!DOCTYPE pinplan>
|
||||
<pinplan intended_family="Cyclone III" variation_name="altddio_out0" megafunction_name="ALTDDIO_OUT" specifies="all_ports">
|
||||
<global>
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||||
<pin name="datain_h[3..0]" direction="input" scope="external" />
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||||
<pin name="datain_l[3..0]" direction="input" scope="external" />
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<pin name="outclock" direction="input" scope="external" source="clock" />
|
||||
<pin name="dataout[3..0]" direction="output" scope="external" />
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||||
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||||
</global>
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||||
</pinplan>
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||||
4
FPGA_quartus_GE/altip/altddio_out0.qip
Normal file
4
FPGA_quartus_GE/altip/altddio_out0.qip
Normal file
@@ -0,0 +1,4 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT"
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||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
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||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "altddio_out0.v"]
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||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.ppf"]
|
||||
107
FPGA_quartus_GE/altip/altddio_out0.v
Normal file
107
FPGA_quartus_GE/altip/altddio_out0.v
Normal file
@@ -0,0 +1,107 @@
|
||||
// megafunction wizard: %ALTDDIO_OUT%
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||||
// GENERATION: STANDARD
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||||
// VERSION: WM1.0
|
||||
// MODULE: ALTDDIO_OUT
|
||||
|
||||
// ============================================================
|
||||
// File Name: altddio_out0.v
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// Megafunction Name(s):
|
||||
// ALTDDIO_OUT
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||||
//
|
||||
// Simulation Library Files(s):
|
||||
// altera_mf
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2013 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module altddio_out0 (
|
||||
datain_h,
|
||||
datain_l,
|
||||
outclock,
|
||||
dataout);
|
||||
|
||||
input [3:0] datain_h;
|
||||
input [3:0] datain_l;
|
||||
input outclock;
|
||||
output [3:0] dataout;
|
||||
|
||||
wire [3:0] sub_wire0;
|
||||
wire [3:0] dataout = sub_wire0[3:0];
|
||||
|
||||
altddio_out ALTDDIO_OUT_component (
|
||||
.datain_h (datain_h),
|
||||
.datain_l (datain_l),
|
||||
.outclock (outclock),
|
||||
.dataout (sub_wire0),
|
||||
.aclr (1'b0),
|
||||
.aset (1'b0),
|
||||
.oe (1'b1),
|
||||
.oe_out (),
|
||||
.outclocken (1'b1),
|
||||
.sclr (1'b0),
|
||||
.sset (1'b0));
|
||||
defparam
|
||||
ALTDDIO_OUT_component.extend_oe_disable = "OFF",
|
||||
ALTDDIO_OUT_component.intended_device_family = "Cyclone III",
|
||||
ALTDDIO_OUT_component.invert_output = "ON",
|
||||
ALTDDIO_OUT_component.lpm_hint = "UNUSED",
|
||||
ALTDDIO_OUT_component.lpm_type = "altddio_out",
|
||||
ALTDDIO_OUT_component.oe_reg = "UNREGISTERED",
|
||||
ALTDDIO_OUT_component.power_up_high = "ON",
|
||||
ALTDDIO_OUT_component.width = 4;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: CONSTANT: INVERT_OUTPUT STRING "ON"
|
||||
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
|
||||
// Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED"
|
||||
// Retrieval info: CONSTANT: POWER_UP_HIGH STRING "ON"
|
||||
// Retrieval info: CONSTANT: WIDTH NUMERIC "4"
|
||||
// Retrieval info: USED_PORT: datain_h 0 0 4 0 INPUT NODEFVAL "datain_h[3..0]"
|
||||
// Retrieval info: CONNECT: @datain_h 0 0 4 0 datain_h 0 0 4 0
|
||||
// Retrieval info: USED_PORT: datain_l 0 0 4 0 INPUT NODEFVAL "datain_l[3..0]"
|
||||
// Retrieval info: CONNECT: @datain_l 0 0 4 0 datain_l 0 0 4 0
|
||||
// Retrieval info: USED_PORT: dataout 0 0 4 0 OUTPUT NODEFVAL "dataout[3..0]"
|
||||
// Retrieval info: CONNECT: dataout 0 0 4 0 @dataout 0 0 4 0
|
||||
// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock"
|
||||
// Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.v TRUE FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.qip TRUE FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.bsf FALSE TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0_inst.v FALSE TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0_bb.v FALSE TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.inc FALSE TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.cmp FALSE TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.ppf TRUE FALSE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
11
FPGA_quartus_GE/altip/altddio_out1.ppf
Normal file
11
FPGA_quartus_GE/altip/altddio_out1.ppf
Normal file
@@ -0,0 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<!DOCTYPE pinplan>
|
||||
<pinplan intended_family="Cyclone III" variation_name="altddio_out1" megafunction_name="ALTDDIO_OUT" specifies="all_ports">
|
||||
<global>
|
||||
<pin name="datain_h[0..0]" direction="input" scope="external" />
|
||||
<pin name="datain_l[0..0]" direction="input" scope="external" />
|
||||
<pin name="outclock" direction="input" scope="external" source="clock" />
|
||||
<pin name="dataout[0..0]" direction="output" scope="external" />
|
||||
|
||||
</global>
|
||||
</pinplan>
|
||||
4
FPGA_quartus_GE/altip/altddio_out1.qip
Normal file
4
FPGA_quartus_GE/altip/altddio_out1.qip
Normal file
@@ -0,0 +1,4 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "altddio_out1.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out1.ppf"]
|
||||
107
FPGA_quartus_GE/altip/altddio_out1.v
Normal file
107
FPGA_quartus_GE/altip/altddio_out1.v
Normal file
@@ -0,0 +1,107 @@
|
||||
// megafunction wizard: %ALTDDIO_OUT%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: ALTDDIO_OUT
|
||||
|
||||
// ============================================================
|
||||
// File Name: altddio_out1.v
|
||||
// Megafunction Name(s):
|
||||
// ALTDDIO_OUT
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// altera_mf
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2013 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module altddio_out1 (
|
||||
datain_h,
|
||||
datain_l,
|
||||
outclock,
|
||||
dataout);
|
||||
|
||||
input [0:0] datain_h;
|
||||
input [0:0] datain_l;
|
||||
input outclock;
|
||||
output [0:0] dataout;
|
||||
|
||||
wire [0:0] sub_wire0;
|
||||
wire [0:0] dataout = sub_wire0[0:0];
|
||||
|
||||
altddio_out ALTDDIO_OUT_component (
|
||||
.datain_h (datain_h),
|
||||
.datain_l (datain_l),
|
||||
.outclock (outclock),
|
||||
.dataout (sub_wire0),
|
||||
.aclr (1'b0),
|
||||
.aset (1'b0),
|
||||
.oe (1'b1),
|
||||
.oe_out (),
|
||||
.outclocken (1'b1),
|
||||
.sclr (1'b0),
|
||||
.sset (1'b0));
|
||||
defparam
|
||||
ALTDDIO_OUT_component.extend_oe_disable = "OFF",
|
||||
ALTDDIO_OUT_component.intended_device_family = "Cyclone III",
|
||||
ALTDDIO_OUT_component.invert_output = "OFF",
|
||||
ALTDDIO_OUT_component.lpm_hint = "UNUSED",
|
||||
ALTDDIO_OUT_component.lpm_type = "altddio_out",
|
||||
ALTDDIO_OUT_component.oe_reg = "UNREGISTERED",
|
||||
ALTDDIO_OUT_component.power_up_high = "OFF",
|
||||
ALTDDIO_OUT_component.width = 1;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
|
||||
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
|
||||
// Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED"
|
||||
// Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
|
||||
// Retrieval info: CONSTANT: WIDTH NUMERIC "1"
|
||||
// Retrieval info: USED_PORT: datain_h 0 0 1 0 INPUT NODEFVAL "datain_h[0..0]"
|
||||
// Retrieval info: CONNECT: @datain_h 0 0 1 0 datain_h 0 0 1 0
|
||||
// Retrieval info: USED_PORT: datain_l 0 0 1 0 INPUT NODEFVAL "datain_l[0..0]"
|
||||
// Retrieval info: CONNECT: @datain_l 0 0 1 0 datain_l 0 0 1 0
|
||||
// Retrieval info: USED_PORT: dataout 0 0 1 0 OUTPUT NODEFVAL "dataout[0..0]"
|
||||
// Retrieval info: CONNECT: dataout 0 0 1 0 @dataout 0 0 1 0
|
||||
// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock"
|
||||
// Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1.v TRUE FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1.qip TRUE FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1.bsf FALSE TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1_inst.v FALSE TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1_bb.v FALSE TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1.inc FALSE TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1.cmp FALSE TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1.ppf TRUE FALSE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
11
FPGA_quartus_GE/altip/altddio_out2.ppf
Normal file
11
FPGA_quartus_GE/altip/altddio_out2.ppf
Normal file
@@ -0,0 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<!DOCTYPE pinplan>
|
||||
<pinplan intended_family="Cyclone III" variation_name="altddio_out2" megafunction_name="ALTDDIO_OUT" specifies="all_ports">
|
||||
<global>
|
||||
<pin name="datain_h[23..0]" direction="input" scope="external" />
|
||||
<pin name="datain_l[23..0]" direction="input" scope="external" />
|
||||
<pin name="outclock" direction="input" scope="external" source="clock" />
|
||||
<pin name="dataout[23..0]" direction="output" scope="external" />
|
||||
|
||||
</global>
|
||||
</pinplan>
|
||||
4
FPGA_quartus_GE/altip/altddio_out2.qip
Normal file
4
FPGA_quartus_GE/altip/altddio_out2.qip
Normal file
@@ -0,0 +1,4 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "altddio_out2.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.ppf"]
|
||||
107
FPGA_quartus_GE/altip/altddio_out2.v
Normal file
107
FPGA_quartus_GE/altip/altddio_out2.v
Normal file
@@ -0,0 +1,107 @@
|
||||
// megafunction wizard: %ALTDDIO_OUT%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: ALTDDIO_OUT
|
||||
|
||||
// ============================================================
|
||||
// File Name: altddio_out2.v
|
||||
// Megafunction Name(s):
|
||||
// ALTDDIO_OUT
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// altera_mf
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2013 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module altddio_out2 (
|
||||
datain_h,
|
||||
datain_l,
|
||||
outclock,
|
||||
dataout);
|
||||
|
||||
input [23:0] datain_h;
|
||||
input [23:0] datain_l;
|
||||
input outclock;
|
||||
output [23:0] dataout;
|
||||
|
||||
wire [23:0] sub_wire0;
|
||||
wire [23:0] dataout = sub_wire0[23:0];
|
||||
|
||||
altddio_out ALTDDIO_OUT_component (
|
||||
.datain_h (datain_h),
|
||||
.datain_l (datain_l),
|
||||
.outclock (outclock),
|
||||
.dataout (sub_wire0),
|
||||
.aclr (1'b0),
|
||||
.aset (1'b0),
|
||||
.oe (1'b1),
|
||||
.oe_out (),
|
||||
.outclocken (1'b1),
|
||||
.sclr (1'b0),
|
||||
.sset (1'b0));
|
||||
defparam
|
||||
ALTDDIO_OUT_component.extend_oe_disable = "OFF",
|
||||
ALTDDIO_OUT_component.intended_device_family = "Cyclone III",
|
||||
ALTDDIO_OUT_component.invert_output = "OFF",
|
||||
ALTDDIO_OUT_component.lpm_hint = "UNUSED",
|
||||
ALTDDIO_OUT_component.lpm_type = "altddio_out",
|
||||
ALTDDIO_OUT_component.oe_reg = "UNREGISTERED",
|
||||
ALTDDIO_OUT_component.power_up_high = "OFF",
|
||||
ALTDDIO_OUT_component.width = 24;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
|
||||
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
|
||||
// Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED"
|
||||
// Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
|
||||
// Retrieval info: CONSTANT: WIDTH NUMERIC "24"
|
||||
// Retrieval info: USED_PORT: datain_h 0 0 24 0 INPUT NODEFVAL "datain_h[23..0]"
|
||||
// Retrieval info: CONNECT: @datain_h 0 0 24 0 datain_h 0 0 24 0
|
||||
// Retrieval info: USED_PORT: datain_l 0 0 24 0 INPUT NODEFVAL "datain_l[23..0]"
|
||||
// Retrieval info: CONNECT: @datain_l 0 0 24 0 datain_l 0 0 24 0
|
||||
// Retrieval info: USED_PORT: dataout 0 0 24 0 OUTPUT NODEFVAL "dataout[23..0]"
|
||||
// Retrieval info: CONNECT: dataout 0 0 24 0 @dataout 0 0 24 0
|
||||
// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock"
|
||||
// Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.v TRUE FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.qip TRUE FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.bsf FALSE TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2_inst.v FALSE TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2_bb.v FALSE TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.inc FALSE TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.cmp FALSE TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.ppf TRUE FALSE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
11
FPGA_quartus_GE/altip/altddio_out3.ppf
Normal file
11
FPGA_quartus_GE/altip/altddio_out3.ppf
Normal file
@@ -0,0 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<!DOCTYPE pinplan>
|
||||
<pinplan intended_family="Cyclone III" variation_name="altddio_out3" megafunction_name="ALTDDIO_OUT" specifies="all_ports">
|
||||
<global>
|
||||
<pin name="datain_h[0..0]" direction="input" scope="external" />
|
||||
<pin name="datain_l[0..0]" direction="input" scope="external" />
|
||||
<pin name="outclock" direction="input" scope="external" source="clock" />
|
||||
<pin name="dataout[0..0]" direction="output" scope="external" />
|
||||
|
||||
</global>
|
||||
</pinplan>
|
||||
4
FPGA_quartus_GE/altip/altddio_out3.qip
Normal file
4
FPGA_quartus_GE/altip/altddio_out3.qip
Normal file
@@ -0,0 +1,4 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "altddio_out3.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out3.ppf"]
|
||||
107
FPGA_quartus_GE/altip/altddio_out3.v
Normal file
107
FPGA_quartus_GE/altip/altddio_out3.v
Normal file
@@ -0,0 +1,107 @@
|
||||
// megafunction wizard: %ALTDDIO_OUT%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: ALTDDIO_OUT
|
||||
|
||||
// ============================================================
|
||||
// File Name: altddio_out3.v
|
||||
// Megafunction Name(s):
|
||||
// ALTDDIO_OUT
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// altera_mf
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2013 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module altddio_out3 (
|
||||
datain_h,
|
||||
datain_l,
|
||||
outclock,
|
||||
dataout);
|
||||
|
||||
input [0:0] datain_h;
|
||||
input [0:0] datain_l;
|
||||
input outclock;
|
||||
output [0:0] dataout;
|
||||
|
||||
wire [0:0] sub_wire0;
|
||||
wire [0:0] dataout = sub_wire0[0:0];
|
||||
|
||||
altddio_out ALTDDIO_OUT_component (
|
||||
.datain_h (datain_h),
|
||||
.datain_l (datain_l),
|
||||
.outclock (outclock),
|
||||
.dataout (sub_wire0),
|
||||
.aclr (1'b0),
|
||||
.aset (1'b0),
|
||||
.oe (1'b1),
|
||||
.oe_out (),
|
||||
.outclocken (1'b1),
|
||||
.sclr (1'b0),
|
||||
.sset (1'b0));
|
||||
defparam
|
||||
ALTDDIO_OUT_component.extend_oe_disable = "OFF",
|
||||
ALTDDIO_OUT_component.intended_device_family = "Cyclone III",
|
||||
ALTDDIO_OUT_component.invert_output = "OFF",
|
||||
ALTDDIO_OUT_component.lpm_hint = "UNUSED",
|
||||
ALTDDIO_OUT_component.lpm_type = "altddio_out",
|
||||
ALTDDIO_OUT_component.oe_reg = "UNREGISTERED",
|
||||
ALTDDIO_OUT_component.power_up_high = "OFF",
|
||||
ALTDDIO_OUT_component.width = 1;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
|
||||
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
|
||||
// Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED"
|
||||
// Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
|
||||
// Retrieval info: CONSTANT: WIDTH NUMERIC "1"
|
||||
// Retrieval info: USED_PORT: datain_h 0 0 1 0 INPUT NODEFVAL "datain_h[0..0]"
|
||||
// Retrieval info: CONNECT: @datain_h 0 0 1 0 datain_h 0 0 1 0
|
||||
// Retrieval info: USED_PORT: datain_l 0 0 1 0 INPUT NODEFVAL "datain_l[0..0]"
|
||||
// Retrieval info: CONNECT: @datain_l 0 0 1 0 datain_l 0 0 1 0
|
||||
// Retrieval info: USED_PORT: dataout 0 0 1 0 OUTPUT NODEFVAL "dataout[0..0]"
|
||||
// Retrieval info: CONNECT: dataout 0 0 1 0 @dataout 0 0 1 0
|
||||
// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock"
|
||||
// Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.v TRUE FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.qip TRUE FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.bsf FALSE TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3_inst.v FALSE TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3_bb.v FALSE TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.inc FALSE TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.cmp FALSE TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.ppf TRUE FALSE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
3
FPGA_quartus_GE/altip/altdpram0.qip
Normal file
3
FPGA_quartus_GE/altip/altdpram0.qip
Normal file
@@ -0,0 +1,3 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "altdpram0.v"]
|
||||
244
FPGA_quartus_GE/altip/altdpram0.v
Normal file
244
FPGA_quartus_GE/altip/altdpram0.v
Normal file
@@ -0,0 +1,244 @@
|
||||
// megafunction wizard: %RAM: 2-PORT%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: altsyncram
|
||||
|
||||
// ============================================================
|
||||
// File Name: altdpram0.v
|
||||
// Megafunction Name(s):
|
||||
// altsyncram
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// altera_mf
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2013 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module altdpram0 (
|
||||
address_a,
|
||||
address_b,
|
||||
clock_a,
|
||||
clock_b,
|
||||
data_a,
|
||||
data_b,
|
||||
wren_a,
|
||||
wren_b,
|
||||
q_a,
|
||||
q_b);
|
||||
|
||||
input [3:0] address_a;
|
||||
input [3:0] address_b;
|
||||
input clock_a;
|
||||
input clock_b;
|
||||
input [2:0] data_a;
|
||||
input [2:0] data_b;
|
||||
input wren_a;
|
||||
input wren_b;
|
||||
output [2:0] q_a;
|
||||
output [2:0] q_b;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_off
|
||||
`endif
|
||||
tri1 clock_a;
|
||||
tri0 wren_a;
|
||||
tri0 wren_b;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_on
|
||||
`endif
|
||||
|
||||
wire [2:0] sub_wire0;
|
||||
wire [2:0] sub_wire1;
|
||||
wire [2:0] q_a = sub_wire0[2:0];
|
||||
wire [2:0] q_b = sub_wire1[2:0];
|
||||
|
||||
altsyncram altsyncram_component (
|
||||
.clock0 (clock_a),
|
||||
.wren_a (wren_a),
|
||||
.address_b (address_b),
|
||||
.clock1 (clock_b),
|
||||
.data_b (data_b),
|
||||
.wren_b (wren_b),
|
||||
.address_a (address_a),
|
||||
.data_a (data_a),
|
||||
.q_a (sub_wire0),
|
||||
.q_b (sub_wire1),
|
||||
.aclr0 (1'b0),
|
||||
.aclr1 (1'b0),
|
||||
.addressstall_a (1'b0),
|
||||
.addressstall_b (1'b0),
|
||||
.byteena_a (1'b1),
|
||||
.byteena_b (1'b1),
|
||||
.clocken0 (1'b1),
|
||||
.clocken1 (1'b1),
|
||||
.clocken2 (1'b1),
|
||||
.clocken3 (1'b1),
|
||||
.eccstatus (),
|
||||
.rden_a (1'b1),
|
||||
.rden_b (1'b1));
|
||||
defparam
|
||||
altsyncram_component.address_reg_b = "CLOCK1",
|
||||
altsyncram_component.clock_enable_input_a = "BYPASS",
|
||||
altsyncram_component.clock_enable_input_b = "BYPASS",
|
||||
altsyncram_component.clock_enable_output_a = "BYPASS",
|
||||
altsyncram_component.clock_enable_output_b = "BYPASS",
|
||||
altsyncram_component.indata_reg_b = "CLOCK1",
|
||||
altsyncram_component.intended_device_family = "Cyclone III",
|
||||
altsyncram_component.lpm_type = "altsyncram",
|
||||
altsyncram_component.numwords_a = 16,
|
||||
altsyncram_component.numwords_b = 16,
|
||||
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
|
||||
altsyncram_component.outdata_aclr_a = "NONE",
|
||||
altsyncram_component.outdata_aclr_b = "NONE",
|
||||
altsyncram_component.outdata_reg_a = "CLOCK0",
|
||||
altsyncram_component.outdata_reg_b = "CLOCK1",
|
||||
altsyncram_component.power_up_uninitialized = "FALSE",
|
||||
altsyncram_component.read_during_write_mode_port_a = "OLD_DATA",
|
||||
altsyncram_component.read_during_write_mode_port_b = "OLD_DATA",
|
||||
altsyncram_component.widthad_a = 4,
|
||||
altsyncram_component.widthad_b = 4,
|
||||
altsyncram_component.width_a = 3,
|
||||
altsyncram_component.width_b = 3,
|
||||
altsyncram_component.width_byteena_a = 1,
|
||||
altsyncram_component.width_byteena_b = 1,
|
||||
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1";
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
|
||||
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Clock NUMERIC "5"
|
||||
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
|
||||
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
|
||||
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "48"
|
||||
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: MIFfilename STRING ""
|
||||
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
|
||||
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
|
||||
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: REGq NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "3"
|
||||
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "3"
|
||||
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "3"
|
||||
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "3"
|
||||
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: enable NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: rden NUMERIC "0"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
|
||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
|
||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
|
||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
|
||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
|
||||
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
|
||||
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16"
|
||||
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16"
|
||||
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
|
||||
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
|
||||
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
|
||||
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
|
||||
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
|
||||
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
|
||||
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "OLD_DATA"
|
||||
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "OLD_DATA"
|
||||
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "4"
|
||||
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "4"
|
||||
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "3"
|
||||
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "3"
|
||||
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
|
||||
// Retrieval info: USED_PORT: address_a 0 0 4 0 INPUT NODEFVAL "address_a[3..0]"
|
||||
// Retrieval info: USED_PORT: address_b 0 0 4 0 INPUT NODEFVAL "address_b[3..0]"
|
||||
// Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a"
|
||||
// Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b"
|
||||
// Retrieval info: USED_PORT: data_a 0 0 3 0 INPUT NODEFVAL "data_a[2..0]"
|
||||
// Retrieval info: USED_PORT: data_b 0 0 3 0 INPUT NODEFVAL "data_b[2..0]"
|
||||
// Retrieval info: USED_PORT: q_a 0 0 3 0 OUTPUT NODEFVAL "q_a[2..0]"
|
||||
// Retrieval info: USED_PORT: q_b 0 0 3 0 OUTPUT NODEFVAL "q_b[2..0]"
|
||||
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
|
||||
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
|
||||
// Retrieval info: CONNECT: @address_a 0 0 4 0 address_a 0 0 4 0
|
||||
// Retrieval info: CONNECT: @address_b 0 0 4 0 address_b 0 0 4 0
|
||||
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
|
||||
// Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
|
||||
// Retrieval info: CONNECT: @data_a 0 0 3 0 data_a 0 0 3 0
|
||||
// Retrieval info: CONNECT: @data_b 0 0 3 0 data_b 0 0 3 0
|
||||
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
|
||||
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
|
||||
// Retrieval info: CONNECT: q_a 0 0 3 0 @q_a 0 0 3 0
|
||||
// Retrieval info: CONNECT: q_b 0 0 3 0 @q_b 0 0 3 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
3
FPGA_quartus_GE/altip/altdpram1.qip
Normal file
3
FPGA_quartus_GE/altip/altdpram1.qip
Normal file
@@ -0,0 +1,3 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "altdpram1.v"]
|
||||
244
FPGA_quartus_GE/altip/altdpram1.v
Normal file
244
FPGA_quartus_GE/altip/altdpram1.v
Normal file
@@ -0,0 +1,244 @@
|
||||
// megafunction wizard: %RAM: 2-PORT%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: altsyncram
|
||||
|
||||
// ============================================================
|
||||
// File Name: altdpram1.v
|
||||
// Megafunction Name(s):
|
||||
// altsyncram
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// altera_mf
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2013 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module altdpram1 (
|
||||
address_a,
|
||||
address_b,
|
||||
clock_a,
|
||||
clock_b,
|
||||
data_a,
|
||||
data_b,
|
||||
wren_a,
|
||||
wren_b,
|
||||
q_a,
|
||||
q_b);
|
||||
|
||||
input [7:0] address_a;
|
||||
input [7:0] address_b;
|
||||
input clock_a;
|
||||
input clock_b;
|
||||
input [5:0] data_a;
|
||||
input [5:0] data_b;
|
||||
input wren_a;
|
||||
input wren_b;
|
||||
output [5:0] q_a;
|
||||
output [5:0] q_b;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_off
|
||||
`endif
|
||||
tri1 clock_a;
|
||||
tri0 wren_a;
|
||||
tri0 wren_b;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_on
|
||||
`endif
|
||||
|
||||
wire [5:0] sub_wire0;
|
||||
wire [5:0] sub_wire1;
|
||||
wire [5:0] q_a = sub_wire0[5:0];
|
||||
wire [5:0] q_b = sub_wire1[5:0];
|
||||
|
||||
altsyncram altsyncram_component (
|
||||
.clock0 (clock_a),
|
||||
.wren_a (wren_a),
|
||||
.address_b (address_b),
|
||||
.clock1 (clock_b),
|
||||
.data_b (data_b),
|
||||
.wren_b (wren_b),
|
||||
.address_a (address_a),
|
||||
.data_a (data_a),
|
||||
.q_a (sub_wire0),
|
||||
.q_b (sub_wire1),
|
||||
.aclr0 (1'b0),
|
||||
.aclr1 (1'b0),
|
||||
.addressstall_a (1'b0),
|
||||
.addressstall_b (1'b0),
|
||||
.byteena_a (1'b1),
|
||||
.byteena_b (1'b1),
|
||||
.clocken0 (1'b1),
|
||||
.clocken1 (1'b1),
|
||||
.clocken2 (1'b1),
|
||||
.clocken3 (1'b1),
|
||||
.eccstatus (),
|
||||
.rden_a (1'b1),
|
||||
.rden_b (1'b1));
|
||||
defparam
|
||||
altsyncram_component.address_reg_b = "CLOCK1",
|
||||
altsyncram_component.clock_enable_input_a = "BYPASS",
|
||||
altsyncram_component.clock_enable_input_b = "BYPASS",
|
||||
altsyncram_component.clock_enable_output_a = "BYPASS",
|
||||
altsyncram_component.clock_enable_output_b = "BYPASS",
|
||||
altsyncram_component.indata_reg_b = "CLOCK1",
|
||||
altsyncram_component.intended_device_family = "Cyclone III",
|
||||
altsyncram_component.lpm_type = "altsyncram",
|
||||
altsyncram_component.numwords_a = 256,
|
||||
altsyncram_component.numwords_b = 256,
|
||||
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
|
||||
altsyncram_component.outdata_aclr_a = "NONE",
|
||||
altsyncram_component.outdata_aclr_b = "NONE",
|
||||
altsyncram_component.outdata_reg_a = "CLOCK0",
|
||||
altsyncram_component.outdata_reg_b = "CLOCK1",
|
||||
altsyncram_component.power_up_uninitialized = "FALSE",
|
||||
altsyncram_component.read_during_write_mode_port_a = "OLD_DATA",
|
||||
altsyncram_component.read_during_write_mode_port_b = "OLD_DATA",
|
||||
altsyncram_component.widthad_a = 8,
|
||||
altsyncram_component.widthad_b = 8,
|
||||
altsyncram_component.width_a = 6,
|
||||
altsyncram_component.width_b = 6,
|
||||
altsyncram_component.width_byteena_a = 1,
|
||||
altsyncram_component.width_byteena_b = 1,
|
||||
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1";
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
|
||||
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Clock NUMERIC "5"
|
||||
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
|
||||
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
|
||||
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "1536"
|
||||
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: MIFfilename STRING ""
|
||||
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
|
||||
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
|
||||
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: REGq NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "6"
|
||||
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "6"
|
||||
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "6"
|
||||
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "6"
|
||||
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: enable NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: rden NUMERIC "0"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
|
||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
|
||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
|
||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
|
||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
|
||||
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
|
||||
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
|
||||
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256"
|
||||
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
|
||||
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
|
||||
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
|
||||
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
|
||||
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
|
||||
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
|
||||
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "OLD_DATA"
|
||||
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "OLD_DATA"
|
||||
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
|
||||
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8"
|
||||
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "6"
|
||||
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "6"
|
||||
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
|
||||
// Retrieval info: USED_PORT: address_a 0 0 8 0 INPUT NODEFVAL "address_a[7..0]"
|
||||
// Retrieval info: USED_PORT: address_b 0 0 8 0 INPUT NODEFVAL "address_b[7..0]"
|
||||
// Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a"
|
||||
// Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b"
|
||||
// Retrieval info: USED_PORT: data_a 0 0 6 0 INPUT NODEFVAL "data_a[5..0]"
|
||||
// Retrieval info: USED_PORT: data_b 0 0 6 0 INPUT NODEFVAL "data_b[5..0]"
|
||||
// Retrieval info: USED_PORT: q_a 0 0 6 0 OUTPUT NODEFVAL "q_a[5..0]"
|
||||
// Retrieval info: USED_PORT: q_b 0 0 6 0 OUTPUT NODEFVAL "q_b[5..0]"
|
||||
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
|
||||
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
|
||||
// Retrieval info: CONNECT: @address_a 0 0 8 0 address_a 0 0 8 0
|
||||
// Retrieval info: CONNECT: @address_b 0 0 8 0 address_b 0 0 8 0
|
||||
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
|
||||
// Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
|
||||
// Retrieval info: CONNECT: @data_a 0 0 6 0 data_a 0 0 6 0
|
||||
// Retrieval info: CONNECT: @data_b 0 0 6 0 data_b 0 0 6 0
|
||||
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
|
||||
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
|
||||
// Retrieval info: CONNECT: q_a 0 0 6 0 @q_a 0 0 6 0
|
||||
// Retrieval info: CONNECT: q_b 0 0 6 0 @q_b 0 0 6 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
3
FPGA_quartus_GE/altip/altdpram2.qip
Normal file
3
FPGA_quartus_GE/altip/altdpram2.qip
Normal file
@@ -0,0 +1,3 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "altdpram2.v"]
|
||||
244
FPGA_quartus_GE/altip/altdpram2.v
Normal file
244
FPGA_quartus_GE/altip/altdpram2.v
Normal file
@@ -0,0 +1,244 @@
|
||||
// megafunction wizard: %RAM: 2-PORT%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: altsyncram
|
||||
|
||||
// ============================================================
|
||||
// File Name: altdpram2.v
|
||||
// Megafunction Name(s):
|
||||
// altsyncram
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// altera_mf
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2013 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module altdpram2 (
|
||||
address_a,
|
||||
address_b,
|
||||
clock_a,
|
||||
clock_b,
|
||||
data_a,
|
||||
data_b,
|
||||
wren_a,
|
||||
wren_b,
|
||||
q_a,
|
||||
q_b);
|
||||
|
||||
input [7:0] address_a;
|
||||
input [7:0] address_b;
|
||||
input clock_a;
|
||||
input clock_b;
|
||||
input [7:0] data_a;
|
||||
input [7:0] data_b;
|
||||
input wren_a;
|
||||
input wren_b;
|
||||
output [7:0] q_a;
|
||||
output [7:0] q_b;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_off
|
||||
`endif
|
||||
tri1 clock_a;
|
||||
tri0 wren_a;
|
||||
tri0 wren_b;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_on
|
||||
`endif
|
||||
|
||||
wire [7:0] sub_wire0;
|
||||
wire [7:0] sub_wire1;
|
||||
wire [7:0] q_a = sub_wire0[7:0];
|
||||
wire [7:0] q_b = sub_wire1[7:0];
|
||||
|
||||
altsyncram altsyncram_component (
|
||||
.clock0 (clock_a),
|
||||
.wren_a (wren_a),
|
||||
.address_b (address_b),
|
||||
.clock1 (clock_b),
|
||||
.data_b (data_b),
|
||||
.wren_b (wren_b),
|
||||
.address_a (address_a),
|
||||
.data_a (data_a),
|
||||
.q_a (sub_wire0),
|
||||
.q_b (sub_wire1),
|
||||
.aclr0 (1'b0),
|
||||
.aclr1 (1'b0),
|
||||
.addressstall_a (1'b0),
|
||||
.addressstall_b (1'b0),
|
||||
.byteena_a (1'b1),
|
||||
.byteena_b (1'b1),
|
||||
.clocken0 (1'b1),
|
||||
.clocken1 (1'b1),
|
||||
.clocken2 (1'b1),
|
||||
.clocken3 (1'b1),
|
||||
.eccstatus (),
|
||||
.rden_a (1'b1),
|
||||
.rden_b (1'b1));
|
||||
defparam
|
||||
altsyncram_component.address_reg_b = "CLOCK1",
|
||||
altsyncram_component.clock_enable_input_a = "BYPASS",
|
||||
altsyncram_component.clock_enable_input_b = "BYPASS",
|
||||
altsyncram_component.clock_enable_output_a = "BYPASS",
|
||||
altsyncram_component.clock_enable_output_b = "BYPASS",
|
||||
altsyncram_component.indata_reg_b = "CLOCK1",
|
||||
altsyncram_component.intended_device_family = "Cyclone III",
|
||||
altsyncram_component.lpm_type = "altsyncram",
|
||||
altsyncram_component.numwords_a = 256,
|
||||
altsyncram_component.numwords_b = 256,
|
||||
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
|
||||
altsyncram_component.outdata_aclr_a = "NONE",
|
||||
altsyncram_component.outdata_aclr_b = "NONE",
|
||||
altsyncram_component.outdata_reg_a = "CLOCK0",
|
||||
altsyncram_component.outdata_reg_b = "CLOCK1",
|
||||
altsyncram_component.power_up_uninitialized = "FALSE",
|
||||
altsyncram_component.read_during_write_mode_port_a = "OLD_DATA",
|
||||
altsyncram_component.read_during_write_mode_port_b = "OLD_DATA",
|
||||
altsyncram_component.widthad_a = 8,
|
||||
altsyncram_component.widthad_b = 8,
|
||||
altsyncram_component.width_a = 8,
|
||||
altsyncram_component.width_b = 8,
|
||||
altsyncram_component.width_byteena_a = 1,
|
||||
altsyncram_component.width_byteena_b = 1,
|
||||
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1";
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
|
||||
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Clock NUMERIC "5"
|
||||
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
|
||||
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
|
||||
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "2048"
|
||||
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: MIFfilename STRING ""
|
||||
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
|
||||
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
|
||||
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: REGq NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
|
||||
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
|
||||
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
|
||||
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
|
||||
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: enable NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: rden NUMERIC "0"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
|
||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
|
||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
|
||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
|
||||
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
|
||||
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
|
||||
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
|
||||
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256"
|
||||
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
|
||||
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
|
||||
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
|
||||
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
|
||||
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
|
||||
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
|
||||
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "OLD_DATA"
|
||||
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "OLD_DATA"
|
||||
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
|
||||
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8"
|
||||
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
|
||||
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
|
||||
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
|
||||
// Retrieval info: USED_PORT: address_a 0 0 8 0 INPUT NODEFVAL "address_a[7..0]"
|
||||
// Retrieval info: USED_PORT: address_b 0 0 8 0 INPUT NODEFVAL "address_b[7..0]"
|
||||
// Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a"
|
||||
// Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b"
|
||||
// Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL "data_a[7..0]"
|
||||
// Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL "data_b[7..0]"
|
||||
// Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL "q_a[7..0]"
|
||||
// Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL "q_b[7..0]"
|
||||
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
|
||||
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
|
||||
// Retrieval info: CONNECT: @address_a 0 0 8 0 address_a 0 0 8 0
|
||||
// Retrieval info: CONNECT: @address_b 0 0 8 0 address_b 0 0 8 0
|
||||
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
|
||||
// Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
|
||||
// Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0
|
||||
// Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0
|
||||
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
|
||||
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
|
||||
// Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0
|
||||
// Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
13
FPGA_quartus_GE/altip/altpll0.ppf
Normal file
13
FPGA_quartus_GE/altip/altpll0.ppf
Normal file
@@ -0,0 +1,13 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<!DOCTYPE pinplan>
|
||||
<pinplan intended_family="Cyclone III" variation_name="altpll0" megafunction_name="ALTPLL" specifies="all_ports">
|
||||
<global>
|
||||
<pin name="inclk0" direction="input" scope="external" source="clock" />
|
||||
<pin name="c0" direction="output" scope="external" source="clock" />
|
||||
<pin name="c1" direction="output" scope="external" source="clock" />
|
||||
<pin name="c2" direction="output" scope="external" source="clock" />
|
||||
<pin name="c3" direction="output" scope="external" source="clock" />
|
||||
<pin name="c4" direction="output" scope="external" source="clock" />
|
||||
|
||||
</global>
|
||||
</pinplan>
|
||||
4
FPGA_quartus_GE/altip/altpll0.qip
Normal file
4
FPGA_quartus_GE/altip/altpll0.qip
Normal file
@@ -0,0 +1,4 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "altpll0.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll0.ppf"]
|
||||
411
FPGA_quartus_GE/altip/altpll0.v
Normal file
411
FPGA_quartus_GE/altip/altpll0.v
Normal file
@@ -0,0 +1,411 @@
|
||||
// megafunction wizard: %ALTPLL%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: altpll
|
||||
|
||||
// ============================================================
|
||||
// File Name: altpll0.v
|
||||
// Megafunction Name(s):
|
||||
// altpll
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// altera_mf
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2013 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module altpll0 (
|
||||
inclk0,
|
||||
c0,
|
||||
c1,
|
||||
c2,
|
||||
c3,
|
||||
c4);
|
||||
|
||||
input inclk0;
|
||||
output c0;
|
||||
output c1;
|
||||
output c2;
|
||||
output c3;
|
||||
output c4;
|
||||
|
||||
wire [4:0] sub_wire0;
|
||||
wire [0:0] sub_wire8 = 1'h0;
|
||||
wire [4:4] sub_wire5 = sub_wire0[4:4];
|
||||
wire [2:2] sub_wire4 = sub_wire0[2:2];
|
||||
wire [0:0] sub_wire3 = sub_wire0[0:0];
|
||||
wire [3:3] sub_wire2 = sub_wire0[3:3];
|
||||
wire [1:1] sub_wire1 = sub_wire0[1:1];
|
||||
wire c1 = sub_wire1;
|
||||
wire c3 = sub_wire2;
|
||||
wire c0 = sub_wire3;
|
||||
wire c2 = sub_wire4;
|
||||
wire c4 = sub_wire5;
|
||||
wire sub_wire6 = inclk0;
|
||||
wire [1:0] sub_wire7 = {sub_wire8, sub_wire6};
|
||||
|
||||
altpll altpll_component (
|
||||
.inclk (sub_wire7),
|
||||
.clk (sub_wire0),
|
||||
.activeclock (),
|
||||
.areset (1'b0),
|
||||
.clkbad (),
|
||||
.clkena ({6{1'b1}}),
|
||||
.clkloss (),
|
||||
.clkswitch (1'b0),
|
||||
.configupdate (1'b0),
|
||||
.enable0 (),
|
||||
.enable1 (),
|
||||
.extclk (),
|
||||
.extclkena ({4{1'b1}}),
|
||||
.fbin (1'b1),
|
||||
.fbmimicbidir (),
|
||||
.fbout (),
|
||||
.fref (),
|
||||
.icdrclk (),
|
||||
.locked (),
|
||||
.pfdena (1'b1),
|
||||
.phasecounterselect ({4{1'b1}}),
|
||||
.phasedone (),
|
||||
.phasestep (1'b1),
|
||||
.phaseupdown (1'b1),
|
||||
.pllena (1'b1),
|
||||
.scanaclr (1'b0),
|
||||
.scanclk (1'b0),
|
||||
.scanclkena (1'b1),
|
||||
.scandata (1'b0),
|
||||
.scandataout (),
|
||||
.scandone (),
|
||||
.scanread (1'b0),
|
||||
.scanwrite (1'b0),
|
||||
.sclkout0 (),
|
||||
.sclkout1 (),
|
||||
.vcooverrange (),
|
||||
.vcounderrange ());
|
||||
defparam
|
||||
altpll_component.bandwidth_type = "AUTO",
|
||||
altpll_component.clk0_divide_by = 11,
|
||||
altpll_component.clk0_duty_cycle = 50,
|
||||
altpll_component.clk0_multiply_by = 16,
|
||||
altpll_component.clk0_phase_shift = "0",
|
||||
altpll_component.clk1_divide_by = 11,
|
||||
altpll_component.clk1_duty_cycle = 50,
|
||||
altpll_component.clk1_multiply_by = 50,
|
||||
altpll_component.clk1_phase_shift = "0",
|
||||
altpll_component.clk2_divide_by = 11,
|
||||
altpll_component.clk2_duty_cycle = 50,
|
||||
altpll_component.clk2_multiply_by = 40,
|
||||
altpll_component.clk2_phase_shift = "0",
|
||||
altpll_component.clk3_divide_by = 33,
|
||||
altpll_component.clk3_duty_cycle = 50,
|
||||
altpll_component.clk3_multiply_by = 109,
|
||||
altpll_component.clk3_phase_shift = "0",
|
||||
altpll_component.clk4_divide_by = 39,
|
||||
altpll_component.clk4_duty_cycle = 50,
|
||||
altpll_component.clk4_multiply_by = 109,
|
||||
altpll_component.clk4_phase_shift = "0",
|
||||
altpll_component.compensate_clock = "CLK0",
|
||||
altpll_component.inclk0_input_frequency = 30303,
|
||||
altpll_component.intended_device_family = "Cyclone III",
|
||||
altpll_component.lpm_type = "altpll",
|
||||
altpll_component.operation_mode = "NORMAL",
|
||||
altpll_component.pll_type = "AUTO",
|
||||
altpll_component.port_activeclock = "PORT_UNUSED",
|
||||
altpll_component.port_areset = "PORT_UNUSED",
|
||||
altpll_component.port_clkbad0 = "PORT_UNUSED",
|
||||
altpll_component.port_clkbad1 = "PORT_UNUSED",
|
||||
altpll_component.port_clkloss = "PORT_UNUSED",
|
||||
altpll_component.port_clkswitch = "PORT_UNUSED",
|
||||
altpll_component.port_configupdate = "PORT_UNUSED",
|
||||
altpll_component.port_fbin = "PORT_UNUSED",
|
||||
altpll_component.port_inclk0 = "PORT_USED",
|
||||
altpll_component.port_inclk1 = "PORT_UNUSED",
|
||||
altpll_component.port_locked = "PORT_UNUSED",
|
||||
altpll_component.port_pfdena = "PORT_UNUSED",
|
||||
altpll_component.port_phasecounterselect = "PORT_UNUSED",
|
||||
altpll_component.port_phasedone = "PORT_UNUSED",
|
||||
altpll_component.port_phasestep = "PORT_UNUSED",
|
||||
altpll_component.port_phaseupdown = "PORT_UNUSED",
|
||||
altpll_component.port_pllena = "PORT_UNUSED",
|
||||
altpll_component.port_scanaclr = "PORT_UNUSED",
|
||||
altpll_component.port_scanclk = "PORT_UNUSED",
|
||||
altpll_component.port_scanclkena = "PORT_UNUSED",
|
||||
altpll_component.port_scandata = "PORT_UNUSED",
|
||||
altpll_component.port_scandataout = "PORT_UNUSED",
|
||||
altpll_component.port_scandone = "PORT_UNUSED",
|
||||
altpll_component.port_scanread = "PORT_UNUSED",
|
||||
altpll_component.port_scanwrite = "PORT_UNUSED",
|
||||
altpll_component.port_clk0 = "PORT_USED",
|
||||
altpll_component.port_clk1 = "PORT_USED",
|
||||
altpll_component.port_clk2 = "PORT_USED",
|
||||
altpll_component.port_clk3 = "PORT_USED",
|
||||
altpll_component.port_clk4 = "PORT_USED",
|
||||
altpll_component.port_clk5 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena0 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena1 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena2 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena3 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena4 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena5 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk0 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk1 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk2 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk3 = "PORT_UNUSED",
|
||||
altpll_component.width_clock = 5;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
|
||||
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
|
||||
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "75"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "33"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "36"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "39"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "39"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "150.000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "120.000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "109.000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "92.230766"
|
||||
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||||
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
|
||||
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.000"
|
||||
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "ps"
|
||||
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "109"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "109"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "109"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "109"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "109"
|
||||
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "150.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "120.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "109.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "92.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "ps"
|
||||
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
|
||||
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll0.mif"
|
||||
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
|
||||
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
|
||||
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
|
||||
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
|
||||
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK4 STRING "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLK3 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLK4 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA4 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
|
||||
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "11"
|
||||
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "16"
|
||||
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "11"
|
||||
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "11"
|
||||
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "40"
|
||||
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "33"
|
||||
// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "109"
|
||||
// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "39"
|
||||
// Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "109"
|
||||
// Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
|
||||
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
|
||||
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
|
||||
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
|
||||
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
|
||||
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||||
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
|
||||
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
|
||||
// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
|
||||
// Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
|
||||
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
||||
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
|
||||
// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
|
||||
// Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.ppf TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll0_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
12
FPGA_quartus_GE/altip/altpll1.ppf
Normal file
12
FPGA_quartus_GE/altip/altpll1.ppf
Normal file
@@ -0,0 +1,12 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<!DOCTYPE pinplan>
|
||||
<pinplan intended_family="Cyclone III" variation_name="altpll1" megafunction_name="ALTPLL" specifies="all_ports">
|
||||
<global>
|
||||
<pin name="inclk0" direction="input" scope="external" source="clock" />
|
||||
<pin name="c0" direction="output" scope="external" source="clock" />
|
||||
<pin name="c1" direction="output" scope="external" source="clock" />
|
||||
<pin name="c2" direction="output" scope="external" source="clock" />
|
||||
<pin name="locked" direction="output" scope="external" />
|
||||
|
||||
</global>
|
||||
</pinplan>
|
||||
4
FPGA_quartus_GE/altip/altpll1.qip
Normal file
4
FPGA_quartus_GE/altip/altpll1.qip
Normal file
@@ -0,0 +1,4 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "altpll1.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.ppf"]
|
||||
363
FPGA_quartus_GE/altip/altpll1.v
Normal file
363
FPGA_quartus_GE/altip/altpll1.v
Normal file
@@ -0,0 +1,363 @@
|
||||
// megafunction wizard: %ALTPLL%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: altpll
|
||||
|
||||
// ============================================================
|
||||
// File Name: altpll1.v
|
||||
// Megafunction Name(s):
|
||||
// altpll
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// altera_mf
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2013 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module altpll1 (
|
||||
inclk0,
|
||||
c0,
|
||||
c1,
|
||||
c2,
|
||||
locked);
|
||||
|
||||
input inclk0;
|
||||
output c0;
|
||||
output c1;
|
||||
output c2;
|
||||
output locked;
|
||||
|
||||
wire [4:0] sub_wire0;
|
||||
wire sub_wire2;
|
||||
wire [0:0] sub_wire7 = 1'h0;
|
||||
wire [2:2] sub_wire4 = sub_wire0[2:2];
|
||||
wire [0:0] sub_wire3 = sub_wire0[0:0];
|
||||
wire [1:1] sub_wire1 = sub_wire0[1:1];
|
||||
wire c1 = sub_wire1;
|
||||
wire locked = sub_wire2;
|
||||
wire c0 = sub_wire3;
|
||||
wire c2 = sub_wire4;
|
||||
wire sub_wire5 = inclk0;
|
||||
wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
|
||||
|
||||
altpll altpll_component (
|
||||
.inclk (sub_wire6),
|
||||
.clk (sub_wire0),
|
||||
.locked (sub_wire2),
|
||||
.activeclock (),
|
||||
.areset (1'b0),
|
||||
.clkbad (),
|
||||
.clkena ({6{1'b1}}),
|
||||
.clkloss (),
|
||||
.clkswitch (1'b0),
|
||||
.configupdate (1'b0),
|
||||
.enable0 (),
|
||||
.enable1 (),
|
||||
.extclk (),
|
||||
.extclkena ({4{1'b1}}),
|
||||
.fbin (1'b1),
|
||||
.fbmimicbidir (),
|
||||
.fbout (),
|
||||
.fref (),
|
||||
.icdrclk (),
|
||||
.pfdena (1'b1),
|
||||
.phasecounterselect ({4{1'b1}}),
|
||||
.phasedone (),
|
||||
.phasestep (1'b1),
|
||||
.phaseupdown (1'b1),
|
||||
.pllena (1'b1),
|
||||
.scanaclr (1'b0),
|
||||
.scanclk (1'b0),
|
||||
.scanclkena (1'b1),
|
||||
.scandata (1'b0),
|
||||
.scandataout (),
|
||||
.scandone (),
|
||||
.scanread (1'b0),
|
||||
.scanwrite (1'b0),
|
||||
.sclkout0 (),
|
||||
.sclkout1 (),
|
||||
.vcooverrange (),
|
||||
.vcounderrange ());
|
||||
defparam
|
||||
altpll_component.bandwidth_type = "AUTO",
|
||||
altpll_component.clk0_divide_by = 66,
|
||||
altpll_component.clk0_duty_cycle = 50,
|
||||
altpll_component.clk0_multiply_by = 1,
|
||||
altpll_component.clk0_phase_shift = "0",
|
||||
altpll_component.clk1_divide_by = 900,
|
||||
altpll_component.clk1_duty_cycle = 50,
|
||||
altpll_component.clk1_multiply_by = 67,
|
||||
altpll_component.clk1_phase_shift = "0",
|
||||
altpll_component.clk2_divide_by = 90,
|
||||
altpll_component.clk2_duty_cycle = 50,
|
||||
altpll_component.clk2_multiply_by = 67,
|
||||
altpll_component.clk2_phase_shift = "0",
|
||||
altpll_component.compensate_clock = "CLK0",
|
||||
altpll_component.inclk0_input_frequency = 30303,
|
||||
altpll_component.intended_device_family = "Cyclone III",
|
||||
altpll_component.lpm_type = "altpll",
|
||||
altpll_component.operation_mode = "SOURCE_SYNCHRONOUS",
|
||||
altpll_component.pll_type = "AUTO",
|
||||
altpll_component.port_activeclock = "PORT_UNUSED",
|
||||
altpll_component.port_areset = "PORT_UNUSED",
|
||||
altpll_component.port_clkbad0 = "PORT_UNUSED",
|
||||
altpll_component.port_clkbad1 = "PORT_UNUSED",
|
||||
altpll_component.port_clkloss = "PORT_UNUSED",
|
||||
altpll_component.port_clkswitch = "PORT_UNUSED",
|
||||
altpll_component.port_configupdate = "PORT_UNUSED",
|
||||
altpll_component.port_fbin = "PORT_UNUSED",
|
||||
altpll_component.port_inclk0 = "PORT_USED",
|
||||
altpll_component.port_inclk1 = "PORT_UNUSED",
|
||||
altpll_component.port_locked = "PORT_USED",
|
||||
altpll_component.port_pfdena = "PORT_UNUSED",
|
||||
altpll_component.port_phasecounterselect = "PORT_UNUSED",
|
||||
altpll_component.port_phasedone = "PORT_UNUSED",
|
||||
altpll_component.port_phasestep = "PORT_UNUSED",
|
||||
altpll_component.port_phaseupdown = "PORT_UNUSED",
|
||||
altpll_component.port_pllena = "PORT_UNUSED",
|
||||
altpll_component.port_scanaclr = "PORT_UNUSED",
|
||||
altpll_component.port_scanclk = "PORT_UNUSED",
|
||||
altpll_component.port_scanclkena = "PORT_UNUSED",
|
||||
altpll_component.port_scandata = "PORT_UNUSED",
|
||||
altpll_component.port_scandataout = "PORT_UNUSED",
|
||||
altpll_component.port_scandone = "PORT_UNUSED",
|
||||
altpll_component.port_scanread = "PORT_UNUSED",
|
||||
altpll_component.port_scanwrite = "PORT_UNUSED",
|
||||
altpll_component.port_clk0 = "PORT_USED",
|
||||
altpll_component.port_clk1 = "PORT_USED",
|
||||
altpll_component.port_clk2 = "PORT_USED",
|
||||
altpll_component.port_clk3 = "PORT_UNUSED",
|
||||
altpll_component.port_clk4 = "PORT_UNUSED",
|
||||
altpll_component.port_clk5 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena0 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena1 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena2 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena3 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena4 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena5 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk0 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk1 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk2 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk3 = "PORT_UNUSED",
|
||||
altpll_component.self_reset_on_loss_lock = "OFF",
|
||||
altpll_component.width_clock = 5;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
|
||||
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
|
||||
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "90"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "900"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "90"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "0.500000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "2.456667"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "24.566668"
|
||||
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||||
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
|
||||
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.000"
|
||||
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
|
||||
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
|
||||
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "67"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "67"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "67"
|
||||
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "0.50000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "2.45760000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "24.57600000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
|
||||
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll1.mif"
|
||||
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
|
||||
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
|
||||
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
|
||||
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
|
||||
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
|
||||
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "66"
|
||||
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "900"
|
||||
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "67"
|
||||
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "90"
|
||||
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "67"
|
||||
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
|
||||
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS"
|
||||
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
|
||||
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
|
||||
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
|
||||
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
|
||||
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||||
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
|
||||
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
|
||||
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
||||
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
|
||||
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.ppf TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
13
FPGA_quartus_GE/altip/altpll2.ppf
Normal file
13
FPGA_quartus_GE/altip/altpll2.ppf
Normal file
@@ -0,0 +1,13 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<!DOCTYPE pinplan>
|
||||
<pinplan intended_family="Cyclone III" variation_name="altpll2" megafunction_name="ALTPLL" specifies="all_ports">
|
||||
<global>
|
||||
<pin name="inclk0" direction="input" scope="external" source="clock" />
|
||||
<pin name="c0" direction="output" scope="external" source="clock" />
|
||||
<pin name="c1" direction="output" scope="external" source="clock" />
|
||||
<pin name="c2" direction="output" scope="external" source="clock" />
|
||||
<pin name="c3" direction="output" scope="external" source="clock" />
|
||||
<pin name="c4" direction="output" scope="external" source="clock" />
|
||||
|
||||
</global>
|
||||
</pinplan>
|
||||
4
FPGA_quartus_GE/altip/altpll2.qip
Normal file
4
FPGA_quartus_GE/altip/altpll2.qip
Normal file
@@ -0,0 +1,4 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "altpll2.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.ppf"]
|
||||
411
FPGA_quartus_GE/altip/altpll2.v
Normal file
411
FPGA_quartus_GE/altip/altpll2.v
Normal file
@@ -0,0 +1,411 @@
|
||||
// megafunction wizard: %ALTPLL%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: altpll
|
||||
|
||||
// ============================================================
|
||||
// File Name: altpll2.v
|
||||
// Megafunction Name(s):
|
||||
// altpll
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// altera_mf
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2013 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module altpll2 (
|
||||
inclk0,
|
||||
c0,
|
||||
c1,
|
||||
c2,
|
||||
c3,
|
||||
c4);
|
||||
|
||||
input inclk0;
|
||||
output c0;
|
||||
output c1;
|
||||
output c2;
|
||||
output c3;
|
||||
output c4;
|
||||
|
||||
wire [4:0] sub_wire0;
|
||||
wire [0:0] sub_wire8 = 1'h0;
|
||||
wire [4:4] sub_wire5 = sub_wire0[4:4];
|
||||
wire [2:2] sub_wire4 = sub_wire0[2:2];
|
||||
wire [0:0] sub_wire3 = sub_wire0[0:0];
|
||||
wire [3:3] sub_wire2 = sub_wire0[3:3];
|
||||
wire [1:1] sub_wire1 = sub_wire0[1:1];
|
||||
wire c1 = sub_wire1;
|
||||
wire c3 = sub_wire2;
|
||||
wire c0 = sub_wire3;
|
||||
wire c2 = sub_wire4;
|
||||
wire c4 = sub_wire5;
|
||||
wire sub_wire6 = inclk0;
|
||||
wire [1:0] sub_wire7 = {sub_wire8, sub_wire6};
|
||||
|
||||
altpll altpll_component (
|
||||
.inclk (sub_wire7),
|
||||
.clk (sub_wire0),
|
||||
.activeclock (),
|
||||
.areset (1'b0),
|
||||
.clkbad (),
|
||||
.clkena ({6{1'b1}}),
|
||||
.clkloss (),
|
||||
.clkswitch (1'b0),
|
||||
.configupdate (1'b0),
|
||||
.enable0 (),
|
||||
.enable1 (),
|
||||
.extclk (),
|
||||
.extclkena ({4{1'b1}}),
|
||||
.fbin (1'b1),
|
||||
.fbmimicbidir (),
|
||||
.fbout (),
|
||||
.fref (),
|
||||
.icdrclk (),
|
||||
.locked (),
|
||||
.pfdena (1'b1),
|
||||
.phasecounterselect ({4{1'b1}}),
|
||||
.phasedone (),
|
||||
.phasestep (1'b1),
|
||||
.phaseupdown (1'b1),
|
||||
.pllena (1'b1),
|
||||
.scanaclr (1'b0),
|
||||
.scanclk (1'b0),
|
||||
.scanclkena (1'b1),
|
||||
.scandata (1'b0),
|
||||
.scandataout (),
|
||||
.scandone (),
|
||||
.scanread (1'b0),
|
||||
.scanwrite (1'b0),
|
||||
.sclkout0 (),
|
||||
.sclkout1 (),
|
||||
.vcooverrange (),
|
||||
.vcounderrange ());
|
||||
defparam
|
||||
altpll_component.bandwidth_type = "AUTO",
|
||||
altpll_component.clk0_divide_by = 1,
|
||||
altpll_component.clk0_duty_cycle = 50,
|
||||
altpll_component.clk0_multiply_by = 4,
|
||||
altpll_component.clk0_phase_shift = "5051",
|
||||
altpll_component.clk1_divide_by = 1,
|
||||
altpll_component.clk1_duty_cycle = 50,
|
||||
altpll_component.clk1_multiply_by = 4,
|
||||
altpll_component.clk1_phase_shift = "0",
|
||||
altpll_component.clk2_divide_by = 1,
|
||||
altpll_component.clk2_duty_cycle = 50,
|
||||
altpll_component.clk2_multiply_by = 4,
|
||||
altpll_component.clk2_phase_shift = "3788",
|
||||
altpll_component.clk3_divide_by = 1,
|
||||
altpll_component.clk3_duty_cycle = 50,
|
||||
altpll_component.clk3_multiply_by = 4,
|
||||
altpll_component.clk3_phase_shift = "2210",
|
||||
altpll_component.clk4_divide_by = 1,
|
||||
altpll_component.clk4_duty_cycle = 50,
|
||||
altpll_component.clk4_multiply_by = 2,
|
||||
altpll_component.clk4_phase_shift = "11364",
|
||||
altpll_component.compensate_clock = "CLK0",
|
||||
altpll_component.inclk0_input_frequency = 30303,
|
||||
altpll_component.intended_device_family = "Cyclone III",
|
||||
altpll_component.lpm_type = "altpll",
|
||||
altpll_component.operation_mode = "SOURCE_SYNCHRONOUS",
|
||||
altpll_component.pll_type = "AUTO",
|
||||
altpll_component.port_activeclock = "PORT_UNUSED",
|
||||
altpll_component.port_areset = "PORT_UNUSED",
|
||||
altpll_component.port_clkbad0 = "PORT_UNUSED",
|
||||
altpll_component.port_clkbad1 = "PORT_UNUSED",
|
||||
altpll_component.port_clkloss = "PORT_UNUSED",
|
||||
altpll_component.port_clkswitch = "PORT_UNUSED",
|
||||
altpll_component.port_configupdate = "PORT_UNUSED",
|
||||
altpll_component.port_fbin = "PORT_UNUSED",
|
||||
altpll_component.port_inclk0 = "PORT_USED",
|
||||
altpll_component.port_inclk1 = "PORT_UNUSED",
|
||||
altpll_component.port_locked = "PORT_UNUSED",
|
||||
altpll_component.port_pfdena = "PORT_UNUSED",
|
||||
altpll_component.port_phasecounterselect = "PORT_UNUSED",
|
||||
altpll_component.port_phasedone = "PORT_UNUSED",
|
||||
altpll_component.port_phasestep = "PORT_UNUSED",
|
||||
altpll_component.port_phaseupdown = "PORT_UNUSED",
|
||||
altpll_component.port_pllena = "PORT_UNUSED",
|
||||
altpll_component.port_scanaclr = "PORT_UNUSED",
|
||||
altpll_component.port_scanclk = "PORT_UNUSED",
|
||||
altpll_component.port_scanclkena = "PORT_UNUSED",
|
||||
altpll_component.port_scandata = "PORT_UNUSED",
|
||||
altpll_component.port_scandataout = "PORT_UNUSED",
|
||||
altpll_component.port_scandone = "PORT_UNUSED",
|
||||
altpll_component.port_scanread = "PORT_UNUSED",
|
||||
altpll_component.port_scanwrite = "PORT_UNUSED",
|
||||
altpll_component.port_clk0 = "PORT_USED",
|
||||
altpll_component.port_clk1 = "PORT_USED",
|
||||
altpll_component.port_clk2 = "PORT_USED",
|
||||
altpll_component.port_clk3 = "PORT_USED",
|
||||
altpll_component.port_clk4 = "PORT_USED",
|
||||
altpll_component.port_clk5 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena0 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena1 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena2 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena3 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena4 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena5 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk0 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk1 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk2 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk3 = "PORT_UNUSED",
|
||||
altpll_component.width_clock = 5;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
|
||||
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
|
||||
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "132.000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "132.000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "132.000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "132.000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "66.000000"
|
||||
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||||
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
|
||||
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.000"
|
||||
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "ps"
|
||||
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "4"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "4"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "2"
|
||||
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "133.33333000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "133.33330000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "133.33330000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "133.33330000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "100.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "240.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "180.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "105.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "270.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
|
||||
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll2.mif"
|
||||
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
|
||||
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
|
||||
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
|
||||
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
|
||||
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK4 STRING "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLK3 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLK4 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA4 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
|
||||
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4"
|
||||
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "5051"
|
||||
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4"
|
||||
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4"
|
||||
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "3788"
|
||||
// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "4"
|
||||
// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "2210"
|
||||
// Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "2"
|
||||
// Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "11364"
|
||||
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
|
||||
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS"
|
||||
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
|
||||
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
|
||||
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
|
||||
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||||
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
|
||||
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
|
||||
// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
|
||||
// Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
|
||||
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
||||
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
|
||||
// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
|
||||
// Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.ppf TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
12
FPGA_quartus_GE/altip/altpll3.ppf
Normal file
12
FPGA_quartus_GE/altip/altpll3.ppf
Normal file
@@ -0,0 +1,12 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<!DOCTYPE pinplan>
|
||||
<pinplan intended_family="Cyclone III" variation_name="altpll3" megafunction_name="ALTPLL" specifies="all_ports">
|
||||
<global>
|
||||
<pin name="inclk0" direction="input" scope="external" source="clock" />
|
||||
<pin name="c0" direction="output" scope="external" source="clock" />
|
||||
<pin name="c1" direction="output" scope="external" source="clock" />
|
||||
<pin name="c2" direction="output" scope="external" source="clock" />
|
||||
<pin name="c3" direction="output" scope="external" source="clock" />
|
||||
|
||||
</global>
|
||||
</pinplan>
|
||||
4
FPGA_quartus_GE/altip/altpll3.qip
Normal file
4
FPGA_quartus_GE/altip/altpll3.qip
Normal file
@@ -0,0 +1,4 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "altpll3.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll3.ppf"]
|
||||
383
FPGA_quartus_GE/altip/altpll3.v
Normal file
383
FPGA_quartus_GE/altip/altpll3.v
Normal file
@@ -0,0 +1,383 @@
|
||||
// megafunction wizard: %ALTPLL%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: altpll
|
||||
|
||||
// ============================================================
|
||||
// File Name: altpll3.v
|
||||
// Megafunction Name(s):
|
||||
// altpll
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// altera_mf
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2013 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module altpll3 (
|
||||
inclk0,
|
||||
c0,
|
||||
c1,
|
||||
c2,
|
||||
c3);
|
||||
|
||||
input inclk0;
|
||||
output c0;
|
||||
output c1;
|
||||
output c2;
|
||||
output c3;
|
||||
|
||||
wire [4:0] sub_wire0;
|
||||
wire [0:0] sub_wire7 = 1'h0;
|
||||
wire [2:2] sub_wire4 = sub_wire0[2:2];
|
||||
wire [0:0] sub_wire3 = sub_wire0[0:0];
|
||||
wire [3:3] sub_wire2 = sub_wire0[3:3];
|
||||
wire [1:1] sub_wire1 = sub_wire0[1:1];
|
||||
wire c1 = sub_wire1;
|
||||
wire c3 = sub_wire2;
|
||||
wire c0 = sub_wire3;
|
||||
wire c2 = sub_wire4;
|
||||
wire sub_wire5 = inclk0;
|
||||
wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
|
||||
|
||||
altpll altpll_component (
|
||||
.inclk (sub_wire6),
|
||||
.clk (sub_wire0),
|
||||
.activeclock (),
|
||||
.areset (1'b0),
|
||||
.clkbad (),
|
||||
.clkena ({6{1'b1}}),
|
||||
.clkloss (),
|
||||
.clkswitch (1'b0),
|
||||
.configupdate (1'b0),
|
||||
.enable0 (),
|
||||
.enable1 (),
|
||||
.extclk (),
|
||||
.extclkena ({4{1'b1}}),
|
||||
.fbin (1'b1),
|
||||
.fbmimicbidir (),
|
||||
.fbout (),
|
||||
.fref (),
|
||||
.icdrclk (),
|
||||
.locked (),
|
||||
.pfdena (1'b1),
|
||||
.phasecounterselect ({4{1'b1}}),
|
||||
.phasedone (),
|
||||
.phasestep (1'b1),
|
||||
.phaseupdown (1'b1),
|
||||
.pllena (1'b1),
|
||||
.scanaclr (1'b0),
|
||||
.scanclk (1'b0),
|
||||
.scanclkena (1'b1),
|
||||
.scandata (1'b0),
|
||||
.scandataout (),
|
||||
.scandone (),
|
||||
.scanread (1'b0),
|
||||
.scanwrite (1'b0),
|
||||
.sclkout0 (),
|
||||
.sclkout1 (),
|
||||
.vcooverrange (),
|
||||
.vcounderrange ());
|
||||
defparam
|
||||
altpll_component.bandwidth_type = "AUTO",
|
||||
altpll_component.clk0_divide_by = 33,
|
||||
altpll_component.clk0_duty_cycle = 50,
|
||||
altpll_component.clk0_multiply_by = 2,
|
||||
altpll_component.clk0_phase_shift = "0",
|
||||
altpll_component.clk1_divide_by = 33,
|
||||
altpll_component.clk1_duty_cycle = 50,
|
||||
altpll_component.clk1_multiply_by = 16,
|
||||
altpll_component.clk1_phase_shift = "0",
|
||||
altpll_component.clk2_divide_by = 33,
|
||||
altpll_component.clk2_duty_cycle = 50,
|
||||
altpll_component.clk2_multiply_by = 25,
|
||||
altpll_component.clk2_phase_shift = "0",
|
||||
altpll_component.clk3_divide_by = 11,
|
||||
altpll_component.clk3_duty_cycle = 50,
|
||||
altpll_component.clk3_multiply_by = 16,
|
||||
altpll_component.clk3_phase_shift = "0",
|
||||
altpll_component.compensate_clock = "CLK1",
|
||||
altpll_component.inclk0_input_frequency = 30303,
|
||||
altpll_component.intended_device_family = "Cyclone III",
|
||||
altpll_component.lpm_type = "altpll",
|
||||
altpll_component.operation_mode = "SOURCE_SYNCHRONOUS",
|
||||
altpll_component.pll_type = "AUTO",
|
||||
altpll_component.port_activeclock = "PORT_UNUSED",
|
||||
altpll_component.port_areset = "PORT_UNUSED",
|
||||
altpll_component.port_clkbad0 = "PORT_UNUSED",
|
||||
altpll_component.port_clkbad1 = "PORT_UNUSED",
|
||||
altpll_component.port_clkloss = "PORT_UNUSED",
|
||||
altpll_component.port_clkswitch = "PORT_UNUSED",
|
||||
altpll_component.port_configupdate = "PORT_UNUSED",
|
||||
altpll_component.port_fbin = "PORT_UNUSED",
|
||||
altpll_component.port_inclk0 = "PORT_USED",
|
||||
altpll_component.port_inclk1 = "PORT_UNUSED",
|
||||
altpll_component.port_locked = "PORT_UNUSED",
|
||||
altpll_component.port_pfdena = "PORT_UNUSED",
|
||||
altpll_component.port_phasecounterselect = "PORT_UNUSED",
|
||||
altpll_component.port_phasedone = "PORT_UNUSED",
|
||||
altpll_component.port_phasestep = "PORT_UNUSED",
|
||||
altpll_component.port_phaseupdown = "PORT_UNUSED",
|
||||
altpll_component.port_pllena = "PORT_UNUSED",
|
||||
altpll_component.port_scanaclr = "PORT_UNUSED",
|
||||
altpll_component.port_scanclk = "PORT_UNUSED",
|
||||
altpll_component.port_scanclkena = "PORT_UNUSED",
|
||||
altpll_component.port_scandata = "PORT_UNUSED",
|
||||
altpll_component.port_scandataout = "PORT_UNUSED",
|
||||
altpll_component.port_scandone = "PORT_UNUSED",
|
||||
altpll_component.port_scanread = "PORT_UNUSED",
|
||||
altpll_component.port_scanwrite = "PORT_UNUSED",
|
||||
altpll_component.port_clk0 = "PORT_USED",
|
||||
altpll_component.port_clk1 = "PORT_USED",
|
||||
altpll_component.port_clk2 = "PORT_USED",
|
||||
altpll_component.port_clk3 = "PORT_USED",
|
||||
altpll_component.port_clk4 = "PORT_UNUSED",
|
||||
altpll_component.port_clk5 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena0 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena1 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena2 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena3 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena4 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena5 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk0 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk1 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk2 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk3 = "PORT_UNUSED",
|
||||
altpll_component.width_clock = 5;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c1"
|
||||
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
|
||||
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "33"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "33"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "33"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "33"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "2.000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "16.000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "25.000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "48.000000"
|
||||
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||||
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
|
||||
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.000"
|
||||
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
|
||||
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "16"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "25"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "48"
|
||||
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "2.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "16.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "25.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "160.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
|
||||
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
|
||||
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll3.mif"
|
||||
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
|
||||
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
|
||||
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
|
||||
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
|
||||
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLK3 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
|
||||
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "33"
|
||||
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
|
||||
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "33"
|
||||
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "16"
|
||||
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "33"
|
||||
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "25"
|
||||
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "11"
|
||||
// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "16"
|
||||
// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK1"
|
||||
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
|
||||
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS"
|
||||
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
|
||||
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
|
||||
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
|
||||
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||||
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
|
||||
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
|
||||
// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
|
||||
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
||||
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
|
||||
// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.ppf TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
174
FPGA_quartus_GE/altip/altpll4.mif
Normal file
174
FPGA_quartus_GE/altip/altpll4.mif
Normal file
@@ -0,0 +1,174 @@
|
||||
-- Copyright (C) 1991-2013 Altera Corporation
|
||||
-- Your use of Altera Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Altera Program License
|
||||
-- Subscription Agreement, Altera MegaCore Function License
|
||||
-- Agreement, or other applicable license agreement, including,
|
||||
-- without limitation, that your use is for the sole purpose of
|
||||
-- programming logic devices manufactured by Altera and sold by
|
||||
-- Altera or its authorized distributors. Please refer to the
|
||||
-- applicable agreement for further details.
|
||||
|
||||
-- MIF file representing initial state of PLL Scan Chain
|
||||
-- Device Family: Cyclone III
|
||||
-- Device Part: -
|
||||
-- Device Speed Grade: 8
|
||||
-- PLL Scan Chain: Fast PLL (144 bits)
|
||||
-- File Name: C:/firebee/FPGA_quartus/v//altpll4.mif
|
||||
-- Generated: Wed Mar 05 00:29:26 2014
|
||||
|
||||
WIDTH=1;
|
||||
DEPTH=144;
|
||||
|
||||
ADDRESS_RADIX=UNS;
|
||||
DATA_RADIX=UNS;
|
||||
|
||||
CONTENT BEGIN
|
||||
0 : 0; -- Reserved Bits = 0 (1 bit(s))
|
||||
1 : 0; -- Reserved Bits = 0 (1 bit(s))
|
||||
2 : 0; -- Loop Filter Capacitance = 0 (2 bit(s)) (Setting 0)
|
||||
3 : 0;
|
||||
4 : 1; -- Loop Filter Resistance = 27 (5 bit(s)) (Setting 27)
|
||||
5 : 1;
|
||||
6 : 0;
|
||||
7 : 1;
|
||||
8 : 1;
|
||||
9 : 0; -- VCO Post Scale = 0 (1 bit(s)) (VCO post-scale divider counter value = 2)
|
||||
10 : 0; -- Reserved Bits = 0 (5 bit(s))
|
||||
11 : 0;
|
||||
12 : 0;
|
||||
13 : 0;
|
||||
14 : 0;
|
||||
15 : 0; -- Charge Pump Current = 1 (3 bit(s)) (Setting 1)
|
||||
16 : 0;
|
||||
17 : 1;
|
||||
18 : 1; -- N counter: Bypass = 1 (1 bit(s))
|
||||
19 : 0; -- N counter: High Count = 0 (8 bit(s))
|
||||
20 : 0;
|
||||
21 : 0;
|
||||
22 : 0;
|
||||
23 : 0;
|
||||
24 : 0;
|
||||
25 : 0;
|
||||
26 : 0;
|
||||
27 : 0; -- N counter: Odd Division = 0 (1 bit(s))
|
||||
28 : 0; -- N counter: Low Count = 0 (8 bit(s))
|
||||
29 : 0;
|
||||
30 : 0;
|
||||
31 : 0;
|
||||
32 : 0;
|
||||
33 : 0;
|
||||
34 : 0;
|
||||
35 : 0;
|
||||
36 : 0; -- M counter: Bypass = 0 (1 bit(s))
|
||||
37 : 0; -- M counter: High Count = 6 (8 bit(s))
|
||||
38 : 0;
|
||||
39 : 0;
|
||||
40 : 0;
|
||||
41 : 0;
|
||||
42 : 1;
|
||||
43 : 1;
|
||||
44 : 0;
|
||||
45 : 0; -- M counter: Odd Division = 0 (1 bit(s))
|
||||
46 : 0; -- M counter: Low Count = 6 (8 bit(s))
|
||||
47 : 0;
|
||||
48 : 0;
|
||||
49 : 0;
|
||||
50 : 0;
|
||||
51 : 1;
|
||||
52 : 1;
|
||||
53 : 0;
|
||||
54 : 0; -- clk0 counter: Bypass = 0 (1 bit(s))
|
||||
55 : 0; -- clk0 counter: High Count = 3 (8 bit(s))
|
||||
56 : 0;
|
||||
57 : 0;
|
||||
58 : 0;
|
||||
59 : 0;
|
||||
60 : 0;
|
||||
61 : 1;
|
||||
62 : 1;
|
||||
63 : 0; -- clk0 counter: Odd Division = 0 (1 bit(s))
|
||||
64 : 0; -- clk0 counter: Low Count = 3 (8 bit(s))
|
||||
65 : 0;
|
||||
66 : 0;
|
||||
67 : 0;
|
||||
68 : 0;
|
||||
69 : 0;
|
||||
70 : 1;
|
||||
71 : 1;
|
||||
72 : 1; -- clk1 counter: Bypass = 1 (1 bit(s))
|
||||
73 : 0; -- clk1 counter: High Count = 0 (8 bit(s))
|
||||
74 : 0;
|
||||
75 : 0;
|
||||
76 : 0;
|
||||
77 : 0;
|
||||
78 : 0;
|
||||
79 : 0;
|
||||
80 : 0;
|
||||
81 : 0; -- clk1 counter: Odd Division = 0 (1 bit(s))
|
||||
82 : 0; -- clk1 counter: Low Count = 0 (8 bit(s))
|
||||
83 : 0;
|
||||
84 : 0;
|
||||
85 : 0;
|
||||
86 : 0;
|
||||
87 : 0;
|
||||
88 : 0;
|
||||
89 : 0;
|
||||
90 : 1; -- clk2 counter: Bypass = 1 (1 bit(s))
|
||||
91 : 0; -- clk2 counter: High Count = 0 (8 bit(s))
|
||||
92 : 0;
|
||||
93 : 0;
|
||||
94 : 0;
|
||||
95 : 0;
|
||||
96 : 0;
|
||||
97 : 0;
|
||||
98 : 0;
|
||||
99 : 0; -- clk2 counter: Odd Division = 0 (1 bit(s))
|
||||
100 : 0; -- clk2 counter: Low Count = 0 (8 bit(s))
|
||||
101 : 0;
|
||||
102 : 0;
|
||||
103 : 0;
|
||||
104 : 0;
|
||||
105 : 0;
|
||||
106 : 0;
|
||||
107 : 0;
|
||||
108 : 1; -- clk3 counter: Bypass = 1 (1 bit(s))
|
||||
109 : 0; -- clk3 counter: High Count = 0 (8 bit(s))
|
||||
110 : 0;
|
||||
111 : 0;
|
||||
112 : 0;
|
||||
113 : 0;
|
||||
114 : 0;
|
||||
115 : 0;
|
||||
116 : 0;
|
||||
117 : 0; -- clk3 counter: Odd Division = 0 (1 bit(s))
|
||||
118 : 0; -- clk3 counter: Low Count = 0 (8 bit(s))
|
||||
119 : 0;
|
||||
120 : 0;
|
||||
121 : 0;
|
||||
122 : 0;
|
||||
123 : 0;
|
||||
124 : 0;
|
||||
125 : 0;
|
||||
126 : 1; -- clk4 counter: Bypass = 1 (1 bit(s))
|
||||
127 : 0; -- clk4 counter: High Count = 0 (8 bit(s))
|
||||
128 : 0;
|
||||
129 : 0;
|
||||
130 : 0;
|
||||
131 : 0;
|
||||
132 : 0;
|
||||
133 : 0;
|
||||
134 : 0;
|
||||
135 : 0; -- clk4 counter: Odd Division = 0 (1 bit(s))
|
||||
136 : 0; -- clk4 counter: Low Count = 0 (8 bit(s))
|
||||
137 : 0;
|
||||
138 : 0;
|
||||
139 : 0;
|
||||
140 : 0;
|
||||
141 : 0;
|
||||
142 : 0;
|
||||
143 : 0;
|
||||
END;
|
||||
17
FPGA_quartus_GE/altip/altpll4.ppf
Normal file
17
FPGA_quartus_GE/altip/altpll4.ppf
Normal file
@@ -0,0 +1,17 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<!DOCTYPE pinplan>
|
||||
<pinplan intended_family="Cyclone III" variation_name="altpll4" megafunction_name="ALTPLL" specifies="all_ports">
|
||||
<global>
|
||||
<pin name="areset" direction="input" scope="external" />
|
||||
<pin name="configupdate" direction="input" scope="external" />
|
||||
<pin name="inclk0" direction="input" scope="external" source="clock" />
|
||||
<pin name="scanclk" direction="input" scope="external" source="clock" />
|
||||
<pin name="scanclkena" direction="input" scope="external" />
|
||||
<pin name="scandata" direction="input" scope="external" />
|
||||
<pin name="c0" direction="output" scope="external" source="clock" />
|
||||
<pin name="locked" direction="output" scope="external" />
|
||||
<pin name="scandataout" direction="output" scope="external" />
|
||||
<pin name="scandone" direction="output" scope="external" />
|
||||
|
||||
</global>
|
||||
</pinplan>
|
||||
4
FPGA_quartus_GE/altip/altpll4.qip
Normal file
4
FPGA_quartus_GE/altip/altpll4.qip
Normal file
@@ -0,0 +1,4 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "altpll4.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.ppf"]
|
||||
352
FPGA_quartus_GE/altip/altpll4.v
Normal file
352
FPGA_quartus_GE/altip/altpll4.v
Normal file
@@ -0,0 +1,352 @@
|
||||
// megafunction wizard: %ALTPLL%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: altpll
|
||||
|
||||
// ============================================================
|
||||
// File Name: altpll4.v
|
||||
// Megafunction Name(s):
|
||||
// altpll
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// altera_mf
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2013 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module altpll4 (
|
||||
areset,
|
||||
configupdate,
|
||||
inclk0,
|
||||
scanclk,
|
||||
scanclkena,
|
||||
scandata,
|
||||
c0,
|
||||
locked,
|
||||
scandataout,
|
||||
scandone);
|
||||
|
||||
input areset;
|
||||
input configupdate;
|
||||
input inclk0;
|
||||
input scanclk;
|
||||
input scanclkena;
|
||||
input scandata;
|
||||
output c0;
|
||||
output locked;
|
||||
output scandataout;
|
||||
output scandone;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_off
|
||||
`endif
|
||||
tri0 areset;
|
||||
tri0 configupdate;
|
||||
tri0 scanclkena;
|
||||
tri0 scandata;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_on
|
||||
`endif
|
||||
|
||||
wire [4:0] sub_wire0;
|
||||
wire sub_wire2;
|
||||
wire sub_wire3;
|
||||
wire sub_wire4;
|
||||
wire [0:0] sub_wire7 = 1'h0;
|
||||
wire [0:0] sub_wire1 = sub_wire0[0:0];
|
||||
wire c0 = sub_wire1;
|
||||
wire scandataout = sub_wire2;
|
||||
wire scandone = sub_wire3;
|
||||
wire locked = sub_wire4;
|
||||
wire sub_wire5 = inclk0;
|
||||
wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
|
||||
|
||||
altpll altpll_component (
|
||||
.areset (areset),
|
||||
.configupdate (configupdate),
|
||||
.inclk (sub_wire6),
|
||||
.scanclk (scanclk),
|
||||
.scanclkena (scanclkena),
|
||||
.scandata (scandata),
|
||||
.clk (sub_wire0),
|
||||
.scandataout (sub_wire2),
|
||||
.scandone (sub_wire3),
|
||||
.locked (sub_wire4),
|
||||
.activeclock (),
|
||||
.clkbad (),
|
||||
.clkena ({6{1'b1}}),
|
||||
.clkloss (),
|
||||
.clkswitch (1'b0),
|
||||
.enable0 (),
|
||||
.enable1 (),
|
||||
.extclk (),
|
||||
.extclkena ({4{1'b1}}),
|
||||
.fbin (1'b1),
|
||||
.fbmimicbidir (),
|
||||
.fbout (),
|
||||
.fref (),
|
||||
.icdrclk (),
|
||||
.pfdena (1'b1),
|
||||
.phasecounterselect ({4{1'b1}}),
|
||||
.phasedone (),
|
||||
.phasestep (1'b1),
|
||||
.phaseupdown (1'b1),
|
||||
.pllena (1'b1),
|
||||
.scanaclr (1'b0),
|
||||
.scanread (1'b0),
|
||||
.scanwrite (1'b0),
|
||||
.sclkout0 (),
|
||||
.sclkout1 (),
|
||||
.vcooverrange (),
|
||||
.vcounderrange ());
|
||||
defparam
|
||||
altpll_component.bandwidth_type = "AUTO",
|
||||
altpll_component.clk0_divide_by = 1,
|
||||
altpll_component.clk0_duty_cycle = 50,
|
||||
altpll_component.clk0_multiply_by = 2,
|
||||
altpll_component.clk0_phase_shift = "0",
|
||||
altpll_component.compensate_clock = "CLK0",
|
||||
altpll_component.inclk0_input_frequency = 20833,
|
||||
altpll_component.intended_device_family = "Cyclone III",
|
||||
altpll_component.lpm_type = "altpll",
|
||||
altpll_component.operation_mode = "NORMAL",
|
||||
altpll_component.pll_type = "AUTO",
|
||||
altpll_component.port_activeclock = "PORT_UNUSED",
|
||||
altpll_component.port_areset = "PORT_USED",
|
||||
altpll_component.port_clkbad0 = "PORT_UNUSED",
|
||||
altpll_component.port_clkbad1 = "PORT_UNUSED",
|
||||
altpll_component.port_clkloss = "PORT_UNUSED",
|
||||
altpll_component.port_clkswitch = "PORT_UNUSED",
|
||||
altpll_component.port_configupdate = "PORT_USED",
|
||||
altpll_component.port_fbin = "PORT_UNUSED",
|
||||
altpll_component.port_inclk0 = "PORT_USED",
|
||||
altpll_component.port_inclk1 = "PORT_UNUSED",
|
||||
altpll_component.port_locked = "PORT_USED",
|
||||
altpll_component.port_pfdena = "PORT_UNUSED",
|
||||
altpll_component.port_phasecounterselect = "PORT_UNUSED",
|
||||
altpll_component.port_phasedone = "PORT_UNUSED",
|
||||
altpll_component.port_phasestep = "PORT_UNUSED",
|
||||
altpll_component.port_phaseupdown = "PORT_UNUSED",
|
||||
altpll_component.port_pllena = "PORT_UNUSED",
|
||||
altpll_component.port_scanaclr = "PORT_UNUSED",
|
||||
altpll_component.port_scanclk = "PORT_USED",
|
||||
altpll_component.port_scanclkena = "PORT_USED",
|
||||
altpll_component.port_scandata = "PORT_USED",
|
||||
altpll_component.port_scandataout = "PORT_USED",
|
||||
altpll_component.port_scandone = "PORT_USED",
|
||||
altpll_component.port_scanread = "PORT_UNUSED",
|
||||
altpll_component.port_scanwrite = "PORT_UNUSED",
|
||||
altpll_component.port_clk0 = "PORT_USED",
|
||||
altpll_component.port_clk1 = "PORT_UNUSED",
|
||||
altpll_component.port_clk2 = "PORT_UNUSED",
|
||||
altpll_component.port_clk3 = "PORT_UNUSED",
|
||||
altpll_component.port_clk4 = "PORT_UNUSED",
|
||||
altpll_component.port_clk5 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena0 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena1 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena2 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena3 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena4 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena5 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk0 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk1 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk2 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk3 = "PORT_UNUSED",
|
||||
altpll_component.self_reset_on_loss_lock = "OFF",
|
||||
altpll_component.width_clock = 5,
|
||||
altpll_component.scan_chain_mif_file = "altpll4.mif";
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
|
||||
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
|
||||
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "96.000000"
|
||||
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||||
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
|
||||
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.000"
|
||||
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
|
||||
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
|
||||
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "144.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
|
||||
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
|
||||
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll4.mif"
|
||||
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "1"
|
||||
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
|
||||
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
|
||||
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
|
||||
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
|
||||
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
|
||||
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
|
||||
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20833"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
|
||||
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
|
||||
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
|
||||
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
|
||||
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
|
||||
// Retrieval info: CONSTANT: scan_chain_mif_file STRING "altpll4.mif"
|
||||
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
|
||||
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
|
||||
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||||
// Retrieval info: USED_PORT: configupdate 0 0 0 0 INPUT GND "configupdate"
|
||||
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
|
||||
// Retrieval info: USED_PORT: scanclk 0 0 0 0 INPUT_CLK_EXT VCC "scanclk"
|
||||
// Retrieval info: USED_PORT: scanclkena 0 0 0 0 INPUT GND "scanclkena"
|
||||
// Retrieval info: USED_PORT: scandata 0 0 0 0 INPUT GND "scandata"
|
||||
// Retrieval info: USED_PORT: scandataout 0 0 0 0 OUTPUT VCC "scandataout"
|
||||
// Retrieval info: USED_PORT: scandone 0 0 0 0 OUTPUT VCC "scandone"
|
||||
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
|
||||
// Retrieval info: CONNECT: @configupdate 0 0 0 0 configupdate 0 0 0 0
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
// Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0
|
||||
// Retrieval info: CONNECT: @scanclkena 0 0 0 0 scanclkena 0 0 0 0
|
||||
// Retrieval info: CONNECT: @scandata 0 0 0 0 scandata 0 0 0 0
|
||||
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
|
||||
// Retrieval info: CONNECT: scandataout 0 0 0 0 @scandataout 0 0 0 0
|
||||
// Retrieval info: CONNECT: scandone 0 0 0 0 @scandone 0 0 0 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.ppf TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll4_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll4_bb.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.mif TRUE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
3
FPGA_quartus_GE/altip/altpll_reconfig1.qip
Normal file
3
FPGA_quartus_GE/altip/altpll_reconfig1.qip
Normal file
@@ -0,0 +1,3 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ALTPLL_RECONFIG"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "altpll_reconfig1.v"]
|
||||
1465
FPGA_quartus_GE/altip/altpll_reconfig1.v
Normal file
1465
FPGA_quartus_GE/altip/altpll_reconfig1.v
Normal file
File diff suppressed because it is too large
Load Diff
3
FPGA_quartus_GE/altip/dcfifo0.qip
Normal file
3
FPGA_quartus_GE/altip/dcfifo0.qip
Normal file
@@ -0,0 +1,3 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "FIFO"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "dcfifo0.v"]
|
||||
177
FPGA_quartus_GE/altip/dcfifo0.v
Normal file
177
FPGA_quartus_GE/altip/dcfifo0.v
Normal file
@@ -0,0 +1,177 @@
|
||||
// megafunction wizard: %FIFO%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: dcfifo_mixed_widths
|
||||
|
||||
// ============================================================
|
||||
// File Name: dcfifo0.v
|
||||
// Megafunction Name(s):
|
||||
// dcfifo_mixed_widths
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// altera_mf
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2013 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module dcfifo0 (
|
||||
aclr,
|
||||
data,
|
||||
rdclk,
|
||||
rdreq,
|
||||
wrclk,
|
||||
wrreq,
|
||||
q,
|
||||
wrusedw);
|
||||
|
||||
input aclr;
|
||||
input [7:0] data;
|
||||
input rdclk;
|
||||
input rdreq;
|
||||
input wrclk;
|
||||
input wrreq;
|
||||
output [31:0] q;
|
||||
output [9:0] wrusedw;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_off
|
||||
`endif
|
||||
tri0 aclr;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_on
|
||||
`endif
|
||||
|
||||
wire [31:0] sub_wire0;
|
||||
wire [9:0] sub_wire1;
|
||||
wire [31:0] q = sub_wire0[31:0];
|
||||
wire [9:0] wrusedw = sub_wire1[9:0];
|
||||
|
||||
dcfifo_mixed_widths dcfifo_mixed_widths_component (
|
||||
.aclr (aclr),
|
||||
.data (data),
|
||||
.rdclk (rdclk),
|
||||
.rdreq (rdreq),
|
||||
.wrclk (wrclk),
|
||||
.wrreq (wrreq),
|
||||
.q (sub_wire0),
|
||||
.wrusedw (sub_wire1),
|
||||
.rdempty (),
|
||||
.rdfull (),
|
||||
.rdusedw (),
|
||||
.wrempty (),
|
||||
.wrfull ());
|
||||
defparam
|
||||
dcfifo_mixed_widths_component.intended_device_family = "Cyclone III",
|
||||
dcfifo_mixed_widths_component.lpm_numwords = 1024,
|
||||
dcfifo_mixed_widths_component.lpm_showahead = "OFF",
|
||||
dcfifo_mixed_widths_component.lpm_type = "dcfifo_mixed_widths",
|
||||
dcfifo_mixed_widths_component.lpm_width = 8,
|
||||
dcfifo_mixed_widths_component.lpm_widthu = 10,
|
||||
dcfifo_mixed_widths_component.lpm_widthu_r = 8,
|
||||
dcfifo_mixed_widths_component.lpm_width_r = 32,
|
||||
dcfifo_mixed_widths_component.overflow_checking = "ON",
|
||||
dcfifo_mixed_widths_component.rdsync_delaypipe = 5,
|
||||
dcfifo_mixed_widths_component.read_aclr_synch = "OFF",
|
||||
dcfifo_mixed_widths_component.underflow_checking = "ON",
|
||||
dcfifo_mixed_widths_component.use_eab = "ON",
|
||||
dcfifo_mixed_widths_component.write_aclr_synch = "OFF",
|
||||
dcfifo_mixed_widths_component.wrsync_delaypipe = 5;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
|
||||
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
|
||||
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Clock NUMERIC "4"
|
||||
// Retrieval info: PRIVATE: Depth NUMERIC "1024"
|
||||
// Retrieval info: PRIVATE: Empty NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: Full NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
|
||||
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: Width NUMERIC "8"
|
||||
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: diff_widths NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: output_width NUMERIC "32"
|
||||
// Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: wsFull NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
|
||||
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo_mixed_widths"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "8"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "32"
|
||||
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
|
||||
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
|
||||
// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
|
||||
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
|
||||
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
|
||||
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
|
||||
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
|
||||
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
|
||||
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
|
||||
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
|
||||
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
|
||||
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
|
||||
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
|
||||
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
|
||||
// Retrieval info: USED_PORT: wrusedw 0 0 10 0 OUTPUT NODEFVAL "wrusedw[9..0]"
|
||||
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
|
||||
// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
|
||||
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
|
||||
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
|
||||
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
|
||||
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
|
||||
// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
|
||||
// Retrieval info: CONNECT: wrusedw 0 0 10 0 @wrusedw 0 0 10 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
3
FPGA_quartus_GE/altip/dcfifo1.qip
Normal file
3
FPGA_quartus_GE/altip/dcfifo1.qip
Normal file
@@ -0,0 +1,3 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "FIFO"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "dcfifo1.v"]
|
||||
177
FPGA_quartus_GE/altip/dcfifo1.v
Normal file
177
FPGA_quartus_GE/altip/dcfifo1.v
Normal file
@@ -0,0 +1,177 @@
|
||||
// megafunction wizard: %FIFO%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: dcfifo_mixed_widths
|
||||
|
||||
// ============================================================
|
||||
// File Name: dcfifo1.v
|
||||
// Megafunction Name(s):
|
||||
// dcfifo_mixed_widths
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// altera_mf
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2013 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module dcfifo1 (
|
||||
aclr,
|
||||
data,
|
||||
rdclk,
|
||||
rdreq,
|
||||
wrclk,
|
||||
wrreq,
|
||||
q,
|
||||
rdusedw);
|
||||
|
||||
input aclr;
|
||||
input [31:0] data;
|
||||
input rdclk;
|
||||
input rdreq;
|
||||
input wrclk;
|
||||
input wrreq;
|
||||
output [7:0] q;
|
||||
output [9:0] rdusedw;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_off
|
||||
`endif
|
||||
tri0 aclr;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_on
|
||||
`endif
|
||||
|
||||
wire [9:0] sub_wire0;
|
||||
wire [7:0] sub_wire1;
|
||||
wire [9:0] rdusedw = sub_wire0[9:0];
|
||||
wire [7:0] q = sub_wire1[7:0];
|
||||
|
||||
dcfifo_mixed_widths dcfifo_mixed_widths_component (
|
||||
.aclr (aclr),
|
||||
.data (data),
|
||||
.rdclk (rdclk),
|
||||
.rdreq (rdreq),
|
||||
.wrclk (wrclk),
|
||||
.wrreq (wrreq),
|
||||
.rdusedw (sub_wire0),
|
||||
.q (sub_wire1),
|
||||
.rdempty (),
|
||||
.rdfull (),
|
||||
.wrempty (),
|
||||
.wrfull (),
|
||||
.wrusedw ());
|
||||
defparam
|
||||
dcfifo_mixed_widths_component.intended_device_family = "Cyclone III",
|
||||
dcfifo_mixed_widths_component.lpm_numwords = 256,
|
||||
dcfifo_mixed_widths_component.lpm_showahead = "OFF",
|
||||
dcfifo_mixed_widths_component.lpm_type = "dcfifo_mixed_widths",
|
||||
dcfifo_mixed_widths_component.lpm_width = 32,
|
||||
dcfifo_mixed_widths_component.lpm_widthu = 8,
|
||||
dcfifo_mixed_widths_component.lpm_widthu_r = 10,
|
||||
dcfifo_mixed_widths_component.lpm_width_r = 8,
|
||||
dcfifo_mixed_widths_component.overflow_checking = "ON",
|
||||
dcfifo_mixed_widths_component.rdsync_delaypipe = 5,
|
||||
dcfifo_mixed_widths_component.read_aclr_synch = "OFF",
|
||||
dcfifo_mixed_widths_component.underflow_checking = "ON",
|
||||
dcfifo_mixed_widths_component.use_eab = "ON",
|
||||
dcfifo_mixed_widths_component.write_aclr_synch = "OFF",
|
||||
dcfifo_mixed_widths_component.wrsync_delaypipe = 5;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
|
||||
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
|
||||
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Clock NUMERIC "4"
|
||||
// Retrieval info: PRIVATE: Depth NUMERIC "256"
|
||||
// Retrieval info: PRIVATE: Empty NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: Full NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
|
||||
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: Width NUMERIC "32"
|
||||
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: diff_widths NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: output_width NUMERIC "8"
|
||||
// Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: wsFull NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
|
||||
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo_mixed_widths"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "10"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "8"
|
||||
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
|
||||
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
|
||||
// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
|
||||
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
|
||||
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
|
||||
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
|
||||
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
|
||||
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
|
||||
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
|
||||
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
|
||||
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
|
||||
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
|
||||
// Retrieval info: USED_PORT: rdusedw 0 0 10 0 OUTPUT NODEFVAL "rdusedw[9..0]"
|
||||
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
|
||||
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
|
||||
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
|
||||
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
|
||||
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
|
||||
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
|
||||
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
|
||||
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
|
||||
// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
|
||||
// Retrieval info: CONNECT: rdusedw 0 0 10 0 @rdusedw 0 0 10 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
3
FPGA_quartus_GE/altip/lpm_compare1.qip
Normal file
3
FPGA_quartus_GE/altip/lpm_compare1.qip
Normal file
@@ -0,0 +1,3 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "LPM_COMPARE"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_compare1.v"]
|
||||
108
FPGA_quartus_GE/altip/lpm_compare1.v
Normal file
108
FPGA_quartus_GE/altip/lpm_compare1.v
Normal file
@@ -0,0 +1,108 @@
|
||||
// megafunction wizard: %LPM_COMPARE%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: LPM_COMPARE
|
||||
|
||||
// ============================================================
|
||||
// File Name: lpm_compare1.v
|
||||
// Megafunction Name(s):
|
||||
// LPM_COMPARE
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// lpm
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2013 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module lpm_compare1 (
|
||||
dataa,
|
||||
datab,
|
||||
agb);
|
||||
|
||||
input [10:0] dataa;
|
||||
input [10:0] datab;
|
||||
output agb;
|
||||
|
||||
wire sub_wire0;
|
||||
wire agb = sub_wire0;
|
||||
|
||||
lpm_compare LPM_COMPARE_component (
|
||||
.dataa (dataa),
|
||||
.datab (datab),
|
||||
.agb (sub_wire0),
|
||||
.aclr (1'b0),
|
||||
.aeb (),
|
||||
.ageb (),
|
||||
.alb (),
|
||||
.aleb (),
|
||||
.aneb (),
|
||||
.clken (1'b1),
|
||||
.clock (1'b0));
|
||||
defparam
|
||||
LPM_COMPARE_component.lpm_representation = "UNSIGNED",
|
||||
LPM_COMPARE_component.lpm_type = "LPM_COMPARE",
|
||||
LPM_COMPARE_component.lpm_width = 11;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: AeqB NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AgeB NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AgtB NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: AleB NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AltB NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AneB NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Latency NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PortBValue NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Radix NUMERIC "10"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: SignedCompare NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: aclr NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: clken NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: isPortBConstant NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: nBit NUMERIC "11"
|
||||
// Retrieval info: PRIVATE: new_diagram STRING "1"
|
||||
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "11"
|
||||
// Retrieval info: USED_PORT: agb 0 0 0 0 OUTPUT NODEFVAL "agb"
|
||||
// Retrieval info: USED_PORT: dataa 0 0 11 0 INPUT NODEFVAL "dataa[10..0]"
|
||||
// Retrieval info: USED_PORT: datab 0 0 11 0 INPUT NODEFVAL "datab[10..0]"
|
||||
// Retrieval info: CONNECT: @dataa 0 0 11 0 dataa 0 0 11 0
|
||||
// Retrieval info: CONNECT: @datab 0 0 11 0 datab 0 0 11 0
|
||||
// Retrieval info: CONNECT: agb 0 0 0 0 @agb 0 0 0 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: lpm
|
||||
3
FPGA_quartus_GE/altip/lpm_constant0.qip
Normal file
3
FPGA_quartus_GE/altip/lpm_constant0.qip
Normal file
@@ -0,0 +1,3 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_constant0.v"]
|
||||
82
FPGA_quartus_GE/altip/lpm_constant0.v
Normal file
82
FPGA_quartus_GE/altip/lpm_constant0.v
Normal file
@@ -0,0 +1,82 @@
|
||||
// megafunction wizard: %LPM_CONSTANT%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: LPM_CONSTANT
|
||||
|
||||
// ============================================================
|
||||
// File Name: lpm_constant0.v
|
||||
// Megafunction Name(s):
|
||||
// LPM_CONSTANT
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// lpm
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2013 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module lpm_constant0 (
|
||||
result);
|
||||
|
||||
output [4:0] result;
|
||||
|
||||
wire [4:0] sub_wire0;
|
||||
wire [4:0] result = sub_wire0[4:0];
|
||||
|
||||
lpm_constant LPM_CONSTANT_component (
|
||||
.result (sub_wire0));
|
||||
defparam
|
||||
LPM_CONSTANT_component.lpm_cvalue = 0,
|
||||
LPM_CONSTANT_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
|
||||
LPM_CONSTANT_component.lpm_type = "LPM_CONSTANT",
|
||||
LPM_CONSTANT_component.lpm_width = 5;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
|
||||
// Retrieval info: PRIVATE: Radix NUMERIC "2"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: Value NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: nBit NUMERIC "5"
|
||||
// Retrieval info: PRIVATE: new_diagram STRING "1"
|
||||
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||
// Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
|
||||
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5"
|
||||
// Retrieval info: USED_PORT: result 0 0 5 0 OUTPUT NODEFVAL "result[4..0]"
|
||||
// Retrieval info: CONNECT: result 0 0 5 0 @result 0 0 5 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: lpm
|
||||
3
FPGA_quartus_GE/altip/lpm_constant1.qip
Normal file
3
FPGA_quartus_GE/altip/lpm_constant1.qip
Normal file
@@ -0,0 +1,3 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_constant1.v"]
|
||||
82
FPGA_quartus_GE/altip/lpm_constant1.v
Normal file
82
FPGA_quartus_GE/altip/lpm_constant1.v
Normal file
@@ -0,0 +1,82 @@
|
||||
// megafunction wizard: %LPM_CONSTANT%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: LPM_CONSTANT
|
||||
|
||||
// ============================================================
|
||||
// File Name: lpm_constant1.v
|
||||
// Megafunction Name(s):
|
||||
// LPM_CONSTANT
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// lpm
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2013 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module lpm_constant1 (
|
||||
result);
|
||||
|
||||
output [1:0] result;
|
||||
|
||||
wire [1:0] sub_wire0;
|
||||
wire [1:0] result = sub_wire0[1:0];
|
||||
|
||||
lpm_constant LPM_CONSTANT_component (
|
||||
.result (sub_wire0));
|
||||
defparam
|
||||
LPM_CONSTANT_component.lpm_cvalue = 0,
|
||||
LPM_CONSTANT_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
|
||||
LPM_CONSTANT_component.lpm_type = "LPM_CONSTANT",
|
||||
LPM_CONSTANT_component.lpm_width = 2;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
|
||||
// Retrieval info: PRIVATE: Radix NUMERIC "2"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: Value NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: nBit NUMERIC "2"
|
||||
// Retrieval info: PRIVATE: new_diagram STRING "1"
|
||||
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||
// Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
|
||||
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "2"
|
||||
// Retrieval info: USED_PORT: result 0 0 2 0 OUTPUT NODEFVAL "result[1..0]"
|
||||
// Retrieval info: CONNECT: result 0 0 2 0 @result 0 0 2 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: lpm
|
||||
3
FPGA_quartus_GE/altip/lpm_constant2.qip
Normal file
3
FPGA_quartus_GE/altip/lpm_constant2.qip
Normal file
@@ -0,0 +1,3 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_constant2.v"]
|
||||
82
FPGA_quartus_GE/altip/lpm_constant2.v
Normal file
82
FPGA_quartus_GE/altip/lpm_constant2.v
Normal file
@@ -0,0 +1,82 @@
|
||||
// megafunction wizard: %LPM_CONSTANT%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: LPM_CONSTANT
|
||||
|
||||
// ============================================================
|
||||
// File Name: lpm_constant2.v
|
||||
// Megafunction Name(s):
|
||||
// LPM_CONSTANT
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// lpm
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2013 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module lpm_constant2 (
|
||||
result);
|
||||
|
||||
output [7:0] result;
|
||||
|
||||
wire [7:0] sub_wire0;
|
||||
wire [7:0] result = sub_wire0[7:0];
|
||||
|
||||
lpm_constant LPM_CONSTANT_component (
|
||||
.result (sub_wire0));
|
||||
defparam
|
||||
LPM_CONSTANT_component.lpm_cvalue = 0,
|
||||
LPM_CONSTANT_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
|
||||
LPM_CONSTANT_component.lpm_type = "LPM_CONSTANT",
|
||||
LPM_CONSTANT_component.lpm_width = 8;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
|
||||
// Retrieval info: PRIVATE: Radix NUMERIC "2"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: Value NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: nBit NUMERIC "8"
|
||||
// Retrieval info: PRIVATE: new_diagram STRING "1"
|
||||
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||
// Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
|
||||
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
|
||||
// Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL "result[7..0]"
|
||||
// Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: lpm
|
||||
3
FPGA_quartus_GE/altip/lpm_constant3.qip
Normal file
3
FPGA_quartus_GE/altip/lpm_constant3.qip
Normal file
@@ -0,0 +1,3 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_constant3.v"]
|
||||
82
FPGA_quartus_GE/altip/lpm_constant3.v
Normal file
82
FPGA_quartus_GE/altip/lpm_constant3.v
Normal file
@@ -0,0 +1,82 @@
|
||||
// megafunction wizard: %LPM_CONSTANT%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: LPM_CONSTANT
|
||||
|
||||
// ============================================================
|
||||
// File Name: lpm_constant3.v
|
||||
// Megafunction Name(s):
|
||||
// LPM_CONSTANT
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// lpm
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2013 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module lpm_constant3 (
|
||||
result);
|
||||
|
||||
output [6:0] result;
|
||||
|
||||
wire [6:0] sub_wire0;
|
||||
wire [6:0] result = sub_wire0[6:0];
|
||||
|
||||
lpm_constant LPM_CONSTANT_component (
|
||||
.result (sub_wire0));
|
||||
defparam
|
||||
LPM_CONSTANT_component.lpm_cvalue = 0,
|
||||
LPM_CONSTANT_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
|
||||
LPM_CONSTANT_component.lpm_type = "LPM_CONSTANT",
|
||||
LPM_CONSTANT_component.lpm_width = 7;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
|
||||
// Retrieval info: PRIVATE: Radix NUMERIC "2"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: Value NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: nBit NUMERIC "7"
|
||||
// Retrieval info: PRIVATE: new_diagram STRING "1"
|
||||
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||
// Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
|
||||
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "7"
|
||||
// Retrieval info: USED_PORT: result 0 0 7 0 OUTPUT NODEFVAL "result[6..0]"
|
||||
// Retrieval info: CONNECT: result 0 0 7 0 @result 0 0 7 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: lpm
|
||||
3
FPGA_quartus_GE/altip/lpm_constant4.qip
Normal file
3
FPGA_quartus_GE/altip/lpm_constant4.qip
Normal file
@@ -0,0 +1,3 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_constant4.v"]
|
||||
82
FPGA_quartus_GE/altip/lpm_constant4.v
Normal file
82
FPGA_quartus_GE/altip/lpm_constant4.v
Normal file
@@ -0,0 +1,82 @@
|
||||
// megafunction wizard: %LPM_CONSTANT%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: LPM_CONSTANT
|
||||
|
||||
// ============================================================
|
||||
// File Name: lpm_constant4.v
|
||||
// Megafunction Name(s):
|
||||
// LPM_CONSTANT
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// lpm
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2013 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module lpm_constant4 (
|
||||
result);
|
||||
|
||||
output [10:0] result;
|
||||
|
||||
wire [10:0] sub_wire0;
|
||||
wire [10:0] result = sub_wire0[10:0];
|
||||
|
||||
lpm_constant LPM_CONSTANT_component (
|
||||
.result (sub_wire0));
|
||||
defparam
|
||||
LPM_CONSTANT_component.lpm_cvalue = 2040,
|
||||
LPM_CONSTANT_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
|
||||
LPM_CONSTANT_component.lpm_type = "LPM_CONSTANT",
|
||||
LPM_CONSTANT_component.lpm_width = 11;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
|
||||
// Retrieval info: PRIVATE: Radix NUMERIC "10"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: Value NUMERIC "2040"
|
||||
// Retrieval info: PRIVATE: nBit NUMERIC "11"
|
||||
// Retrieval info: PRIVATE: new_diagram STRING "1"
|
||||
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||
// Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "2040"
|
||||
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "11"
|
||||
// Retrieval info: USED_PORT: result 0 0 11 0 OUTPUT NODEFVAL "result[10..0]"
|
||||
// Retrieval info: CONNECT: result 0 0 11 0 @result 0 0 11 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant4.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant4.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant4.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant4.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant4_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant4_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: lpm
|
||||
3
FPGA_quartus_GE/altip/lpm_counter0.qip
Normal file
3
FPGA_quartus_GE/altip/lpm_counter0.qip
Normal file
@@ -0,0 +1,3 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "LPM_COUNTER"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_counter0.v"]
|
||||
111
FPGA_quartus_GE/altip/lpm_counter0.v
Normal file
111
FPGA_quartus_GE/altip/lpm_counter0.v
Normal file
@@ -0,0 +1,111 @@
|
||||
// megafunction wizard: %LPM_COUNTER%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: LPM_COUNTER
|
||||
|
||||
// ============================================================
|
||||
// File Name: lpm_counter0.v
|
||||
// Megafunction Name(s):
|
||||
// LPM_COUNTER
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// lpm
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2013 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module lpm_counter0 (
|
||||
clock,
|
||||
q);
|
||||
|
||||
input clock;
|
||||
output [17:0] q;
|
||||
|
||||
wire [17:0] sub_wire0;
|
||||
wire [17:0] q = sub_wire0[17:0];
|
||||
|
||||
lpm_counter LPM_COUNTER_component (
|
||||
.clock (clock),
|
||||
.q (sub_wire0),
|
||||
.aclr (1'b0),
|
||||
.aload (1'b0),
|
||||
.aset (1'b0),
|
||||
.cin (1'b1),
|
||||
.clk_en (1'b1),
|
||||
.cnt_en (1'b1),
|
||||
.cout (),
|
||||
.data ({18{1'b0}}),
|
||||
.eq (),
|
||||
.sclr (1'b0),
|
||||
.sload (1'b0),
|
||||
.sset (1'b0),
|
||||
.updown (1'b1));
|
||||
defparam
|
||||
LPM_COUNTER_component.lpm_direction = "UP",
|
||||
LPM_COUNTER_component.lpm_port_updown = "PORT_UNUSED",
|
||||
LPM_COUNTER_component.lpm_type = "LPM_COUNTER",
|
||||
LPM_COUNTER_component.lpm_width = 18;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: ACLR NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ASET NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Direction NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: PRIVATE: ModulusCounter NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ModulusValue NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: SSET NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: nBit NUMERIC "18"
|
||||
// Retrieval info: PRIVATE: new_diagram STRING "1"
|
||||
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||
// Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
|
||||
// Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "18"
|
||||
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
|
||||
// Retrieval info: USED_PORT: q 0 0 18 0 OUTPUT NODEFVAL "q[17..0]"
|
||||
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
|
||||
// Retrieval info: CONNECT: q 0 0 18 0 @q 0 0 18 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: lpm
|
||||
3
FPGA_quartus_GE/altip/lpm_fifoDZ.qip
Normal file
3
FPGA_quartus_GE/altip/lpm_fifoDZ.qip
Normal file
@@ -0,0 +1,3 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "FIFO"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_fifoDZ.v"]
|
||||
149
FPGA_quartus_GE/altip/lpm_fifoDZ.v
Normal file
149
FPGA_quartus_GE/altip/lpm_fifoDZ.v
Normal file
@@ -0,0 +1,149 @@
|
||||
// megafunction wizard: %FIFO%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: scfifo
|
||||
|
||||
// ============================================================
|
||||
// File Name: lpm_fifoDZ.v
|
||||
// Megafunction Name(s):
|
||||
// scfifo
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// altera_mf
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2013 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module lpm_fifoDZ (
|
||||
aclr,
|
||||
clock,
|
||||
data,
|
||||
rdreq,
|
||||
wrreq,
|
||||
q);
|
||||
|
||||
input aclr;
|
||||
input clock;
|
||||
input [127:0] data;
|
||||
input rdreq;
|
||||
input wrreq;
|
||||
output [127:0] q;
|
||||
|
||||
wire [127:0] sub_wire0;
|
||||
wire [127:0] q = sub_wire0[127:0];
|
||||
|
||||
scfifo scfifo_component (
|
||||
.aclr (aclr),
|
||||
.clock (clock),
|
||||
.data (data),
|
||||
.rdreq (rdreq),
|
||||
.wrreq (wrreq),
|
||||
.q (sub_wire0),
|
||||
.almost_empty (),
|
||||
.almost_full (),
|
||||
.empty (),
|
||||
.full (),
|
||||
.sclr (),
|
||||
.usedw ());
|
||||
defparam
|
||||
scfifo_component.add_ram_output_register = "OFF",
|
||||
scfifo_component.intended_device_family = "Cyclone III",
|
||||
scfifo_component.lpm_numwords = 128,
|
||||
scfifo_component.lpm_showahead = "ON",
|
||||
scfifo_component.lpm_type = "scfifo",
|
||||
scfifo_component.lpm_width = 128,
|
||||
scfifo_component.lpm_widthu = 7,
|
||||
scfifo_component.overflow_checking = "OFF",
|
||||
scfifo_component.underflow_checking = "OFF",
|
||||
scfifo_component.use_eab = "ON";
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
|
||||
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
|
||||
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Clock NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Depth NUMERIC "128"
|
||||
// Retrieval info: PRIVATE: Empty NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Full NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
|
||||
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: UsedW NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Width NUMERIC "128"
|
||||
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: output_width NUMERIC "128"
|
||||
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: wsFull NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128"
|
||||
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7"
|
||||
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
|
||||
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
|
||||
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
|
||||
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
|
||||
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
|
||||
// Retrieval info: USED_PORT: data 0 0 128 0 INPUT NODEFVAL "data[127..0]"
|
||||
// Retrieval info: USED_PORT: q 0 0 128 0 OUTPUT NODEFVAL "q[127..0]"
|
||||
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
|
||||
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
|
||||
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
|
||||
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
|
||||
// Retrieval info: CONNECT: @data 0 0 128 0 data 0 0 128 0
|
||||
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
|
||||
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
|
||||
// Retrieval info: CONNECT: q 0 0 128 0 @q 0 0 128 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifoDZ.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifoDZ.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifoDZ.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifoDZ.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifoDZ_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifoDZ_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
3
FPGA_quartus_GE/altip/lpm_fifo_dc0.qip
Normal file
3
FPGA_quartus_GE/altip/lpm_fifo_dc0.qip
Normal file
@@ -0,0 +1,3 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "FIFO"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_fifo_dc0.v"]
|
||||
179
FPGA_quartus_GE/altip/lpm_fifo_dc0.v
Normal file
179
FPGA_quartus_GE/altip/lpm_fifo_dc0.v
Normal file
@@ -0,0 +1,179 @@
|
||||
// megafunction wizard: %FIFO%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: dcfifo
|
||||
|
||||
// ============================================================
|
||||
// File Name: lpm_fifo_dc0.v
|
||||
// Megafunction Name(s):
|
||||
// dcfifo
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// altera_mf
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2013 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module lpm_fifo_dc0 (
|
||||
aclr,
|
||||
data,
|
||||
rdclk,
|
||||
rdreq,
|
||||
wrclk,
|
||||
wrreq,
|
||||
q,
|
||||
rdempty,
|
||||
wrusedw);
|
||||
|
||||
input aclr;
|
||||
input [127:0] data;
|
||||
input rdclk;
|
||||
input rdreq;
|
||||
input wrclk;
|
||||
input wrreq;
|
||||
output [127:0] q;
|
||||
output rdempty;
|
||||
output [8:0] wrusedw;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_off
|
||||
`endif
|
||||
tri0 aclr;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_on
|
||||
`endif
|
||||
|
||||
wire [127:0] sub_wire0;
|
||||
wire sub_wire1;
|
||||
wire [8:0] sub_wire2;
|
||||
wire [127:0] q = sub_wire0[127:0];
|
||||
wire rdempty = sub_wire1;
|
||||
wire [8:0] wrusedw = sub_wire2[8:0];
|
||||
|
||||
dcfifo dcfifo_component (
|
||||
.rdclk (rdclk),
|
||||
.wrclk (wrclk),
|
||||
.wrreq (wrreq),
|
||||
.aclr (aclr),
|
||||
.data (data),
|
||||
.rdreq (rdreq),
|
||||
.q (sub_wire0),
|
||||
.rdempty (sub_wire1),
|
||||
.wrusedw (sub_wire2),
|
||||
.rdfull (),
|
||||
.rdusedw (),
|
||||
.wrempty (),
|
||||
.wrfull ());
|
||||
defparam
|
||||
dcfifo_component.intended_device_family = "Cyclone III",
|
||||
dcfifo_component.lpm_numwords = 512,
|
||||
dcfifo_component.lpm_showahead = "OFF",
|
||||
dcfifo_component.lpm_type = "dcfifo",
|
||||
dcfifo_component.lpm_width = 128,
|
||||
dcfifo_component.lpm_widthu = 9,
|
||||
dcfifo_component.overflow_checking = "OFF",
|
||||
dcfifo_component.rdsync_delaypipe = 6,
|
||||
dcfifo_component.read_aclr_synch = "OFF",
|
||||
dcfifo_component.underflow_checking = "OFF",
|
||||
dcfifo_component.use_eab = "ON",
|
||||
dcfifo_component.write_aclr_synch = "ON",
|
||||
dcfifo_component.wrsync_delaypipe = 6;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
|
||||
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
|
||||
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Clock NUMERIC "4"
|
||||
// Retrieval info: PRIVATE: Depth NUMERIC "512"
|
||||
// Retrieval info: PRIVATE: Empty NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: Full NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
|
||||
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: Width NUMERIC "128"
|
||||
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: output_width NUMERIC "128"
|
||||
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: wsFull NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
|
||||
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
|
||||
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
|
||||
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "6"
|
||||
// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
|
||||
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
|
||||
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
|
||||
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "ON"
|
||||
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "6"
|
||||
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
|
||||
// Retrieval info: USED_PORT: data 0 0 128 0 INPUT NODEFVAL "data[127..0]"
|
||||
// Retrieval info: USED_PORT: q 0 0 128 0 OUTPUT NODEFVAL "q[127..0]"
|
||||
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
|
||||
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
|
||||
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
|
||||
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
|
||||
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
|
||||
// Retrieval info: USED_PORT: wrusedw 0 0 9 0 OUTPUT NODEFVAL "wrusedw[8..0]"
|
||||
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
|
||||
// Retrieval info: CONNECT: @data 0 0 128 0 data 0 0 128 0
|
||||
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
|
||||
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
|
||||
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
|
||||
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
|
||||
// Retrieval info: CONNECT: q 0 0 128 0 @q 0 0 128 0
|
||||
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
|
||||
// Retrieval info: CONNECT: wrusedw 0 0 9 0 @wrusedw 0 0 9 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifo_dc0.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifo_dc0.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifo_dc0.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifo_dc0.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifo_dc0_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifo_dc0_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
3
FPGA_quartus_GE/altip/lpm_mux0.qip
Normal file
3
FPGA_quartus_GE/altip/lpm_mux0.qip
Normal file
@@ -0,0 +1,3 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_mux0.v"]
|
||||
117
FPGA_quartus_GE/altip/lpm_mux0.v
Normal file
117
FPGA_quartus_GE/altip/lpm_mux0.v
Normal file
@@ -0,0 +1,117 @@
|
||||
// megafunction wizard: %LPM_MUX%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: LPM_MUX
|
||||
|
||||
// ============================================================
|
||||
// File Name: lpm_mux0.v
|
||||
// Megafunction Name(s):
|
||||
// LPM_MUX
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// lpm
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2013 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module lpm_mux0 (
|
||||
clock,
|
||||
data0x,
|
||||
data1x,
|
||||
data2x,
|
||||
data3x,
|
||||
sel,
|
||||
result);
|
||||
|
||||
input clock;
|
||||
input [31:0] data0x;
|
||||
input [31:0] data1x;
|
||||
input [31:0] data2x;
|
||||
input [31:0] data3x;
|
||||
input [1:0] sel;
|
||||
output [31:0] result;
|
||||
|
||||
wire [31:0] sub_wire0;
|
||||
wire [31:0] sub_wire5 = data3x[31:0];
|
||||
wire [31:0] sub_wire4 = data2x[31:0];
|
||||
wire [31:0] sub_wire3 = data1x[31:0];
|
||||
wire [31:0] result = sub_wire0[31:0];
|
||||
wire [31:0] sub_wire1 = data0x[31:0];
|
||||
wire [127:0] sub_wire2 = {sub_wire5, sub_wire4, sub_wire3, sub_wire1};
|
||||
|
||||
lpm_mux LPM_MUX_component (
|
||||
.clock (clock),
|
||||
.data (sub_wire2),
|
||||
.sel (sel),
|
||||
.result (sub_wire0)
|
||||
// synopsys translate_off
|
||||
,
|
||||
.aclr (),
|
||||
.clken ()
|
||||
// synopsys translate_on
|
||||
);
|
||||
defparam
|
||||
LPM_MUX_component.lpm_pipeline = 4,
|
||||
LPM_MUX_component.lpm_size = 4,
|
||||
LPM_MUX_component.lpm_type = "LPM_MUX",
|
||||
LPM_MUX_component.lpm_width = 32,
|
||||
LPM_MUX_component.lpm_widths = 2;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: new_diagram STRING "1"
|
||||
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "4"
|
||||
// Retrieval info: CONSTANT: LPM_SIZE NUMERIC "4"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "2"
|
||||
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
|
||||
// Retrieval info: USED_PORT: data0x 0 0 32 0 INPUT NODEFVAL "data0x[31..0]"
|
||||
// Retrieval info: USED_PORT: data1x 0 0 32 0 INPUT NODEFVAL "data1x[31..0]"
|
||||
// Retrieval info: USED_PORT: data2x 0 0 32 0 INPUT NODEFVAL "data2x[31..0]"
|
||||
// Retrieval info: USED_PORT: data3x 0 0 32 0 INPUT NODEFVAL "data3x[31..0]"
|
||||
// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
|
||||
// Retrieval info: USED_PORT: sel 0 0 2 0 INPUT NODEFVAL "sel[1..0]"
|
||||
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
|
||||
// Retrieval info: CONNECT: @data 0 0 32 0 data0x 0 0 32 0
|
||||
// Retrieval info: CONNECT: @data 0 0 32 32 data1x 0 0 32 0
|
||||
// Retrieval info: CONNECT: @data 0 0 32 64 data2x 0 0 32 0
|
||||
// Retrieval info: CONNECT: @data 0 0 32 96 data3x 0 0 32 0
|
||||
// Retrieval info: CONNECT: @sel 0 0 2 0 sel 0 0 2 0
|
||||
// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: lpm
|
||||
3
FPGA_quartus_GE/altip/lpm_mux1.qip
Normal file
3
FPGA_quartus_GE/altip/lpm_mux1.qip
Normal file
@@ -0,0 +1,3 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_mux1.v"]
|
||||
137
FPGA_quartus_GE/altip/lpm_mux1.v
Normal file
137
FPGA_quartus_GE/altip/lpm_mux1.v
Normal file
@@ -0,0 +1,137 @@
|
||||
// megafunction wizard: %LPM_MUX%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: LPM_MUX
|
||||
|
||||
// ============================================================
|
||||
// File Name: lpm_mux1.v
|
||||
// Megafunction Name(s):
|
||||
// LPM_MUX
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// lpm
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2013 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module lpm_mux1 (
|
||||
clock,
|
||||
data0x,
|
||||
data1x,
|
||||
data2x,
|
||||
data3x,
|
||||
data4x,
|
||||
data5x,
|
||||
data6x,
|
||||
data7x,
|
||||
sel,
|
||||
result);
|
||||
|
||||
input clock;
|
||||
input [15:0] data0x;
|
||||
input [15:0] data1x;
|
||||
input [15:0] data2x;
|
||||
input [15:0] data3x;
|
||||
input [15:0] data4x;
|
||||
input [15:0] data5x;
|
||||
input [15:0] data6x;
|
||||
input [15:0] data7x;
|
||||
input [2:0] sel;
|
||||
output [15:0] result;
|
||||
|
||||
wire [15:0] sub_wire0;
|
||||
wire [15:0] sub_wire9 = data7x[15:0];
|
||||
wire [15:0] sub_wire8 = data6x[15:0];
|
||||
wire [15:0] sub_wire7 = data5x[15:0];
|
||||
wire [15:0] sub_wire6 = data4x[15:0];
|
||||
wire [15:0] sub_wire5 = data3x[15:0];
|
||||
wire [15:0] sub_wire4 = data2x[15:0];
|
||||
wire [15:0] sub_wire3 = data1x[15:0];
|
||||
wire [15:0] result = sub_wire0[15:0];
|
||||
wire [15:0] sub_wire1 = data0x[15:0];
|
||||
wire [127:0] sub_wire2 = {sub_wire9, sub_wire8, sub_wire7, sub_wire6, sub_wire5, sub_wire4, sub_wire3, sub_wire1};
|
||||
|
||||
lpm_mux LPM_MUX_component (
|
||||
.clock (clock),
|
||||
.data (sub_wire2),
|
||||
.sel (sel),
|
||||
.result (sub_wire0)
|
||||
// synopsys translate_off
|
||||
,
|
||||
.aclr (),
|
||||
.clken ()
|
||||
// synopsys translate_on
|
||||
);
|
||||
defparam
|
||||
LPM_MUX_component.lpm_pipeline = 4,
|
||||
LPM_MUX_component.lpm_size = 8,
|
||||
LPM_MUX_component.lpm_type = "LPM_MUX",
|
||||
LPM_MUX_component.lpm_width = 16,
|
||||
LPM_MUX_component.lpm_widths = 3;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: new_diagram STRING "1"
|
||||
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "4"
|
||||
// Retrieval info: CONSTANT: LPM_SIZE NUMERIC "8"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "3"
|
||||
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
|
||||
// Retrieval info: USED_PORT: data0x 0 0 16 0 INPUT NODEFVAL "data0x[15..0]"
|
||||
// Retrieval info: USED_PORT: data1x 0 0 16 0 INPUT NODEFVAL "data1x[15..0]"
|
||||
// Retrieval info: USED_PORT: data2x 0 0 16 0 INPUT NODEFVAL "data2x[15..0]"
|
||||
// Retrieval info: USED_PORT: data3x 0 0 16 0 INPUT NODEFVAL "data3x[15..0]"
|
||||
// Retrieval info: USED_PORT: data4x 0 0 16 0 INPUT NODEFVAL "data4x[15..0]"
|
||||
// Retrieval info: USED_PORT: data5x 0 0 16 0 INPUT NODEFVAL "data5x[15..0]"
|
||||
// Retrieval info: USED_PORT: data6x 0 0 16 0 INPUT NODEFVAL "data6x[15..0]"
|
||||
// Retrieval info: USED_PORT: data7x 0 0 16 0 INPUT NODEFVAL "data7x[15..0]"
|
||||
// Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL "result[15..0]"
|
||||
// Retrieval info: USED_PORT: sel 0 0 3 0 INPUT NODEFVAL "sel[2..0]"
|
||||
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
|
||||
// Retrieval info: CONNECT: @data 0 0 16 0 data0x 0 0 16 0
|
||||
// Retrieval info: CONNECT: @data 0 0 16 16 data1x 0 0 16 0
|
||||
// Retrieval info: CONNECT: @data 0 0 16 32 data2x 0 0 16 0
|
||||
// Retrieval info: CONNECT: @data 0 0 16 48 data3x 0 0 16 0
|
||||
// Retrieval info: CONNECT: @data 0 0 16 64 data4x 0 0 16 0
|
||||
// Retrieval info: CONNECT: @data 0 0 16 80 data5x 0 0 16 0
|
||||
// Retrieval info: CONNECT: @data 0 0 16 96 data6x 0 0 16 0
|
||||
// Retrieval info: CONNECT: @data 0 0 16 112 data7x 0 0 16 0
|
||||
// Retrieval info: CONNECT: @sel 0 0 3 0 sel 0 0 3 0
|
||||
// Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: lpm
|
||||
3
FPGA_quartus_GE/altip/lpm_mux2.qip
Normal file
3
FPGA_quartus_GE/altip/lpm_mux2.qip
Normal file
@@ -0,0 +1,3 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_mux2.v"]
|
||||
177
FPGA_quartus_GE/altip/lpm_mux2.v
Normal file
177
FPGA_quartus_GE/altip/lpm_mux2.v
Normal file
@@ -0,0 +1,177 @@
|
||||
// megafunction wizard: %LPM_MUX%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: LPM_MUX
|
||||
|
||||
// ============================================================
|
||||
// File Name: lpm_mux2.v
|
||||
// Megafunction Name(s):
|
||||
// LPM_MUX
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// lpm
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2013 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module lpm_mux2 (
|
||||
clock,
|
||||
data0x,
|
||||
data10x,
|
||||
data11x,
|
||||
data12x,
|
||||
data13x,
|
||||
data14x,
|
||||
data15x,
|
||||
data1x,
|
||||
data2x,
|
||||
data3x,
|
||||
data4x,
|
||||
data5x,
|
||||
data6x,
|
||||
data7x,
|
||||
data8x,
|
||||
data9x,
|
||||
sel,
|
||||
result);
|
||||
|
||||
input clock;
|
||||
input [7:0] data0x;
|
||||
input [7:0] data10x;
|
||||
input [7:0] data11x;
|
||||
input [7:0] data12x;
|
||||
input [7:0] data13x;
|
||||
input [7:0] data14x;
|
||||
input [7:0] data15x;
|
||||
input [7:0] data1x;
|
||||
input [7:0] data2x;
|
||||
input [7:0] data3x;
|
||||
input [7:0] data4x;
|
||||
input [7:0] data5x;
|
||||
input [7:0] data6x;
|
||||
input [7:0] data7x;
|
||||
input [7:0] data8x;
|
||||
input [7:0] data9x;
|
||||
input [3:0] sel;
|
||||
output [7:0] result;
|
||||
|
||||
wire [7:0] sub_wire0;
|
||||
wire [7:0] sub_wire17 = data15x[7:0];
|
||||
wire [7:0] sub_wire16 = data14x[7:0];
|
||||
wire [7:0] sub_wire15 = data13x[7:0];
|
||||
wire [7:0] sub_wire14 = data12x[7:0];
|
||||
wire [7:0] sub_wire13 = data11x[7:0];
|
||||
wire [7:0] sub_wire12 = data10x[7:0];
|
||||
wire [7:0] sub_wire11 = data9x[7:0];
|
||||
wire [7:0] sub_wire10 = data8x[7:0];
|
||||
wire [7:0] sub_wire9 = data7x[7:0];
|
||||
wire [7:0] sub_wire8 = data6x[7:0];
|
||||
wire [7:0] sub_wire7 = data5x[7:0];
|
||||
wire [7:0] sub_wire6 = data4x[7:0];
|
||||
wire [7:0] sub_wire5 = data3x[7:0];
|
||||
wire [7:0] sub_wire4 = data2x[7:0];
|
||||
wire [7:0] sub_wire3 = data1x[7:0];
|
||||
wire [7:0] result = sub_wire0[7:0];
|
||||
wire [7:0] sub_wire1 = data0x[7:0];
|
||||
wire [127:0] sub_wire2 = {sub_wire17, sub_wire16, sub_wire15, sub_wire14, sub_wire13, sub_wire12, sub_wire11, sub_wire10, sub_wire9, sub_wire8, sub_wire7, sub_wire6, sub_wire5, sub_wire4, sub_wire3, sub_wire1};
|
||||
|
||||
lpm_mux LPM_MUX_component (
|
||||
.clock (clock),
|
||||
.data (sub_wire2),
|
||||
.sel (sel),
|
||||
.result (sub_wire0)
|
||||
// synopsys translate_off
|
||||
,
|
||||
.aclr (),
|
||||
.clken ()
|
||||
// synopsys translate_on
|
||||
);
|
||||
defparam
|
||||
LPM_MUX_component.lpm_pipeline = 2,
|
||||
LPM_MUX_component.lpm_size = 16,
|
||||
LPM_MUX_component.lpm_type = "LPM_MUX",
|
||||
LPM_MUX_component.lpm_width = 8,
|
||||
LPM_MUX_component.lpm_widths = 4;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: new_diagram STRING "1"
|
||||
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "2"
|
||||
// Retrieval info: CONSTANT: LPM_SIZE NUMERIC "16"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "4"
|
||||
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
|
||||
// Retrieval info: USED_PORT: data0x 0 0 8 0 INPUT NODEFVAL "data0x[7..0]"
|
||||
// Retrieval info: USED_PORT: data10x 0 0 8 0 INPUT NODEFVAL "data10x[7..0]"
|
||||
// Retrieval info: USED_PORT: data11x 0 0 8 0 INPUT NODEFVAL "data11x[7..0]"
|
||||
// Retrieval info: USED_PORT: data12x 0 0 8 0 INPUT NODEFVAL "data12x[7..0]"
|
||||
// Retrieval info: USED_PORT: data13x 0 0 8 0 INPUT NODEFVAL "data13x[7..0]"
|
||||
// Retrieval info: USED_PORT: data14x 0 0 8 0 INPUT NODEFVAL "data14x[7..0]"
|
||||
// Retrieval info: USED_PORT: data15x 0 0 8 0 INPUT NODEFVAL "data15x[7..0]"
|
||||
// Retrieval info: USED_PORT: data1x 0 0 8 0 INPUT NODEFVAL "data1x[7..0]"
|
||||
// Retrieval info: USED_PORT: data2x 0 0 8 0 INPUT NODEFVAL "data2x[7..0]"
|
||||
// Retrieval info: USED_PORT: data3x 0 0 8 0 INPUT NODEFVAL "data3x[7..0]"
|
||||
// Retrieval info: USED_PORT: data4x 0 0 8 0 INPUT NODEFVAL "data4x[7..0]"
|
||||
// Retrieval info: USED_PORT: data5x 0 0 8 0 INPUT NODEFVAL "data5x[7..0]"
|
||||
// Retrieval info: USED_PORT: data6x 0 0 8 0 INPUT NODEFVAL "data6x[7..0]"
|
||||
// Retrieval info: USED_PORT: data7x 0 0 8 0 INPUT NODEFVAL "data7x[7..0]"
|
||||
// Retrieval info: USED_PORT: data8x 0 0 8 0 INPUT NODEFVAL "data8x[7..0]"
|
||||
// Retrieval info: USED_PORT: data9x 0 0 8 0 INPUT NODEFVAL "data9x[7..0]"
|
||||
// Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL "result[7..0]"
|
||||
// Retrieval info: USED_PORT: sel 0 0 4 0 INPUT NODEFVAL "sel[3..0]"
|
||||
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
|
||||
// Retrieval info: CONNECT: @data 0 0 8 0 data0x 0 0 8 0
|
||||
// Retrieval info: CONNECT: @data 0 0 8 80 data10x 0 0 8 0
|
||||
// Retrieval info: CONNECT: @data 0 0 8 88 data11x 0 0 8 0
|
||||
// Retrieval info: CONNECT: @data 0 0 8 96 data12x 0 0 8 0
|
||||
// Retrieval info: CONNECT: @data 0 0 8 104 data13x 0 0 8 0
|
||||
// Retrieval info: CONNECT: @data 0 0 8 112 data14x 0 0 8 0
|
||||
// Retrieval info: CONNECT: @data 0 0 8 120 data15x 0 0 8 0
|
||||
// Retrieval info: CONNECT: @data 0 0 8 8 data1x 0 0 8 0
|
||||
// Retrieval info: CONNECT: @data 0 0 8 16 data2x 0 0 8 0
|
||||
// Retrieval info: CONNECT: @data 0 0 8 24 data3x 0 0 8 0
|
||||
// Retrieval info: CONNECT: @data 0 0 8 32 data4x 0 0 8 0
|
||||
// Retrieval info: CONNECT: @data 0 0 8 40 data5x 0 0 8 0
|
||||
// Retrieval info: CONNECT: @data 0 0 8 48 data6x 0 0 8 0
|
||||
// Retrieval info: CONNECT: @data 0 0 8 56 data7x 0 0 8 0
|
||||
// Retrieval info: CONNECT: @data 0 0 8 64 data8x 0 0 8 0
|
||||
// Retrieval info: CONNECT: @data 0 0 8 72 data9x 0 0 8 0
|
||||
// Retrieval info: CONNECT: @sel 0 0 4 0 sel 0 0 4 0
|
||||
// Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: lpm
|
||||
3
FPGA_quartus_GE/altip/lpm_mux3.qip
Normal file
3
FPGA_quartus_GE/altip/lpm_mux3.qip
Normal file
@@ -0,0 +1,3 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_mux3.v"]
|
||||
104
FPGA_quartus_GE/altip/lpm_mux3.v
Normal file
104
FPGA_quartus_GE/altip/lpm_mux3.v
Normal file
@@ -0,0 +1,104 @@
|
||||
// megafunction wizard: %LPM_MUX%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: LPM_MUX
|
||||
|
||||
// ============================================================
|
||||
// File Name: lpm_mux3.v
|
||||
// Megafunction Name(s):
|
||||
// LPM_MUX
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// lpm
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2013 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module lpm_mux3 (
|
||||
data0,
|
||||
data1,
|
||||
sel,
|
||||
result);
|
||||
|
||||
input data0;
|
||||
input data1;
|
||||
input sel;
|
||||
output result;
|
||||
|
||||
wire [0:0] sub_wire0;
|
||||
wire sub_wire4 = data1;
|
||||
wire [0:0] sub_wire1 = sub_wire0[0:0];
|
||||
wire result = sub_wire1;
|
||||
wire sub_wire2 = data0;
|
||||
wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
|
||||
wire sub_wire5 = sel;
|
||||
wire sub_wire6 = sub_wire5;
|
||||
|
||||
lpm_mux LPM_MUX_component (
|
||||
.data (sub_wire3),
|
||||
.sel (sub_wire6),
|
||||
.result (sub_wire0)
|
||||
// synopsys translate_off
|
||||
,
|
||||
.aclr (),
|
||||
.clken (),
|
||||
.clock ()
|
||||
// synopsys translate_on
|
||||
);
|
||||
defparam
|
||||
LPM_MUX_component.lpm_size = 2,
|
||||
LPM_MUX_component.lpm_type = "LPM_MUX",
|
||||
LPM_MUX_component.lpm_width = 1,
|
||||
LPM_MUX_component.lpm_widths = 1;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: new_diagram STRING "1"
|
||||
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||
// Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1"
|
||||
// Retrieval info: USED_PORT: data0 0 0 0 0 INPUT NODEFVAL "data0"
|
||||
// Retrieval info: USED_PORT: data1 0 0 0 0 INPUT NODEFVAL "data1"
|
||||
// Retrieval info: USED_PORT: result 0 0 0 0 OUTPUT NODEFVAL "result"
|
||||
// Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL "sel"
|
||||
// Retrieval info: CONNECT: @data 0 0 1 0 data0 0 0 0 0
|
||||
// Retrieval info: CONNECT: @data 0 0 1 1 data1 0 0 0 0
|
||||
// Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0
|
||||
// Retrieval info: CONNECT: result 0 0 0 0 @result 0 0 1 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: lpm
|
||||
3
FPGA_quartus_GE/altip/lpm_mux4.qip
Normal file
3
FPGA_quartus_GE/altip/lpm_mux4.qip
Normal file
@@ -0,0 +1,3 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_mux4.v"]
|
||||
103
FPGA_quartus_GE/altip/lpm_mux4.v
Normal file
103
FPGA_quartus_GE/altip/lpm_mux4.v
Normal file
@@ -0,0 +1,103 @@
|
||||
// megafunction wizard: %LPM_MUX%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: LPM_MUX
|
||||
|
||||
// ============================================================
|
||||
// File Name: lpm_mux4.v
|
||||
// Megafunction Name(s):
|
||||
// LPM_MUX
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// lpm
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2013 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module lpm_mux4 (
|
||||
data0x,
|
||||
data1x,
|
||||
sel,
|
||||
result);
|
||||
|
||||
input [6:0] data0x;
|
||||
input [6:0] data1x;
|
||||
input sel;
|
||||
output [6:0] result;
|
||||
|
||||
wire [6:0] sub_wire0;
|
||||
wire [6:0] sub_wire3 = data1x[6:0];
|
||||
wire [6:0] result = sub_wire0[6:0];
|
||||
wire [6:0] sub_wire1 = data0x[6:0];
|
||||
wire [13:0] sub_wire2 = {sub_wire3, sub_wire1};
|
||||
wire sub_wire4 = sel;
|
||||
wire sub_wire5 = sub_wire4;
|
||||
|
||||
lpm_mux LPM_MUX_component (
|
||||
.data (sub_wire2),
|
||||
.sel (sub_wire5),
|
||||
.result (sub_wire0)
|
||||
// synopsys translate_off
|
||||
,
|
||||
.aclr (),
|
||||
.clken (),
|
||||
.clock ()
|
||||
// synopsys translate_on
|
||||
);
|
||||
defparam
|
||||
LPM_MUX_component.lpm_size = 2,
|
||||
LPM_MUX_component.lpm_type = "LPM_MUX",
|
||||
LPM_MUX_component.lpm_width = 7,
|
||||
LPM_MUX_component.lpm_widths = 1;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: new_diagram STRING "1"
|
||||
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||
// Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "7"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1"
|
||||
// Retrieval info: USED_PORT: data0x 0 0 7 0 INPUT NODEFVAL "data0x[6..0]"
|
||||
// Retrieval info: USED_PORT: data1x 0 0 7 0 INPUT NODEFVAL "data1x[6..0]"
|
||||
// Retrieval info: USED_PORT: result 0 0 7 0 OUTPUT NODEFVAL "result[6..0]"
|
||||
// Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL "sel"
|
||||
// Retrieval info: CONNECT: @data 0 0 7 0 data0x 0 0 7 0
|
||||
// Retrieval info: CONNECT: @data 0 0 7 7 data1x 0 0 7 0
|
||||
// Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0
|
||||
// Retrieval info: CONNECT: result 0 0 7 0 @result 0 0 7 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: lpm
|
||||
3
FPGA_quartus_GE/altip/lpm_mux5.qip
Normal file
3
FPGA_quartus_GE/altip/lpm_mux5.qip
Normal file
@@ -0,0 +1,3 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_mux5.v"]
|
||||
111
FPGA_quartus_GE/altip/lpm_mux5.v
Normal file
111
FPGA_quartus_GE/altip/lpm_mux5.v
Normal file
@@ -0,0 +1,111 @@
|
||||
// megafunction wizard: %LPM_MUX%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: LPM_MUX
|
||||
|
||||
// ============================================================
|
||||
// File Name: lpm_mux5.v
|
||||
// Megafunction Name(s):
|
||||
// LPM_MUX
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// lpm
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2013 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module lpm_mux5 (
|
||||
data0x,
|
||||
data1x,
|
||||
data2x,
|
||||
data3x,
|
||||
sel,
|
||||
result);
|
||||
|
||||
input [63:0] data0x;
|
||||
input [63:0] data1x;
|
||||
input [63:0] data2x;
|
||||
input [63:0] data3x;
|
||||
input [1:0] sel;
|
||||
output [63:0] result;
|
||||
|
||||
wire [63:0] sub_wire0;
|
||||
wire [63:0] sub_wire5 = data3x[63:0];
|
||||
wire [63:0] sub_wire4 = data2x[63:0];
|
||||
wire [63:0] sub_wire3 = data1x[63:0];
|
||||
wire [63:0] result = sub_wire0[63:0];
|
||||
wire [63:0] sub_wire1 = data0x[63:0];
|
||||
wire [255:0] sub_wire2 = {sub_wire5, sub_wire4, sub_wire3, sub_wire1};
|
||||
|
||||
lpm_mux LPM_MUX_component (
|
||||
.data (sub_wire2),
|
||||
.sel (sel),
|
||||
.result (sub_wire0)
|
||||
// synopsys translate_off
|
||||
,
|
||||
.aclr (),
|
||||
.clken (),
|
||||
.clock ()
|
||||
// synopsys translate_on
|
||||
);
|
||||
defparam
|
||||
LPM_MUX_component.lpm_size = 4,
|
||||
LPM_MUX_component.lpm_type = "LPM_MUX",
|
||||
LPM_MUX_component.lpm_width = 64,
|
||||
LPM_MUX_component.lpm_widths = 2;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: new_diagram STRING "1"
|
||||
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||
// Retrieval info: CONSTANT: LPM_SIZE NUMERIC "4"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "64"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "2"
|
||||
// Retrieval info: USED_PORT: data0x 0 0 64 0 INPUT NODEFVAL "data0x[63..0]"
|
||||
// Retrieval info: USED_PORT: data1x 0 0 64 0 INPUT NODEFVAL "data1x[63..0]"
|
||||
// Retrieval info: USED_PORT: data2x 0 0 64 0 INPUT NODEFVAL "data2x[63..0]"
|
||||
// Retrieval info: USED_PORT: data3x 0 0 64 0 INPUT NODEFVAL "data3x[63..0]"
|
||||
// Retrieval info: USED_PORT: result 0 0 64 0 OUTPUT NODEFVAL "result[63..0]"
|
||||
// Retrieval info: USED_PORT: sel 0 0 2 0 INPUT NODEFVAL "sel[1..0]"
|
||||
// Retrieval info: CONNECT: @data 0 0 64 0 data0x 0 0 64 0
|
||||
// Retrieval info: CONNECT: @data 0 0 64 64 data1x 0 0 64 0
|
||||
// Retrieval info: CONNECT: @data 0 0 64 128 data2x 0 0 64 0
|
||||
// Retrieval info: CONNECT: @data 0 0 64 192 data3x 0 0 64 0
|
||||
// Retrieval info: CONNECT: @sel 0 0 2 0 sel 0 0 2 0
|
||||
// Retrieval info: CONNECT: result 0 0 64 0 @result 0 0 64 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: lpm
|
||||
3
FPGA_quartus_GE/altip/lpm_mux6.qip
Normal file
3
FPGA_quartus_GE/altip/lpm_mux6.qip
Normal file
@@ -0,0 +1,3 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_mux6.v"]
|
||||
137
FPGA_quartus_GE/altip/lpm_mux6.v
Normal file
137
FPGA_quartus_GE/altip/lpm_mux6.v
Normal file
@@ -0,0 +1,137 @@
|
||||
// megafunction wizard: %LPM_MUX%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: LPM_MUX
|
||||
|
||||
// ============================================================
|
||||
// File Name: lpm_mux6.v
|
||||
// Megafunction Name(s):
|
||||
// LPM_MUX
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// lpm
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2013 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module lpm_mux6 (
|
||||
clock,
|
||||
data0x,
|
||||
data1x,
|
||||
data2x,
|
||||
data3x,
|
||||
data4x,
|
||||
data5x,
|
||||
data6x,
|
||||
data7x,
|
||||
sel,
|
||||
result);
|
||||
|
||||
input clock;
|
||||
input [23:0] data0x;
|
||||
input [23:0] data1x;
|
||||
input [23:0] data2x;
|
||||
input [23:0] data3x;
|
||||
input [23:0] data4x;
|
||||
input [23:0] data5x;
|
||||
input [23:0] data6x;
|
||||
input [23:0] data7x;
|
||||
input [2:0] sel;
|
||||
output [23:0] result;
|
||||
|
||||
wire [23:0] sub_wire0;
|
||||
wire [23:0] sub_wire9 = data7x[23:0];
|
||||
wire [23:0] sub_wire8 = data6x[23:0];
|
||||
wire [23:0] sub_wire7 = data5x[23:0];
|
||||
wire [23:0] sub_wire6 = data4x[23:0];
|
||||
wire [23:0] sub_wire5 = data3x[23:0];
|
||||
wire [23:0] sub_wire4 = data2x[23:0];
|
||||
wire [23:0] sub_wire3 = data1x[23:0];
|
||||
wire [23:0] result = sub_wire0[23:0];
|
||||
wire [23:0] sub_wire1 = data0x[23:0];
|
||||
wire [191:0] sub_wire2 = {sub_wire9, sub_wire8, sub_wire7, sub_wire6, sub_wire5, sub_wire4, sub_wire3, sub_wire1};
|
||||
|
||||
lpm_mux LPM_MUX_component (
|
||||
.clock (clock),
|
||||
.data (sub_wire2),
|
||||
.sel (sel),
|
||||
.result (sub_wire0)
|
||||
// synopsys translate_off
|
||||
,
|
||||
.aclr (),
|
||||
.clken ()
|
||||
// synopsys translate_on
|
||||
);
|
||||
defparam
|
||||
LPM_MUX_component.lpm_pipeline = 2,
|
||||
LPM_MUX_component.lpm_size = 8,
|
||||
LPM_MUX_component.lpm_type = "LPM_MUX",
|
||||
LPM_MUX_component.lpm_width = 24,
|
||||
LPM_MUX_component.lpm_widths = 3;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: new_diagram STRING "1"
|
||||
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "2"
|
||||
// Retrieval info: CONSTANT: LPM_SIZE NUMERIC "8"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "24"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "3"
|
||||
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
|
||||
// Retrieval info: USED_PORT: data0x 0 0 24 0 INPUT NODEFVAL "data0x[23..0]"
|
||||
// Retrieval info: USED_PORT: data1x 0 0 24 0 INPUT NODEFVAL "data1x[23..0]"
|
||||
// Retrieval info: USED_PORT: data2x 0 0 24 0 INPUT NODEFVAL "data2x[23..0]"
|
||||
// Retrieval info: USED_PORT: data3x 0 0 24 0 INPUT NODEFVAL "data3x[23..0]"
|
||||
// Retrieval info: USED_PORT: data4x 0 0 24 0 INPUT NODEFVAL "data4x[23..0]"
|
||||
// Retrieval info: USED_PORT: data5x 0 0 24 0 INPUT NODEFVAL "data5x[23..0]"
|
||||
// Retrieval info: USED_PORT: data6x 0 0 24 0 INPUT NODEFVAL "data6x[23..0]"
|
||||
// Retrieval info: USED_PORT: data7x 0 0 24 0 INPUT NODEFVAL "data7x[23..0]"
|
||||
// Retrieval info: USED_PORT: result 0 0 24 0 OUTPUT NODEFVAL "result[23..0]"
|
||||
// Retrieval info: USED_PORT: sel 0 0 3 0 INPUT NODEFVAL "sel[2..0]"
|
||||
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
|
||||
// Retrieval info: CONNECT: @data 0 0 24 0 data0x 0 0 24 0
|
||||
// Retrieval info: CONNECT: @data 0 0 24 24 data1x 0 0 24 0
|
||||
// Retrieval info: CONNECT: @data 0 0 24 48 data2x 0 0 24 0
|
||||
// Retrieval info: CONNECT: @data 0 0 24 72 data3x 0 0 24 0
|
||||
// Retrieval info: CONNECT: @data 0 0 24 96 data4x 0 0 24 0
|
||||
// Retrieval info: CONNECT: @data 0 0 24 120 data5x 0 0 24 0
|
||||
// Retrieval info: CONNECT: @data 0 0 24 144 data6x 0 0 24 0
|
||||
// Retrieval info: CONNECT: @data 0 0 24 168 data7x 0 0 24 0
|
||||
// Retrieval info: CONNECT: @sel 0 0 3 0 sel 0 0 3 0
|
||||
// Retrieval info: CONNECT: result 0 0 24 0 @result 0 0 24 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: lpm
|
||||
3
FPGA_quartus_GE/altip/lpm_muxDZ.qip
Normal file
3
FPGA_quartus_GE/altip/lpm_muxDZ.qip
Normal file
@@ -0,0 +1,3 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_muxDZ.v"]
|
||||
120
FPGA_quartus_GE/altip/lpm_muxDZ.v
Normal file
120
FPGA_quartus_GE/altip/lpm_muxDZ.v
Normal file
@@ -0,0 +1,120 @@
|
||||
// megafunction wizard: %LPM_MUX%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: LPM_MUX
|
||||
|
||||
// ============================================================
|
||||
// File Name: lpm_muxDZ.v
|
||||
// Megafunction Name(s):
|
||||
// LPM_MUX
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// lpm
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2013 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module lpm_muxDZ (
|
||||
clken,
|
||||
clock,
|
||||
data0x,
|
||||
data1x,
|
||||
sel,
|
||||
result);
|
||||
|
||||
input clken;
|
||||
input clock;
|
||||
input [127:0] data0x;
|
||||
input [127:0] data1x;
|
||||
input sel;
|
||||
output [127:0] result;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_off
|
||||
`endif
|
||||
tri1 clken;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_on
|
||||
`endif
|
||||
|
||||
wire [127:0] sub_wire0;
|
||||
wire [127:0] sub_wire3 = data1x[127:0];
|
||||
wire [127:0] result = sub_wire0[127:0];
|
||||
wire [127:0] sub_wire1 = data0x[127:0];
|
||||
wire [255:0] sub_wire2 = {sub_wire3, sub_wire1};
|
||||
wire sub_wire4 = sel;
|
||||
wire sub_wire5 = sub_wire4;
|
||||
|
||||
lpm_mux LPM_MUX_component (
|
||||
.clock (clock),
|
||||
.data (sub_wire2),
|
||||
.sel (sub_wire5),
|
||||
.clken (clken),
|
||||
.result (sub_wire0)
|
||||
// synopsys translate_off
|
||||
,
|
||||
.aclr ()
|
||||
// synopsys translate_on
|
||||
);
|
||||
defparam
|
||||
LPM_MUX_component.lpm_pipeline = 1,
|
||||
LPM_MUX_component.lpm_size = 2,
|
||||
LPM_MUX_component.lpm_type = "LPM_MUX",
|
||||
LPM_MUX_component.lpm_width = 128,
|
||||
LPM_MUX_component.lpm_widths = 1;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: new_diagram STRING "1"
|
||||
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1"
|
||||
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC "clken"
|
||||
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
|
||||
// Retrieval info: USED_PORT: data0x 0 0 128 0 INPUT NODEFVAL "data0x[127..0]"
|
||||
// Retrieval info: USED_PORT: data1x 0 0 128 0 INPUT NODEFVAL "data1x[127..0]"
|
||||
// Retrieval info: USED_PORT: result 0 0 128 0 OUTPUT NODEFVAL "result[127..0]"
|
||||
// Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL "sel"
|
||||
// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
|
||||
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
|
||||
// Retrieval info: CONNECT: @data 0 0 128 0 data0x 0 0 128 0
|
||||
// Retrieval info: CONNECT: @data 0 0 128 128 data1x 0 0 128 0
|
||||
// Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0
|
||||
// Retrieval info: CONNECT: result 0 0 128 0 @result 0 0 128 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: lpm
|
||||
3
FPGA_quartus_GE/altip/lpm_muxDZ2.qip
Normal file
3
FPGA_quartus_GE/altip/lpm_muxDZ2.qip
Normal file
@@ -0,0 +1,3 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_muxDZ2.v"]
|
||||
104
FPGA_quartus_GE/altip/lpm_muxDZ2.v
Normal file
104
FPGA_quartus_GE/altip/lpm_muxDZ2.v
Normal file
@@ -0,0 +1,104 @@
|
||||
// megafunction wizard: %LPM_MUX%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: LPM_MUX
|
||||
|
||||
// ============================================================
|
||||
// File Name: lpm_muxDZ2.v
|
||||
// Megafunction Name(s):
|
||||
// LPM_MUX
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// lpm
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2013 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module lpm_muxDZ2 (
|
||||
data0,
|
||||
data1,
|
||||
sel,
|
||||
result);
|
||||
|
||||
input data0;
|
||||
input data1;
|
||||
input sel;
|
||||
output result;
|
||||
|
||||
wire [0:0] sub_wire0;
|
||||
wire sub_wire4 = data1;
|
||||
wire [0:0] sub_wire1 = sub_wire0[0:0];
|
||||
wire result = sub_wire1;
|
||||
wire sub_wire2 = data0;
|
||||
wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
|
||||
wire sub_wire5 = sel;
|
||||
wire sub_wire6 = sub_wire5;
|
||||
|
||||
lpm_mux LPM_MUX_component (
|
||||
.data (sub_wire3),
|
||||
.sel (sub_wire6),
|
||||
.result (sub_wire0)
|
||||
// synopsys translate_off
|
||||
,
|
||||
.aclr (),
|
||||
.clken (),
|
||||
.clock ()
|
||||
// synopsys translate_on
|
||||
);
|
||||
defparam
|
||||
LPM_MUX_component.lpm_size = 2,
|
||||
LPM_MUX_component.lpm_type = "LPM_MUX",
|
||||
LPM_MUX_component.lpm_width = 1,
|
||||
LPM_MUX_component.lpm_widths = 1;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: new_diagram STRING "1"
|
||||
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||
// Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1"
|
||||
// Retrieval info: USED_PORT: data0 0 0 0 0 INPUT NODEFVAL "data0"
|
||||
// Retrieval info: USED_PORT: data1 0 0 0 0 INPUT NODEFVAL "data1"
|
||||
// Retrieval info: USED_PORT: result 0 0 0 0 OUTPUT NODEFVAL "result"
|
||||
// Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL "sel"
|
||||
// Retrieval info: CONNECT: @data 0 0 1 0 data0 0 0 0 0
|
||||
// Retrieval info: CONNECT: @data 0 0 1 1 data1 0 0 0 0
|
||||
// Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0
|
||||
// Retrieval info: CONNECT: result 0 0 0 0 @result 0 0 1 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ2.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ2.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ2.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ2.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ2_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ2_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: lpm
|
||||
3
FPGA_quartus_GE/altip/lpm_muxVDM.qip
Normal file
3
FPGA_quartus_GE/altip/lpm_muxVDM.qip
Normal file
@@ -0,0 +1,3 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_muxVDM.v"]
|
||||
171
FPGA_quartus_GE/altip/lpm_muxVDM.v
Normal file
171
FPGA_quartus_GE/altip/lpm_muxVDM.v
Normal file
@@ -0,0 +1,171 @@
|
||||
// megafunction wizard: %LPM_MUX%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: LPM_MUX
|
||||
|
||||
// ============================================================
|
||||
// File Name: lpm_muxVDM.v
|
||||
// Megafunction Name(s):
|
||||
// LPM_MUX
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// lpm
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2013 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module lpm_muxVDM (
|
||||
data0x,
|
||||
data10x,
|
||||
data11x,
|
||||
data12x,
|
||||
data13x,
|
||||
data14x,
|
||||
data15x,
|
||||
data1x,
|
||||
data2x,
|
||||
data3x,
|
||||
data4x,
|
||||
data5x,
|
||||
data6x,
|
||||
data7x,
|
||||
data8x,
|
||||
data9x,
|
||||
sel,
|
||||
result);
|
||||
|
||||
input [127:0] data0x;
|
||||
input [127:0] data10x;
|
||||
input [127:0] data11x;
|
||||
input [127:0] data12x;
|
||||
input [127:0] data13x;
|
||||
input [127:0] data14x;
|
||||
input [127:0] data15x;
|
||||
input [127:0] data1x;
|
||||
input [127:0] data2x;
|
||||
input [127:0] data3x;
|
||||
input [127:0] data4x;
|
||||
input [127:0] data5x;
|
||||
input [127:0] data6x;
|
||||
input [127:0] data7x;
|
||||
input [127:0] data8x;
|
||||
input [127:0] data9x;
|
||||
input [3:0] sel;
|
||||
output [127:0] result;
|
||||
|
||||
wire [127:0] sub_wire0;
|
||||
wire [127:0] sub_wire17 = data15x[127:0];
|
||||
wire [127:0] sub_wire16 = data14x[127:0];
|
||||
wire [127:0] sub_wire15 = data13x[127:0];
|
||||
wire [127:0] sub_wire14 = data12x[127:0];
|
||||
wire [127:0] sub_wire13 = data11x[127:0];
|
||||
wire [127:0] sub_wire12 = data10x[127:0];
|
||||
wire [127:0] sub_wire11 = data9x[127:0];
|
||||
wire [127:0] sub_wire10 = data8x[127:0];
|
||||
wire [127:0] sub_wire9 = data7x[127:0];
|
||||
wire [127:0] sub_wire8 = data6x[127:0];
|
||||
wire [127:0] sub_wire7 = data5x[127:0];
|
||||
wire [127:0] sub_wire6 = data4x[127:0];
|
||||
wire [127:0] sub_wire5 = data3x[127:0];
|
||||
wire [127:0] sub_wire4 = data2x[127:0];
|
||||
wire [127:0] sub_wire3 = data1x[127:0];
|
||||
wire [127:0] result = sub_wire0[127:0];
|
||||
wire [127:0] sub_wire1 = data0x[127:0];
|
||||
wire [2047:0] sub_wire2 = {sub_wire17, sub_wire16, sub_wire15, sub_wire14, sub_wire13, sub_wire12, sub_wire11, sub_wire10, sub_wire9, sub_wire8, sub_wire7, sub_wire6, sub_wire5, sub_wire4, sub_wire3, sub_wire1};
|
||||
|
||||
lpm_mux LPM_MUX_component (
|
||||
.data (sub_wire2),
|
||||
.sel (sel),
|
||||
.result (sub_wire0)
|
||||
// synopsys translate_off
|
||||
,
|
||||
.aclr (),
|
||||
.clken (),
|
||||
.clock ()
|
||||
// synopsys translate_on
|
||||
);
|
||||
defparam
|
||||
LPM_MUX_component.lpm_size = 16,
|
||||
LPM_MUX_component.lpm_type = "LPM_MUX",
|
||||
LPM_MUX_component.lpm_width = 128,
|
||||
LPM_MUX_component.lpm_widths = 4;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: new_diagram STRING "1"
|
||||
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||
// Retrieval info: CONSTANT: LPM_SIZE NUMERIC "16"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "4"
|
||||
// Retrieval info: USED_PORT: data0x 0 0 128 0 INPUT NODEFVAL "data0x[127..0]"
|
||||
// Retrieval info: USED_PORT: data10x 0 0 128 0 INPUT NODEFVAL "data10x[127..0]"
|
||||
// Retrieval info: USED_PORT: data11x 0 0 128 0 INPUT NODEFVAL "data11x[127..0]"
|
||||
// Retrieval info: USED_PORT: data12x 0 0 128 0 INPUT NODEFVAL "data12x[127..0]"
|
||||
// Retrieval info: USED_PORT: data13x 0 0 128 0 INPUT NODEFVAL "data13x[127..0]"
|
||||
// Retrieval info: USED_PORT: data14x 0 0 128 0 INPUT NODEFVAL "data14x[127..0]"
|
||||
// Retrieval info: USED_PORT: data15x 0 0 128 0 INPUT NODEFVAL "data15x[127..0]"
|
||||
// Retrieval info: USED_PORT: data1x 0 0 128 0 INPUT NODEFVAL "data1x[127..0]"
|
||||
// Retrieval info: USED_PORT: data2x 0 0 128 0 INPUT NODEFVAL "data2x[127..0]"
|
||||
// Retrieval info: USED_PORT: data3x 0 0 128 0 INPUT NODEFVAL "data3x[127..0]"
|
||||
// Retrieval info: USED_PORT: data4x 0 0 128 0 INPUT NODEFVAL "data4x[127..0]"
|
||||
// Retrieval info: USED_PORT: data5x 0 0 128 0 INPUT NODEFVAL "data5x[127..0]"
|
||||
// Retrieval info: USED_PORT: data6x 0 0 128 0 INPUT NODEFVAL "data6x[127..0]"
|
||||
// Retrieval info: USED_PORT: data7x 0 0 128 0 INPUT NODEFVAL "data7x[127..0]"
|
||||
// Retrieval info: USED_PORT: data8x 0 0 128 0 INPUT NODEFVAL "data8x[127..0]"
|
||||
// Retrieval info: USED_PORT: data9x 0 0 128 0 INPUT NODEFVAL "data9x[127..0]"
|
||||
// Retrieval info: USED_PORT: result 0 0 128 0 OUTPUT NODEFVAL "result[127..0]"
|
||||
// Retrieval info: USED_PORT: sel 0 0 4 0 INPUT NODEFVAL "sel[3..0]"
|
||||
// Retrieval info: CONNECT: @data 0 0 128 0 data0x 0 0 128 0
|
||||
// Retrieval info: CONNECT: @data 0 0 128 1280 data10x 0 0 128 0
|
||||
// Retrieval info: CONNECT: @data 0 0 128 1408 data11x 0 0 128 0
|
||||
// Retrieval info: CONNECT: @data 0 0 128 1536 data12x 0 0 128 0
|
||||
// Retrieval info: CONNECT: @data 0 0 128 1664 data13x 0 0 128 0
|
||||
// Retrieval info: CONNECT: @data 0 0 128 1792 data14x 0 0 128 0
|
||||
// Retrieval info: CONNECT: @data 0 0 128 1920 data15x 0 0 128 0
|
||||
// Retrieval info: CONNECT: @data 0 0 128 128 data1x 0 0 128 0
|
||||
// Retrieval info: CONNECT: @data 0 0 128 256 data2x 0 0 128 0
|
||||
// Retrieval info: CONNECT: @data 0 0 128 384 data3x 0 0 128 0
|
||||
// Retrieval info: CONNECT: @data 0 0 128 512 data4x 0 0 128 0
|
||||
// Retrieval info: CONNECT: @data 0 0 128 640 data5x 0 0 128 0
|
||||
// Retrieval info: CONNECT: @data 0 0 128 768 data6x 0 0 128 0
|
||||
// Retrieval info: CONNECT: @data 0 0 128 896 data7x 0 0 128 0
|
||||
// Retrieval info: CONNECT: @data 0 0 128 1024 data8x 0 0 128 0
|
||||
// Retrieval info: CONNECT: @data 0 0 128 1152 data9x 0 0 128 0
|
||||
// Retrieval info: CONNECT: @sel 0 0 4 0 sel 0 0 4 0
|
||||
// Retrieval info: CONNECT: result 0 0 128 0 @result 0 0 128 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: lpm
|
||||
3
FPGA_quartus_GE/altip/lpm_shiftreg0.qip
Normal file
3
FPGA_quartus_GE/altip/lpm_shiftreg0.qip
Normal file
@@ -0,0 +1,3 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.v"]
|
||||
120
FPGA_quartus_GE/altip/lpm_shiftreg0.v
Normal file
120
FPGA_quartus_GE/altip/lpm_shiftreg0.v
Normal file
@@ -0,0 +1,120 @@
|
||||
// megafunction wizard: %LPM_SHIFTREG%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: LPM_SHIFTREG
|
||||
|
||||
// ============================================================
|
||||
// File Name: lpm_shiftreg0.v
|
||||
// Megafunction Name(s):
|
||||
// LPM_SHIFTREG
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// lpm
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2013 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module lpm_shiftreg0 (
|
||||
clock,
|
||||
data,
|
||||
load,
|
||||
shiftin,
|
||||
shiftout);
|
||||
|
||||
input clock;
|
||||
input [15:0] data;
|
||||
input load;
|
||||
input shiftin;
|
||||
output shiftout;
|
||||
|
||||
wire sub_wire0;
|
||||
wire shiftout = sub_wire0;
|
||||
|
||||
lpm_shiftreg LPM_SHIFTREG_component (
|
||||
.clock (clock),
|
||||
.data (data),
|
||||
.load (load),
|
||||
.shiftin (shiftin),
|
||||
.shiftout (sub_wire0)
|
||||
// synopsys translate_off
|
||||
,
|
||||
.aclr (),
|
||||
.aset (),
|
||||
.enable (),
|
||||
.q (),
|
||||
.sclr (),
|
||||
.sset ()
|
||||
// synopsys translate_on
|
||||
);
|
||||
defparam
|
||||
LPM_SHIFTREG_component.lpm_direction = "LEFT",
|
||||
LPM_SHIFTREG_component.lpm_type = "LPM_SHIFTREG",
|
||||
LPM_SHIFTREG_component.lpm_width = 16;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: ACLR NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ASET NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: PRIVATE: LeftShift NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: ParallelDataInput NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: Q_OUT NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: SLOAD NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SSET NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: nBit NUMERIC "16"
|
||||
// Retrieval info: PRIVATE: new_diagram STRING "1"
|
||||
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||
// Retrieval info: CONSTANT: LPM_DIRECTION STRING "LEFT"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
|
||||
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
|
||||
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
|
||||
// Retrieval info: USED_PORT: load 0 0 0 0 INPUT NODEFVAL "load"
|
||||
// Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL "shiftin"
|
||||
// Retrieval info: USED_PORT: shiftout 0 0 0 0 OUTPUT NODEFVAL "shiftout"
|
||||
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
|
||||
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
|
||||
// Retrieval info: CONNECT: @load 0 0 0 0 load 0 0 0 0
|
||||
// Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0
|
||||
// Retrieval info: CONNECT: shiftout 0 0 0 0 @shiftout 0 0 0 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: lpm
|
||||
3
FPGA_quartus_GE/altip/lpm_shiftreg1.qip
Normal file
3
FPGA_quartus_GE/altip/lpm_shiftreg1.qip
Normal file
@@ -0,0 +1,3 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_shiftreg1.v"]
|
||||
112
FPGA_quartus_GE/altip/lpm_shiftreg1.v
Normal file
112
FPGA_quartus_GE/altip/lpm_shiftreg1.v
Normal file
@@ -0,0 +1,112 @@
|
||||
// megafunction wizard: %LPM_SHIFTREG%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: LPM_SHIFTREG
|
||||
|
||||
// ============================================================
|
||||
// File Name: lpm_shiftreg1.v
|
||||
// Megafunction Name(s):
|
||||
// LPM_SHIFTREG
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// lpm
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2013 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module lpm_shiftreg1 (
|
||||
clock,
|
||||
shiftin,
|
||||
q);
|
||||
|
||||
input clock;
|
||||
input shiftin;
|
||||
output [1:0] q;
|
||||
|
||||
wire [1:0] sub_wire0;
|
||||
wire [1:0] q = sub_wire0[1:0];
|
||||
|
||||
lpm_shiftreg LPM_SHIFTREG_component (
|
||||
.clock (clock),
|
||||
.shiftin (shiftin),
|
||||
.q (sub_wire0)
|
||||
// synopsys translate_off
|
||||
,
|
||||
.aclr (),
|
||||
.aset (),
|
||||
.data (),
|
||||
.enable (),
|
||||
.load (),
|
||||
.sclr (),
|
||||
.shiftout (),
|
||||
.sset ()
|
||||
// synopsys translate_on
|
||||
);
|
||||
defparam
|
||||
LPM_SHIFTREG_component.lpm_direction = "LEFT",
|
||||
LPM_SHIFTREG_component.lpm_type = "LPM_SHIFTREG",
|
||||
LPM_SHIFTREG_component.lpm_width = 2;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: ACLR NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ASET NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: PRIVATE: LeftShift NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: ParallelDataInput NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Q_OUT NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: SSET NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: nBit NUMERIC "2"
|
||||
// Retrieval info: PRIVATE: new_diagram STRING "1"
|
||||
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||
// Retrieval info: CONSTANT: LPM_DIRECTION STRING "LEFT"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "2"
|
||||
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
|
||||
// Retrieval info: USED_PORT: q 0 0 2 0 OUTPUT NODEFVAL "q[1..0]"
|
||||
// Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL "shiftin"
|
||||
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
|
||||
// Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0
|
||||
// Retrieval info: CONNECT: q 0 0 2 0 @q 0 0 2 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg1.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg1.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg1.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg1.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg1_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg1_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: lpm
|
||||
3
FPGA_quartus_GE/altip/lpm_shiftreg2.qip
Normal file
3
FPGA_quartus_GE/altip/lpm_shiftreg2.qip
Normal file
@@ -0,0 +1,3 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_shiftreg2.v"]
|
||||
112
FPGA_quartus_GE/altip/lpm_shiftreg2.v
Normal file
112
FPGA_quartus_GE/altip/lpm_shiftreg2.v
Normal file
@@ -0,0 +1,112 @@
|
||||
// megafunction wizard: %LPM_SHIFTREG%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: LPM_SHIFTREG
|
||||
|
||||
// ============================================================
|
||||
// File Name: lpm_shiftreg2.v
|
||||
// Megafunction Name(s):
|
||||
// LPM_SHIFTREG
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// lpm
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2013 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module lpm_shiftreg2 (
|
||||
clock,
|
||||
shiftin,
|
||||
shiftout);
|
||||
|
||||
input clock;
|
||||
input shiftin;
|
||||
output shiftout;
|
||||
|
||||
wire sub_wire0;
|
||||
wire shiftout = sub_wire0;
|
||||
|
||||
lpm_shiftreg LPM_SHIFTREG_component (
|
||||
.clock (clock),
|
||||
.shiftin (shiftin),
|
||||
.shiftout (sub_wire0)
|
||||
// synopsys translate_off
|
||||
,
|
||||
.aclr (),
|
||||
.aset (),
|
||||
.data (),
|
||||
.enable (),
|
||||
.load (),
|
||||
.q (),
|
||||
.sclr (),
|
||||
.sset ()
|
||||
// synopsys translate_on
|
||||
);
|
||||
defparam
|
||||
LPM_SHIFTREG_component.lpm_direction = "RIGHT",
|
||||
LPM_SHIFTREG_component.lpm_type = "LPM_SHIFTREG",
|
||||
LPM_SHIFTREG_component.lpm_width = 4;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: ACLR NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ASET NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: PRIVATE: LeftShift NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ParallelDataInput NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Q_OUT NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: SSET NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: nBit NUMERIC "4"
|
||||
// Retrieval info: PRIVATE: new_diagram STRING "1"
|
||||
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||
// Retrieval info: CONSTANT: LPM_DIRECTION STRING "RIGHT"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "4"
|
||||
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
|
||||
// Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL "shiftin"
|
||||
// Retrieval info: USED_PORT: shiftout 0 0 0 0 OUTPUT NODEFVAL "shiftout"
|
||||
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
|
||||
// Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0
|
||||
// Retrieval info: CONNECT: shiftout 0 0 0 0 @shiftout 0 0 0 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg2.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg2.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg2.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg2.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg2_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg2_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: lpm
|
||||
3
FPGA_quartus_GE/altip/lpm_shiftreg3.qip
Normal file
3
FPGA_quartus_GE/altip/lpm_shiftreg3.qip
Normal file
@@ -0,0 +1,3 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_shiftreg3.v"]
|
||||
112
FPGA_quartus_GE/altip/lpm_shiftreg3.v
Normal file
112
FPGA_quartus_GE/altip/lpm_shiftreg3.v
Normal file
@@ -0,0 +1,112 @@
|
||||
// megafunction wizard: %LPM_SHIFTREG%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: LPM_SHIFTREG
|
||||
|
||||
// ============================================================
|
||||
// File Name: lpm_shiftreg3.v
|
||||
// Megafunction Name(s):
|
||||
// LPM_SHIFTREG
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// lpm
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2013 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module lpm_shiftreg3 (
|
||||
clock,
|
||||
shiftin,
|
||||
shiftout);
|
||||
|
||||
input clock;
|
||||
input shiftin;
|
||||
output shiftout;
|
||||
|
||||
wire sub_wire0;
|
||||
wire shiftout = sub_wire0;
|
||||
|
||||
lpm_shiftreg LPM_SHIFTREG_component (
|
||||
.clock (clock),
|
||||
.shiftin (shiftin),
|
||||
.shiftout (sub_wire0)
|
||||
// synopsys translate_off
|
||||
,
|
||||
.aclr (),
|
||||
.aset (),
|
||||
.data (),
|
||||
.enable (),
|
||||
.load (),
|
||||
.q (),
|
||||
.sclr (),
|
||||
.sset ()
|
||||
// synopsys translate_on
|
||||
);
|
||||
defparam
|
||||
LPM_SHIFTREG_component.lpm_direction = "RIGHT",
|
||||
LPM_SHIFTREG_component.lpm_type = "LPM_SHIFTREG",
|
||||
LPM_SHIFTREG_component.lpm_width = 2;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: ACLR NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ASET NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: PRIVATE: LeftShift NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ParallelDataInput NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Q_OUT NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: SSET NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: nBit NUMERIC "2"
|
||||
// Retrieval info: PRIVATE: new_diagram STRING "1"
|
||||
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||
// Retrieval info: CONSTANT: LPM_DIRECTION STRING "RIGHT"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "2"
|
||||
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
|
||||
// Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL "shiftin"
|
||||
// Retrieval info: USED_PORT: shiftout 0 0 0 0 OUTPUT NODEFVAL "shiftout"
|
||||
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
|
||||
// Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0
|
||||
// Retrieval info: CONNECT: shiftout 0 0 0 0 @shiftout 0 0 0 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg3.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg3.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg3.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg3.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg3_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg3_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: lpm
|
||||
3
FPGA_quartus_GE/altip/lpm_shiftreg4.qip
Normal file
3
FPGA_quartus_GE/altip/lpm_shiftreg4.qip
Normal file
@@ -0,0 +1,3 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_shiftreg4.v"]
|
||||
112
FPGA_quartus_GE/altip/lpm_shiftreg4.v
Normal file
112
FPGA_quartus_GE/altip/lpm_shiftreg4.v
Normal file
@@ -0,0 +1,112 @@
|
||||
// megafunction wizard: %LPM_SHIFTREG%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: LPM_SHIFTREG
|
||||
|
||||
// ============================================================
|
||||
// File Name: lpm_shiftreg4.v
|
||||
// Megafunction Name(s):
|
||||
// LPM_SHIFTREG
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// lpm
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2013 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module lpm_shiftreg4 (
|
||||
clock,
|
||||
shiftin,
|
||||
shiftout);
|
||||
|
||||
input clock;
|
||||
input shiftin;
|
||||
output shiftout;
|
||||
|
||||
wire sub_wire0;
|
||||
wire shiftout = sub_wire0;
|
||||
|
||||
lpm_shiftreg LPM_SHIFTREG_component (
|
||||
.clock (clock),
|
||||
.shiftin (shiftin),
|
||||
.shiftout (sub_wire0)
|
||||
// synopsys translate_off
|
||||
,
|
||||
.aclr (),
|
||||
.aset (),
|
||||
.data (),
|
||||
.enable (),
|
||||
.load (),
|
||||
.q (),
|
||||
.sclr (),
|
||||
.sset ()
|
||||
// synopsys translate_on
|
||||
);
|
||||
defparam
|
||||
LPM_SHIFTREG_component.lpm_direction = "RIGHT",
|
||||
LPM_SHIFTREG_component.lpm_type = "LPM_SHIFTREG",
|
||||
LPM_SHIFTREG_component.lpm_width = 5;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: ACLR NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ASET NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: PRIVATE: LeftShift NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ParallelDataInput NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Q_OUT NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: SSET NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: nBit NUMERIC "5"
|
||||
// Retrieval info: PRIVATE: new_diagram STRING "1"
|
||||
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||
// Retrieval info: CONSTANT: LPM_DIRECTION STRING "RIGHT"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5"
|
||||
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
|
||||
// Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL "shiftin"
|
||||
// Retrieval info: USED_PORT: shiftout 0 0 0 0 OUTPUT NODEFVAL "shiftout"
|
||||
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
|
||||
// Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0
|
||||
// Retrieval info: CONNECT: shiftout 0 0 0 0 @shiftout 0 0 0 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: lpm
|
||||
3
FPGA_quartus_GE/altip/lpm_shiftreg5.qip
Normal file
3
FPGA_quartus_GE/altip/lpm_shiftreg5.qip
Normal file
@@ -0,0 +1,3 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_shiftreg5.v"]
|
||||
112
FPGA_quartus_GE/altip/lpm_shiftreg5.v
Normal file
112
FPGA_quartus_GE/altip/lpm_shiftreg5.v
Normal file
@@ -0,0 +1,112 @@
|
||||
// megafunction wizard: %LPM_SHIFTREG%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: LPM_SHIFTREG
|
||||
|
||||
// ============================================================
|
||||
// File Name: lpm_shiftreg5.v
|
||||
// Megafunction Name(s):
|
||||
// LPM_SHIFTREG
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// lpm
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2013 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module lpm_shiftreg5 (
|
||||
clock,
|
||||
shiftin,
|
||||
q);
|
||||
|
||||
input clock;
|
||||
input shiftin;
|
||||
output [4:0] q;
|
||||
|
||||
wire [4:0] sub_wire0;
|
||||
wire [4:0] q = sub_wire0[4:0];
|
||||
|
||||
lpm_shiftreg LPM_SHIFTREG_component (
|
||||
.clock (clock),
|
||||
.shiftin (shiftin),
|
||||
.q (sub_wire0)
|
||||
// synopsys translate_off
|
||||
,
|
||||
.aclr (),
|
||||
.aset (),
|
||||
.data (),
|
||||
.enable (),
|
||||
.load (),
|
||||
.sclr (),
|
||||
.shiftout (),
|
||||
.sset ()
|
||||
// synopsys translate_on
|
||||
);
|
||||
defparam
|
||||
LPM_SHIFTREG_component.lpm_direction = "RIGHT",
|
||||
LPM_SHIFTREG_component.lpm_type = "LPM_SHIFTREG",
|
||||
LPM_SHIFTREG_component.lpm_width = 5;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: ACLR NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ASET NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: PRIVATE: LeftShift NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ParallelDataInput NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Q_OUT NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: SSET NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: nBit NUMERIC "5"
|
||||
// Retrieval info: PRIVATE: new_diagram STRING "1"
|
||||
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||
// Retrieval info: CONSTANT: LPM_DIRECTION STRING "RIGHT"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5"
|
||||
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
|
||||
// Retrieval info: USED_PORT: q 0 0 5 0 OUTPUT NODEFVAL "q[4..0]"
|
||||
// Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL "shiftin"
|
||||
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
|
||||
// Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0
|
||||
// Retrieval info: CONNECT: q 0 0 5 0 @q 0 0 5 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg5.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg5.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg5.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg5.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg5_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg5_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: lpm
|
||||
3
FPGA_quartus_GE/altip/lpm_shiftreg6.qip
Normal file
3
FPGA_quartus_GE/altip/lpm_shiftreg6.qip
Normal file
@@ -0,0 +1,3 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_shiftreg6.v"]
|
||||
112
FPGA_quartus_GE/altip/lpm_shiftreg6.v
Normal file
112
FPGA_quartus_GE/altip/lpm_shiftreg6.v
Normal file
@@ -0,0 +1,112 @@
|
||||
// megafunction wizard: %LPM_SHIFTREG%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: LPM_SHIFTREG
|
||||
|
||||
// ============================================================
|
||||
// File Name: lpm_shiftreg6.v
|
||||
// Megafunction Name(s):
|
||||
// LPM_SHIFTREG
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// lpm
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2013 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module lpm_shiftreg6 (
|
||||
clock,
|
||||
shiftin,
|
||||
q);
|
||||
|
||||
input clock;
|
||||
input shiftin;
|
||||
output [4:0] q;
|
||||
|
||||
wire [4:0] sub_wire0;
|
||||
wire [4:0] q = sub_wire0[4:0];
|
||||
|
||||
lpm_shiftreg LPM_SHIFTREG_component (
|
||||
.clock (clock),
|
||||
.shiftin (shiftin),
|
||||
.q (sub_wire0)
|
||||
// synopsys translate_off
|
||||
,
|
||||
.aclr (),
|
||||
.aset (),
|
||||
.data (),
|
||||
.enable (),
|
||||
.load (),
|
||||
.sclr (),
|
||||
.shiftout (),
|
||||
.sset ()
|
||||
// synopsys translate_on
|
||||
);
|
||||
defparam
|
||||
LPM_SHIFTREG_component.lpm_direction = "RIGHT",
|
||||
LPM_SHIFTREG_component.lpm_type = "LPM_SHIFTREG",
|
||||
LPM_SHIFTREG_component.lpm_width = 5;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: ACLR NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ASET NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: PRIVATE: LeftShift NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ParallelDataInput NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Q_OUT NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: SSET NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: nBit NUMERIC "5"
|
||||
// Retrieval info: PRIVATE: new_diagram STRING "1"
|
||||
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||
// Retrieval info: CONSTANT: LPM_DIRECTION STRING "RIGHT"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5"
|
||||
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
|
||||
// Retrieval info: USED_PORT: q 0 0 5 0 OUTPUT NODEFVAL "q[4..0]"
|
||||
// Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL "shiftin"
|
||||
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
|
||||
// Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0
|
||||
// Retrieval info: CONNECT: q 0 0 5 0 @q 0 0 5 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: lpm
|
||||
Reference in New Issue
Block a user