IP migration and cleanup - again

2014-03-07 21:03:00 +00:00
parent a5a899af74
commit 1387bde100
441 changed files with 163358 additions and 0 deletions
--- a/FPGA_quartus_GE/ahdl2v/lpm_bustri_LONG.v
+++ b/FPGA_quartus_GE/ahdl2v/lpm_bustri_LONG.v
@@ -0,0 +1,16 @@
+// Xilinx XPort Language Converter, Version 4.1 (110)
+// 
+// AHDL    Design Source: lpm_bustri_LONG.tdf
+// Verilog Design Output: lpm_bustri_LONG.v
+// Created 05-Mar-2014 12:37 AM
+//
+// Copyright (c) 2014, Xilinx, Inc.  All Rights Reserved.
+// Xilinx Inc makes no warranty, expressed or implied, with respect to
+// the operation and/or functionality of the converted output files.
+// 
+
+//
+//
+// *** this module FAILED during conversion
+//Look at error messages.
+//