diff --git a/vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd b/vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd index e0a14e5..a38c22d 100644 --- a/vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd +++ b/vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd @@ -50,7 +50,7 @@ ENTITY DDR_CTRL IS PORT( clk_main : IN STD_LOGIC; ddr_sync_66m : IN STD_LOGIC; - fb_adr : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + fb_adr : IN UNSIGNED (31 DOWNTO 0); fb_cs1_n : IN STD_LOGIC; fb_oe_n : IN STD_LOGIC; fb_size0 : IN STD_LOGIC; @@ -58,8 +58,8 @@ ENTITY DDR_CTRL IS fb_ale : IN STD_LOGIC; fb_wr_n : IN STD_LOGIC; fifo_clr : IN STD_LOGIC; - video_control_register : IN STD_LOGIC_VECTOR (15 DOWNTO 0); - blitter_adr : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + video_control_register : IN UNSIGNED (15 DOWNTO 0); + blitter_adr : IN UNSIGNED (31 DOWNTO 0); blitter_sig : IN STD_LOGIC; blitter_wr : IN STD_LOGIC; @@ -67,29 +67,29 @@ ENTITY DDR_CTRL IS clk_33m : IN STD_LOGIC; fifo_mw : IN UNSIGNED (8 DOWNTO 0); - va : OUT STD_LOGIC_VECTOR (12 DOWNTO 0); -- video Adress bus at the DDR chips + va : OUT UNSIGNED (12 DOWNTO 0); -- video Adress bus at the DDR chips vwe_n : OUT STD_LOGIC; -- video memory write enable vras_n : OUT STD_LOGIC; -- video memory RAS vcs_n : OUT STD_LOGIC; -- video memory chip SELECT vcke : OUT STD_LOGIC; -- video memory clock enable vcas_n : OUT STD_LOGIC; -- video memory CAS - fb_le : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); - fb_vdoe : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); + fb_le : OUT UNSIGNED (3 DOWNTO 0); + fb_vdoe : OUT UNSIGNED (3 DOWNTO 0); sr_fifo_wre : OUT STD_LOGIC; sr_ddr_fb : OUT STD_LOGIC; sr_ddr_wr : OUT STD_LOGIC; sr_ddrwr_d_sel : OUT STD_LOGIC; - sr_vdmp : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + sr_vdmp : OUT UNSIGNED (7 DOWNTO 0); video_ddr_ta : OUT STD_LOGIC; sr_blitter_dack : OUT STD_LOGIC; - ba : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); + ba : OUT UNSIGNED (1 DOWNTO 0); ddrwr_d_sel1 : OUT STD_LOGIC; - vdm_sel : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); - data_in : IN STD_LOGIC_VECTOR (31 DOWNTO 0); - data_out : OUT STD_LOGIC_VECTOR (31 DOWNTO 16); + vdm_sel : OUT UNSIGNED (3 DOWNTO 0); + data_in : IN UNSIGNED (31 DOWNTO 0); + data_out : OUT UNSIGNED (31 DOWNTO 16); data_en_h : OUT STD_LOGIC; data_en_l : OUT STD_LOGIC ); @@ -102,10 +102,10 @@ ARCHITECTURE BEHAVIOUR of DDR_CTRL IS CONSTANT FIFO_HWM : INTEGER := 500; -- high water mark -- constants for bits in video_control_register - CONSTANT VRCR_VCKE : INTEGER := 0; + CONSTANT vrcr_vcke : INTEGER := 0; CONSTANT VRCR_REFRESH_ON : INTEGER := 2; CONSTANT VRCR_CONFIG_ON : INTEGER := 3; - CONSTANT VRCR_VCS : INTEGER := 1; + CONSTANT vrcr_vcs : INTEGER := 1; -- CONSTANT VRCR_FIFO_ON : INTEGER := 24; CONSTANT VRCR_BORDER_ON : INTEGER := 25; @@ -127,33 +127,33 @@ ARCHITECTURE BEHAVIOUR of DDR_CTRL IS SIGNAL ddr_access : ddr_access_t; SIGNAL ddr_state : ddr_sm_t; SIGNAL ddr_next_state : ddr_sm_t; - SIGNAL byte_sel : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL byte_sel : UNSIGNED (3 DOWNTO 0); SIGNAL sr_fifo_wre_i : STD_LOGIC; SIGNAL vcas : STD_LOGIC; SIGNAL vras : STD_LOGIC; SIGNAL vwe : STD_LOGIC; - SIGNAL mcs : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL mcs : UNSIGNED (1 DOWNTO 0); SIGNAL bus_cyc : STD_LOGIC; SIGNAL bus_cyc_end : STD_LOGIC; SIGNAL blitter_req : STD_LOGIC; - SIGNAL blitter_row_adr : STD_LOGIC_VECTOR (12 DOWNTO 0); - SIGNAL blitter_ba : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL blitter_col_adr : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL blitter_row_adr : UNSIGNED (12 DOWNTO 0); + SIGNAL blitter_ba : UNSIGNED (1 DOWNTO 0); + SIGNAL blitter_col_adr : UNSIGNED (9 DOWNTO 0); SIGNAL cpu_ddr_sync : STD_LOGIC; - SIGNAL cpu_row_adr : STD_LOGIC_VECTOR (12 DOWNTO 0); - SIGNAL cpu_ba : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL cpu_col_adr : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL cpu_row_adr : UNSIGNED (12 DOWNTO 0); + SIGNAL cpu_ba : UNSIGNED (1 DOWNTO 0); + SIGNAL cpu_col_adr : UNSIGNED (9 DOWNTO 0); SIGNAL cpu_req : STD_LOGIC; SIGNAL ddr_sel : STD_LOGIC; SIGNAL ddr_cs : STD_LOGIC; SIGNAL ddr_config : STD_LOGIC; SIGNAL fifo_req : STD_LOGIC; - SIGNAL fifo_row_adr : STD_LOGIC_VECTOR (12 DOWNTO 0); - SIGNAL fifo_ba : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL fifo_row_adr : UNSIGNED (12 DOWNTO 0); + SIGNAL fifo_ba : UNSIGNED (1 DOWNTO 0); SIGNAL fifo_col_adr : UNSIGNED(9 DOWNTO 0); SIGNAL fifo_active : STD_LOGIC; SIGNAL fifo_clr_sync : STD_LOGIC; - SIGNAL vdm_sel_i : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL vdm_sel_i : UNSIGNED (3 DOWNTO 0); SIGNAL clear_fifo_cnt : STD_LOGIC; SIGNAL stop : STD_LOGIC; SIGNAL fifo_bank_ok : STD_LOGIC; @@ -161,27 +161,27 @@ ARCHITECTURE BEHAVIOUR of DDR_CTRL IS SIGNAL ddr_refresh_req : STD_LOGIC; SIGNAL ddr_refresh_sig : UNSIGNED(3 DOWNTO 0); SIGNAL need_refresh : STD_LOGIC; - SIGNAL video_base_l_d : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL video_base_l_d : UNSIGNED (7 DOWNTO 0); SIGNAL video_base_l : STD_LOGIC; - SIGNAL video_base_m_d : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL video_base_m_d : UNSIGNED (7 DOWNTO 0); SIGNAL video_base_m : STD_LOGIC; - SIGNAL video_base_h_d : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL video_base_h_d : UNSIGNED (7 DOWNTO 0); SIGNAL video_base_h : STD_LOGIC; - SIGNAL video_base_x_d : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL video_base_x_d : UNSIGNED (2 DOWNTO 0); SIGNAL video_adr_cnt : UNSIGNED(22 DOWNTO 0); SIGNAL video_cnt_l : STD_LOGIC; SIGNAL video_cnt_m : STD_LOGIC; SIGNAL video_cnt_h : STD_LOGIC; - SIGNAL video_base_adr : STD_LOGIC_VECTOR (22 DOWNTO 0); - SIGNAL video_act_adr : STD_LOGIC_VECTOR (26 DOWNTO 0); - SIGNAL fb_adr_i : STD_LOGIC_VECTOR (32 DOWNTO 0); + SIGNAL video_base_adr : UNSIGNED (22 DOWNTO 0); + SIGNAL video_act_adr : UNSIGNED (26 DOWNTO 0); + SIGNAL fb_adr_i : UNSIGNED (32 DOWNTO 0); - SIGNAL va_s : STD_LOGIC_VECTOR (12 DOWNTO 0); - SIGNAL va_p : STD_LOGIC_VECTOR (12 DOWNTO 0); - SIGNAL ba_s : STD_LOGIC_VECTOR (1 DOWNTO 0) ; - SIGNAL ba_p : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL tsiz : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL va_s : UNSIGNED (12 DOWNTO 0); + SIGNAL va_p : UNSIGNED (12 DOWNTO 0); + SIGNAL ba_s : UNSIGNED (1 DOWNTO 0) ; + SIGNAL ba_p : UNSIGNED (1 DOWNTO 0); + SIGNAL tsiz : UNSIGNED (1 DOWNTO 0); BEGIN tsiz <= fb_size1 & fb_size0; WITH tsiz SELECT @@ -485,8 +485,8 @@ BEGIN blitter_req <= blitter_sig AND NOT video_control_register(VRCR_CONFIG_ON) AND - video_control_register(VRCR_VCKE) AND - video_control_register(VRCR_VCS); + video_control_register(vrcr_vcke) AND + video_control_register(vrcr_vcs); fifo_clr_sync <= fifo_clr; clear_fifo_cnt <= fifo_clr_sync OR NOT fifo_active; @@ -500,20 +500,20 @@ BEGIN clear_fifo_cnt = '0' AND stop = '0' AND ddr_config = '0' AND - video_control_register(VRCR_VCKE) = '1' AND - video_control_register(VRCR_VCS) = '1' THEN + video_control_register(vrcr_vcke) = '1' AND + video_control_register(vrcr_vcs) = '1' THEN fifo_req <= '1'; ELSE fifo_req <= '1'; END IF; IF clear_fifo_cnt = '1' THEN - video_adr_cnt <= UNSIGNED(video_base_adr); + video_adr_cnt <= video_base_adr; ELSIF sr_fifo_wre_i = '1' THEN video_adr_cnt <= video_adr_cnt + 1; END IF; - IF mcs = "10" AND video_control_register(VRCR_VCKE) = '1' AND video_control_register(VRCR_VCS) = '1' THEN + IF mcs = "10" AND video_control_register(vrcr_vcke) = '1' AND video_control_register(vrcr_vcs) = '1' THEN cpu_ddr_sync <= '1'; ELSE cpu_ddr_sync <= '0'; @@ -592,7 +592,7 @@ BEGIN va_s(9 DOWNTO 0) <= cpu_col_adr; ba_s <= cpu_ba; ELSIF fifo_active = '1' THEN - va_s(9 DOWNTO 0) <= STD_LOGIC_VECTOR (fifo_col_adr); + va_s(9 DOWNTO 0) <= UNSIGNED (fifo_col_adr); ba_s <= fifo_ba; ELSIF ddr_access = ddr_access_blitter THEN va_s(9 DOWNTO 0) <= blitter_col_adr; @@ -607,7 +607,7 @@ BEGIN END IF; ELSIF ddr_state = ds_t5r AND fifo_req = '1' AND fifo_bank_ok = '1' THEN va_s(10) <= '0'; - va_s(9 DOWNTO 0) <= STD_LOGIC_VECTOR (fifo_col_adr); + va_s(9 DOWNTO 0) <= UNSIGNED (fifo_col_adr); ba_s <= fifo_ba; ELSIF ddr_state = ds_t5r THEN va_s(10) <= '1'; @@ -646,7 +646,7 @@ BEGIN sr_ddrwr_d_sel <= '1'; ELSIF ddr_state = ds_t9w AND fifo_req = '1' AND fifo_bank_ok = '1' THEN va_s(10) <= '0'; - va_s(9 DOWNTO 0) <= STD_LOGIC_VECTOR (fifo_col_adr); + va_s(9 DOWNTO 0) <= UNSIGNED (fifo_col_adr); ba_s <= fifo_ba; ELSIF ddr_state = ds_t9w THEN va_s(10) <= '0'; @@ -656,7 +656,7 @@ BEGIN va_s(10) <= '1'; ELSIF ddr_state = ds_t5f AND fifo_req = '1' THEN va_s(10) <= '0'; - va_s(9 DOWNTO 0) <= STD_LOGIC_VECTOR (fifo_col_adr + "100"); + va_s(9 DOWNTO 0) <= UNSIGNED (fifo_col_adr + "100"); ba_s <= fifo_ba; ELSIF ddr_state = ds_t5f THEN va_s(10) <= '0'; @@ -668,7 +668,7 @@ BEGIN va_s(10) <= '1'; ELSIF ddr_state = ds_t7f AND fifo_req = '1' THEN va_s(10) <= '0'; - va_s(9 DOWNTO 0) <= STD_LOGIC_VECTOR (fifo_col_adr + "100"); + va_s(9 DOWNTO 0) <= UNSIGNED (fifo_col_adr + "100"); ba_s <= fifo_ba; ELSIF ddr_state = ds_t7f THEN va_s(10) <= '1'; @@ -676,7 +676,7 @@ BEGIN va_s(10) <= '1'; ELSIF ddr_state = ds_t9f AND fifo_req = '1' THEN va_p(10) <= '0'; - va_p(9 DOWNTO 0) <= STD_LOGIC_VECTOR (fifo_col_adr + "100"); + va_p(9 DOWNTO 0) <= UNSIGNED (fifo_col_adr + "100"); ba_p <= fifo_ba; ELSIF ddr_state = ds_t9f THEN va_s(10) <= '1'; @@ -739,46 +739,46 @@ BEGIN sr_fifo_wre <= sr_fifo_wre_i; va <= data_in(26 DOWNTO 14) WHEN ddr_state = ds_t2a AND ddr_sel = '1' AND fb_wr_n = '0' ELSE - data_in(26 DOWNTO 14) WHEN ddr_state = ds_t2a AND ddr_sel = '1' AND (fb_size0 = '0' OR fb_size1= '0') ELSE - va_p WHEN ddr_state = ds_t2a ELSE - data_in(26 DOWNTO 14) WHEN ddr_state = ds_t10f AND fb_wr_n = '0' AND data_in(13 DOWNTO 12) = fifo_ba ELSE - data_in(26 DOWNTO 14) WHEN ddr_state = ds_t10f AND (fb_size0 = '0' OR fb_size1= '0') AND data_in(13 DOWNTO 12) = fifo_ba ELSE - va_p WHEN ddr_state = ds_t10f ELSE - "0010000000000" WHEN ddr_state = ds_r2 AND ddr_refresh_sig = x"9" ELSE va_s; + data_in(26 DOWNTO 14) WHEN ddr_state = ds_t2a AND ddr_sel = '1' AND (fb_size0 = '0' OR fb_size1= '0') ELSE + va_p WHEN ddr_state = ds_t2a ELSE + data_in(26 DOWNTO 14) WHEN ddr_state = ds_t10f AND fb_wr_n = '0' AND data_in(13 DOWNTO 12) = fifo_ba ELSE + data_in(26 DOWNTO 14) WHEN ddr_state = ds_t10f AND (fb_size0 = '0' OR fb_size1= '0') AND data_in(13 DOWNTO 12) = fifo_ba ELSE + va_p WHEN ddr_state = ds_t10f ELSE + "0010000000000" WHEN ddr_state = ds_r2 AND ddr_refresh_sig = x"9" ELSE va_s; ba <= data_in(13 DOWNTO 12) WHEN ddr_state = ds_t2a AND ddr_sel = '1' AND fb_wr_n = '0' ELSE - data_in(13 DOWNTO 12) WHEN ddr_state = ds_t2a AND ddr_sel = '1' AND (fb_size0 = '0' OR fb_size1= '0') ELSE - ba_p WHEN ddr_state = ds_t2a ELSE - data_in(13 DOWNTO 12) WHEN ddr_state = ds_t10f AND fb_wr_n = '0' AND data_in(13 DOWNTO 12) = fifo_ba ELSE - data_in(13 DOWNTO 12) WHEN ddr_state = ds_t10f AND (fb_size0 = '0' OR fb_size1= '0') AND data_in(13 DOWNTO 12) = fifo_ba ELSE - ba_p WHEN ddr_state = ds_t10f ELSE ba_s; + data_in(13 DOWNTO 12) WHEN ddr_state = ds_t2a AND ddr_sel = '1' AND (fb_size0 = '0' OR fb_size1= '0') ELSE + ba_p WHEN ddr_state = ds_t2a ELSE + data_in(13 DOWNTO 12) WHEN ddr_state = ds_t10f AND fb_wr_n = '0' AND data_in(13 DOWNTO 12) = fifo_ba ELSE + data_in(13 DOWNTO 12) WHEN ddr_state = ds_t10f AND (fb_size0 = '0' OR fb_size1= '0') AND data_in(13 DOWNTO 12) = fifo_ba ELSE + ba_p WHEN ddr_state = ds_t10f ELSE ba_s; vras <= '1' WHEN ddr_state = ds_t2a AND ddr_sel = '1' AND fb_wr_n = '0' ELSE - '1' WHEN ddr_state = ds_t2a AND ddr_sel = '1' AND (fb_size0 = '0' OR fb_size1= '0') ELSE - '1' WHEN ddr_state = ds_t2a AND ddr_access = ddr_access_fifo AND fifo_req = '1' ELSE - '1' WHEN ddr_state = ds_t2a AND ddr_access = ddr_access_blitter AND blitter_req = '1' ELSE - '1' WHEN ddr_state = ds_t2b ELSE - '1' WHEN ddr_state = ds_t10f AND fb_wr_n = '0' AND data_in(13 DOWNTO 12) = fifo_ba ELSE - '1' WHEN ddr_state = ds_t10f AND (fb_size0 = '0' OR fb_size1= '0') AND data_in(13 DOWNTO 12) = fifo_ba ELSE - data_in(18) AND NOT fb_wr_n AND NOT fb_size0 AND NOT fb_size1 WHEN ddr_state = ds_c7 ELSE - '1' WHEN ddr_state = ds_cb6 ELSE - '1' WHEN ddr_state = ds_cb8 ELSE - '1' WHEN ddr_state = ds_r2 ELSE '0'; + '1' WHEN ddr_state = ds_t2a AND ddr_sel = '1' AND (fb_size0 = '0' OR fb_size1= '0') ELSE + '1' WHEN ddr_state = ds_t2a AND ddr_access = ddr_access_fifo AND fifo_req = '1' ELSE + '1' WHEN ddr_state = ds_t2a AND ddr_access = ddr_access_blitter AND blitter_req = '1' ELSE + '1' WHEN ddr_state = ds_t2b ELSE + '1' WHEN ddr_state = ds_t10f AND fb_wr_n = '0' AND data_in(13 DOWNTO 12) = fifo_ba ELSE + '1' WHEN ddr_state = ds_t10f AND (fb_size0 = '0' OR fb_size1= '0') AND data_in(13 DOWNTO 12) = fifo_ba ELSE + data_in(18) AND NOT fb_wr_n AND NOT fb_size0 AND NOT fb_size1 WHEN ddr_state = ds_c7 ELSE + '1' WHEN ddr_state = ds_cb6 ELSE + '1' WHEN ddr_state = ds_cb8 ELSE + '1' WHEN ddr_state = ds_r2 ELSE '0'; vcas <= '1' WHEN ddr_state = ds_t4r ELSE - '1' WHEN ddr_state = ds_t6w ELSE - '1' WHEN ddr_state = ds_t4f ELSE - '1' WHEN ddr_state = ds_t6f ELSE - '1' WHEN ddr_state = ds_t8f ELSE - '1' WHEN ddr_state = ds_t10f AND vras = '0' ELSE - data_in(17) AND NOT fb_wr_n AND NOT fb_size0 AND NOT fb_size1 WHEN ddr_state = ds_c7 ELSE - '1' WHEN ddr_state = ds_r2 AND ddr_refresh_sig /= x"9" ELSE '0'; + '1' WHEN ddr_state = ds_t6w ELSE + '1' WHEN ddr_state = ds_t4f ELSE + '1' WHEN ddr_state = ds_t6f ELSE + '1' WHEN ddr_state = ds_t8f ELSE + '1' WHEN ddr_state = ds_t10f AND vras = '0' ELSE + data_in(17) AND NOT fb_wr_n AND NOT fb_size0 AND NOT fb_size1 WHEN ddr_state = ds_c7 ELSE + '1' WHEN ddr_state = ds_r2 AND ddr_refresh_sig /= x"9" ELSE '0'; vwe <= '1' WHEN ddr_state = ds_t6w ELSE - data_in(16) AND NOT fb_wr_n AND NOT fb_size0 AND NOT fb_size1 WHEN ddr_state = ds_c7 ELSE - '1' WHEN ddr_state = ds_cb6 ELSE - '1' WHEN ddr_state = ds_cb8 ELSE - '1' WHEN ddr_state = ds_r2 AND ddr_refresh_sig = x"9" ELSE '0'; + data_in(16) AND NOT fb_wr_n AND NOT fb_size0 AND NOT fb_size1 WHEN ddr_state = ds_c7 ELSE + '1' WHEN ddr_state = ds_cb6 ELSE + '1' WHEN ddr_state = ds_cb8 ELSE + '1' WHEN ddr_state = ds_r2 AND ddr_refresh_sig = x"9" ELSE '0'; -- DDR controller: -- VIDEO RAM CONTROL REGISTER (IS IN VIDEO_MUX_CTR) @@ -801,8 +801,8 @@ BEGIN blitter_ba <= blitter_adr(13 DOWNTO 12); blitter_col_adr <= blitter_adr(11 DOWNTO 2); - fifo_row_adr <= STD_LOGIC_VECTOR (video_adr_cnt(22 DOWNTO 10)); - fifo_ba <= STD_LOGIC_VECTOR (video_adr_cnt(9 DOWNTO 8)); + fifo_row_adr <= video_adr_cnt(22 DOWNTO 10); + fifo_ba <= video_adr_cnt(9 DOWNTO 8); fifo_col_adr <= video_adr_cnt(7 DOWNTO 0) & "00"; video_base_adr(22 DOWNTO 20) <= video_base_x_d; @@ -814,7 +814,7 @@ BEGIN vdm_sel_i <= video_base_l_d(3 DOWNTO 0); -- Current video address: - video_act_adr(26 DOWNTO 4) <= STD_LOGIC_VECTOR (video_adr_cnt - fifo_mw); + video_act_adr(26 DOWNTO 4) <= video_adr_cnt - fifo_mw; video_act_adr(3 DOWNTO 0) <= vdm_sel_i; p_video_regs : PROCESS @@ -822,7 +822,7 @@ BEGIN BEGIN WAIT UNTIL RISING_EDGE(clk_33m); IF video_base_l = '1' AND fb_wr_n = '0' AND byte_sel(1) = '1' THEN - video_base_l_d <= data_in(23 DOWNTO 16); -- 16 byte boarders. + video_base_l_d <= data_in(23 DOWNTO 16); -- 16 byte borders END IF; IF video_base_m = '1' AND fb_wr_n = '0' AND byte_sel(3) = '1' THEN @@ -849,16 +849,16 @@ BEGIN video_cnt_h <= '1' WHEN fb_cs1_n = '0' AND fb_adr_i(15 DOWNTO 0) = x"8204" ELSE '0'; -- x"FF8205". data_out(31 DOWNTO 24) <= "00000" & video_base_x_d WHEN video_base_h = '1' ELSE - "00000" & video_act_adr(26 DOWNTO 24) WHEN video_cnt_h = '1' ELSE (OTHERS => '0'); + "00000" & video_act_adr(26 DOWNTO 24) WHEN video_cnt_h = '1' ELSE (OTHERS => '0'); data_en_h <= (video_base_h OR video_cnt_h) AND NOT fb_oe_n; data_out(23 DOWNTO 16) <= video_base_l_d WHEN video_base_l = '1' ELSE - video_base_m_d WHEN video_base_m = '1' ELSE - video_base_h_d WHEN video_base_h = '1' ELSE - video_act_adr(7 DOWNTO 0) WHEN video_cnt_l = '1' ELSE - video_act_adr(15 DOWNTO 8) WHEN video_cnt_m = '1' ELSE - video_act_adr(23 DOWNTO 16) WHEN video_cnt_h = '1' ELSE (OTHERS => '0'); + video_base_m_d WHEN video_base_m = '1' ELSE + video_base_h_d WHEN video_base_h = '1' ELSE + video_act_adr(7 DOWNTO 0) WHEN video_cnt_l = '1' ELSE + video_act_adr(15 DOWNTO 8) WHEN video_cnt_m = '1' ELSE + video_act_adr(23 DOWNTO 16) WHEN video_cnt_h = '1' ELSE (OTHERS => '0'); data_en_l <= (video_base_l OR video_base_m OR video_base_h OR video_cnt_l OR video_cnt_m OR video_cnt_h) AND NOT fb_oe_n; END ARCHITECTURE BEHAVIOUR; diff --git a/vhdl/rtl/vhdl/Firebee/Firebee.vhd b/vhdl/rtl/vhdl/Firebee/Firebee.vhd index 1a25a76..0053e44 100644 --- a/vhdl/rtl/vhdl/Firebee/Firebee.vhd +++ b/vhdl/rtl/vhdl/Firebee/Firebee.vhd @@ -792,45 +792,45 @@ BEGIN I_DDR_CTRL: DDR_CTRL PORT MAP( - clk_main => clk_main, - ddr_sync_66m => ddr_sync_66m, - fb_adr => fb_adr, - fb_cs1_n => fb_cs_n(1), - fb_oe_n => fb_oe_n, - fb_size0 => fb_size(0), - fb_size1 => fb_size(1), - fb_ale => fb_ale, - fb_wr_n => fb_wr_n, - blitter_adr => blitter_adr, - blitter_sig => blitter_sig, - blitter_wr => blitter_wr, - SR_BLITTER_DACK => blitter_dack_sr, - ba => ba, - va => va, - fb_le => fb_le, - clk_33m => clk_33m, - vras_n => vras_n, - vcas_n => vcas_n, - vwe_n => vwe_n, - vcs_n => vcs_n, - fifo_clr => fifo_clr, - DDRCLK0 => clk_ddr(0), - video_control_register => video_ram_ctr, - vcke => vcke, - DATA_IN => fb_ad, - DATA_OUT => data_out_ddr_ctrl, - DATA_EN_H => data_en_h_ddr_ctrl, - DATA_EN_L => data_en_l_ddr_ctrl, - vdm_sel => vdm_sel, - fifo_mw => fifo_mw, - fb_vdoe => fb_vdoe, - sr_fifo_wre => sr_fifo_wre, - sr_ddr_fb => sr_ddr_fb, - sr_ddr_wr => sr_ddr_wr, - sr_ddrwr_d_sel => sr_ddrwr_d_sel, - sr_vdmp => sr_vdmp, - video_ddr_ta => video_ddr_ta, - ddrwr_d_sel1 => ddrwr_d_sel(1) + clk_main => clk_main, + ddr_sync_66m => ddr_sync_66m, + fb_adr => UNSIGNED(fb_adr), + fb_cs1_n => fb_cs_n(1), + fb_oe_n => fb_oe_n, + fb_size0 => fb_size(0), + fb_size1 => fb_size(1), + fb_ale => fb_ale, + fb_wr_n => fb_wr_n, + blitter_adr => UNSIGNED(blitter_adr), + blitter_sig => blitter_sig, + blitter_wr => blitter_wr, + SR_BLITTER_DACK => blitter_dack_sr, + STD_LOGIC_VECTOR(ba) => ba, + STD_LOGIC_VECTOR(va) => va, + STD_LOGIC_VECTOR(fb_le) => fb_le, + clk_33m => clk_33m, + vras_n => vras_n, + vcas_n => vcas_n, + vwe_n => vwe_n, + vcs_n => vcs_n, + fifo_clr => fifo_clr, + DDRCLK0 => clk_ddr(0), + video_control_register => UNSIGNED(video_ram_ctr), + vcke => vcke, + DATA_IN => UNSIGNED(fb_ad), + STD_LOGIC_VECTOR(DATA_OUT) => data_out_ddr_ctrl, + DATA_EN_H => data_en_h_ddr_ctrl, + DATA_EN_L => data_en_l_ddr_ctrl, + STD_LOGIC_VECTOR(vdm_sel) => vdm_sel, + fifo_mw => fifo_mw, + STD_LOGIC_VECTOR(fb_vdoe) => fb_vdoe, + sr_fifo_wre => sr_fifo_wre, + sr_ddr_fb => sr_ddr_fb, + sr_ddr_wr => sr_ddr_wr, + sr_ddrwr_d_sel => sr_ddrwr_d_sel, + STD_LOGIC_VECTOR(sr_vdmp) => sr_vdmp, + video_ddr_ta => video_ddr_ta, + ddrwr_d_sel1 => ddrwr_d_sel(1) ); -- I_BLITTER: FBEE_BLITTER diff --git a/vhdl/rtl/vhdl/Firebee/Firebee_pkg.vhd b/vhdl/rtl/vhdl/Firebee/Firebee_pkg.vhd index 3a53f43..9174ef1 100644 --- a/vhdl/rtl/vhdl/Firebee/Firebee_pkg.vhd +++ b/vhdl/rtl/vhdl/Firebee/Firebee_pkg.vhd @@ -66,8 +66,8 @@ PACKAGE firebee_pkg IS FB_AD_EN_31_16 : OUT STD_LOGIC; -- Hi word. FB_AD_EN_15_0 : OUT STD_LOGIC; -- Low word. FB_ALE : IN STD_LOGIC; - fb_cs_n : IN STD_LOGIC_VECTOR(3 DOWNTO 1); - fb_oe_n : IN STD_LOGIC; + fb_cs_n : IN STD_LOGIC_VECTOR(3 DOWNTO 1); + fb_oe_n : IN STD_LOGIC; fb_wr_n : IN STD_LOGIC; fb_size1 : IN STD_LOGIC; fb_size0 : IN STD_LOGIC; @@ -83,10 +83,10 @@ PACKAGE firebee_pkg IS BLUE : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); VSYNC : OUT STD_LOGIC; HSYNC : OUT STD_LOGIC; - sync_n : OUT STD_LOGIC; - blank_n : OUT STD_LOGIC; + sync_n : OUT STD_LOGIC; + blank_n : OUT STD_LOGIC; - pd_vga_n : OUT STD_LOGIC; + pd_vga_n : OUT STD_LOGIC; VIDEO_MOD_TA : OUT STD_LOGIC; VD_VZ : OUT STD_LOGIC_VECTOR(127 DOWNTO 0); @@ -107,9 +107,9 @@ PACKAGE firebee_pkg IS COMPONENT VIDEO_CTRL PORT( CLK_MAIN : IN STD_LOGIC; - fb_cs_n : IN STD_LOGIC_VECTOR(2 DOWNTO 1); - fb_wr_n : IN STD_LOGIC; - fb_oe_n : IN STD_LOGIC; + fb_cs_n : IN STD_LOGIC_VECTOR(2 DOWNTO 1); + fb_wr_n : IN STD_LOGIC; + fb_oe_n : IN STD_LOGIC; FB_SIZE : IN STD_LOGIC_VECTOR(1 DOWNTO 0); FB_ADR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); CLK33M : IN STD_LOGIC; @@ -129,9 +129,9 @@ PACKAGE firebee_pkg IS CLUT_MUX_ADR : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); HSYNC : OUT STD_LOGIC; VSYNC : OUT STD_LOGIC; - blank_n : OUT STD_LOGIC; - sync_n : OUT STD_LOGIC; - pd_vga_n : OUT STD_LOGIC; + blank_n : OUT STD_LOGIC; + sync_n : OUT STD_LOGIC; + pd_vga_n : OUT STD_LOGIC; FIFO_RDE : OUT STD_LOGIC; COLOR2 : OUT STD_LOGIC; COLOR4 : OUT STD_LOGIC; @@ -158,46 +158,51 @@ PACKAGE firebee_pkg IS COMPONENT DDR_CTRL is PORT( - CLK_MAIN : IN STD_LOGIC; - DDR_SYNC_66M : IN STD_LOGIC; - FB_ADR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - fb_cs1_n : IN STD_LOGIC; - FB_OE_n : IN STD_LOGIC; - fb_size0 : IN STD_LOGIC; - fb_size1 : IN STD_LOGIC; - FB_ALE : IN STD_LOGIC; - fb_wr_n : IN STD_LOGIC; - FIFO_CLR : IN STD_LOGIC; - video_control_register : IN STD_LOGIC_VECTOR(15 DOWNTO 0); - BLITTER_ADR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - BLITTER_SIG : IN STD_LOGIC; - BLITTER_WR : IN STD_LOGIC; - DDRCLK0 : IN STD_LOGIC; - CLK_33M : IN STD_LOGIC; - FIFO_MW : IN UNSIGNED (8 DOWNTO 0); - VA : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); - vwe_n : OUT STD_LOGIC; - vras_n : OUT STD_LOGIC; - vcs_n : OUT STD_LOGIC; - VCKE : OUT STD_LOGIC; - vcas_n : OUT STD_LOGIC; - FB_LE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - FB_VDOE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - SR_FIFO_WRE : OUT STD_LOGIC; - SR_DDR_FB : OUT STD_LOGIC; - SR_DDR_WR : OUT STD_LOGIC; - SR_DDRWR_D_SEL : OUT STD_LOGIC; - SR_VDMP : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); - VIDEO_DDR_TA : OUT STD_LOGIC; - SR_BLITTER_DACK : OUT STD_LOGIC; - BA : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); - DDRWR_D_SEL1 : OUT STD_LOGIC; - VDM_SEL : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - DATA_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - DATA_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 16); - DATA_EN_H : OUT STD_LOGIC; - DATA_EN_L : OUT STD_LOGIC - ); + clk_main : IN STD_LOGIC; + ddr_sync_66m : IN STD_LOGIC; + fb_adr : IN UNSIGNED (31 DOWNTO 0); + fb_cs1_n : IN STD_LOGIC; + fb_oe_n : IN STD_LOGIC; + fb_size0 : IN STD_LOGIC; + fb_size1 : IN STD_LOGIC; + fb_ale : IN STD_LOGIC; + fb_wr_n : IN STD_LOGIC; + fifo_clr : IN STD_LOGIC; + video_control_register : IN UNSIGNED (15 DOWNTO 0); + blitter_adr : IN UNSIGNED (31 DOWNTO 0); + blitter_sig : IN STD_LOGIC; + blitter_wr : IN STD_LOGIC; + + ddrclk0 : IN STD_LOGIC; + clk_33m : IN STD_LOGIC; + fifo_mw : IN UNSIGNED (8 DOWNTO 0); + + va : OUT UNSIGNED (12 DOWNTO 0); -- video Adress bus at the DDR chips + vwe_n : OUT STD_LOGIC; -- video memory write enable + vras_n : OUT STD_LOGIC; -- video memory RAS + vcs_n : OUT STD_LOGIC; -- video memory chip SELECT + vcke : OUT STD_LOGIC; -- video memory clock enable + vcas_n : OUT STD_LOGIC; -- video memory CAS + + fb_le : OUT UNSIGNED (3 DOWNTO 0); + fb_vdoe : OUT UNSIGNED (3 DOWNTO 0); + + sr_fifo_wre : OUT STD_LOGIC; + sr_ddr_fb : OUT STD_LOGIC; + sr_ddr_wr : OUT STD_LOGIC; + sr_ddrwr_d_sel : OUT STD_LOGIC; + sr_vdmp : OUT UNSIGNED (7 DOWNTO 0); + + video_ddr_ta : OUT STD_LOGIC; + sr_blitter_dack : OUT STD_LOGIC; + ba : OUT UNSIGNED (1 DOWNTO 0); + ddrwr_d_sel1 : OUT STD_LOGIC; + vdm_sel : OUT UNSIGNED (3 DOWNTO 0); + data_in : IN UNSIGNED (31 DOWNTO 0); + data_out : OUT UNSIGNED (31 DOWNTO 16); + data_en_h : OUT STD_LOGIC; + data_en_l : OUT STD_LOGIC + ); END COMPONENT; COMPONENT INTHANDLER @@ -205,11 +210,11 @@ PACKAGE firebee_pkg IS CLK_MAIN : IN STD_LOGIC; RESETn : IN STD_LOGIC; FB_ADR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - fb_cs_n : IN STD_LOGIC_VECTOR(2 DOWNTO 1); + fb_cs_n : IN STD_LOGIC_VECTOR(2 DOWNTO 1); fb_size0 : IN STD_LOGIC; fb_size1 : IN STD_LOGIC; fb_wr_n : IN STD_LOGIC; - fb_oe_n : IN STD_LOGIC; + fb_oe_n : IN STD_LOGIC; FB_AD_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0); FB_AD_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); FB_AD_EN_31_24 : OUT STD_LOGIC; @@ -219,16 +224,16 @@ PACKAGE firebee_pkg IS PIC_INT : IN STD_LOGIC; E0_INT : IN STD_LOGIC; DVI_INT : IN STD_LOGIC; - pci_inta_n : IN STD_LOGIC; - pci_intb_n : IN STD_LOGIC; - pci_intc_n : IN STD_LOGIC; - pci_intd_n : IN STD_LOGIC; - mfp_int_n : IN STD_LOGIC; + pci_inta_n : IN STD_LOGIC; + pci_intb_n : IN STD_LOGIC; + pci_intc_n : IN STD_LOGIC; + pci_intd_n : IN STD_LOGIC; + mfp_int_n : IN STD_LOGIC; DSP_INT : IN STD_LOGIC; VSYNC : IN STD_LOGIC; HSYNC : IN STD_LOGIC; DRQ_DMA : IN STD_LOGIC; - irq_n : OUT STD_LOGIC_VECTOR(7 DOWNTO 2); + irq_n : OUT STD_LOGIC_VECTOR(7 DOWNTO 2); INT_HANDLER_TA : OUT STD_LOGIC; FBEE_CONF : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); TIN0 : OUT STD_LOGIC @@ -244,9 +249,9 @@ PACKAGE firebee_pkg IS FB_ADR : IN STD_LOGIC_VECTOR(26 DOWNTO 0); FB_ALE : IN STD_LOGIC; FB_SIZE : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - fb_cs_n : IN STD_LOGIC_VECTOR(2 DOWNTO 1); - fb_oe_n : IN STD_LOGIC; - fb_wr_n : IN STD_LOGIC; + fb_cs_n : IN STD_LOGIC_VECTOR(2 DOWNTO 1); + fb_oe_n : IN STD_LOGIC; + fb_wr_n : IN STD_LOGIC; FB_AD_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0); FB_AD_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); FB_AD_EN_31_24 : OUT STD_LOGIC; @@ -296,7 +301,7 @@ PACKAGE firebee_pkg IS FB_ADR : IN STD_LOGIC_VECTOR(19 DOWNTO 5); FB_CS1n : IN STD_LOGIC; - fb_wr_n : IN STD_LOGIC; + fb_wr_n : IN STD_LOGIC; FB_B0 : IN STD_LOGIC; FB_B1 : IN STD_LOGIC; @@ -342,9 +347,9 @@ PACKAGE firebee_pkg IS FB_ALE : IN STD_LOGIC; fb_size1 : IN STD_LOGIC; fb_size0 : IN STD_LOGIC; - fb_cs_n : IN STD_LOGIC_VECTOR(3 DOWNTO 1); - fb_oe_n : IN STD_LOGIC; - fb_wr_n : IN STD_LOGIC; + fb_cs_n : IN STD_LOGIC_VECTOR(3 DOWNTO 1); + fb_oe_n : IN STD_LOGIC; + fb_wr_n : IN STD_LOGIC; DATA_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0); DATA_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); DATA_EN : OUT STD_LOGIC; @@ -364,8 +369,8 @@ PACKAGE firebee_pkg IS PORT( CLK_33M : IN STD_LOGIC; CLK_MAIN : IN STD_LOGIC; - fb_oe_n : IN STD_LOGIC; - fb_wr_n : IN STD_LOGIC; + fb_oe_n : IN STD_LOGIC; + fb_wr_n : IN STD_LOGIC; FB_CS1n : IN STD_LOGIC; FB_CS2n : IN STD_LOGIC; fb_size0 : IN STD_LOGIC; @@ -569,8 +574,8 @@ PACKAGE firebee_pkg IS FB_CS1n : IN STD_LOGIC; fb_size0 : IN STD_LOGIC; fb_size1 : IN STD_LOGIC; - fb_wr_n : IN STD_LOGIC; - fb_oe_n : IN STD_LOGIC; + fb_wr_n : IN STD_LOGIC; + fb_oe_n : IN STD_LOGIC; FB_AD_IN : IN STD_LOGIC_VECTOR(23 DOWNTO 16); FB_AD_OUT : OUT STD_LOGIC_VECTOR(23 DOWNTO 16); FB_AD_EN_23_16 : OUT STD_LOGIC; diff --git a/vhdl/rtl/vhdl/Video/VIDEO_CTRL.vhd b/vhdl/rtl/vhdl/Video/VIDEO_CTRL.vhd index d51d2ff..70ddb0c 100644 --- a/vhdl/rtl/vhdl/Video/VIDEO_CTRL.vhd +++ b/vhdl/rtl/vhdl/Video/VIDEO_CTRL.vhd @@ -286,7 +286,7 @@ BEGIN ELSE clut_ta <= '0'; END IF; - end PROCESS P_CLUT_TA; + END PROCESS P_CLUT_TA; --Falcon CLUT: falcon_clut_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(19 DOWNTO 10) = "1111100110" ELSE '0'; -- $F9800/$400 @@ -395,7 +395,7 @@ BEGIN ELSIF atari_vl_cs = '1' AND fb_b(3) = '1' AND fb_wr_n = '0' THEN atari_vl(7 DOWNTO 0) <= data_in(7 DOWNTO 0); END IF; - end PROCESS P_VIDEO_CONTROL; + END PROCESS P_VIDEO_CONTROL; clut_off <= falcon_shift_mode(3 DOWNTO 0) WHEN color4_i = '1' ELSE x"0"; pd_vga_n <= fbee_vctr(1); @@ -452,7 +452,7 @@ BEGIN ELSE video_reconfig_i <= '0'; END IF; - end PROCESS P_VIDEO_CONFIG; + END PROCESS P_VIDEO_CONFIG; video_ram_ctr <= fbee_vctr(31 DOWNTO 16); @@ -471,16 +471,16 @@ BEGIN vdl_lof_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff820e" ELSE '0'; -- $FF820E/F - line-width hi/lo. VDL_LWD_CS <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff8210" ELSE '0'; -- $FF8210/1 - vertical wrap hi/lo. vdl_hht_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff8282" ELSE '0'; -- $FF8282/3 - horizontal hold timer hi/lo. - vdl_hbe_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff8286" ELSE '0'; -- $FF8286/7 - horizontal border end hi/lo. + vdl_hbe_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff8286" ELSE '0'; -- $FF8286/7 - horizontal border END hi/lo. vdl_hdb_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff8288" ELSE '0'; -- $FF8288/9 - horizontal display BEGIN hi/lo. - vdl_hde_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff828a" ELSE '0'; -- $FF828A/B - horizontal display end hi/lo. + vdl_hde_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff828a" ELSE '0'; -- $FF828A/B - horizontal display END hi/lo. vdl_hbb_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff8284" ELSE '0'; -- $FF8284/5 - horizontal border BEGIN hi/lo. vdl_hss_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff828c" ELSE '0'; -- $FF828C/D - position hsync (HSS). vdl_vft_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff82a2" ELSE '0'; -- $FF82A2/3 - video frequency timer (VFT). vdl_vbb_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff82a4" ELSE '0'; -- $FF82A4/5 - vertical blank on (IN half line steps). vdl_vbe_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff82a6" ELSE '0'; -- $FF82A6/7 - vertical blank off (IN half line steps). VDL_VDB_CS <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff82a8" ELSE '0'; -- $FF82A8/9 - vertical display BEGIN (VDB). - vdl_vde_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff82aa" ELSE '0'; -- $FF82AA/B - vertical display end (VDE). + vdl_vde_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff82aa" ELSE '0'; -- $FF82AA/B - vertical display END (VDE). vdl_vss_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff82ac" ELSE '0'; -- $FF82AC/D - position vsync (VSS). vdl_vct_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff82c0" ELSE '0'; -- $FF82C0/1 - clock control (VCO). vdl_vmd_cs <= '1' WHEN fb_cs_n(1) = '0' AND fb_adr(23 DOWNTO 1) & '0' = x"ff82c2" ELSE '0'; -- $FF82C2/3 - resolution control. @@ -614,7 +614,7 @@ BEGIN IF vdl_vmd_cs = '1' AND fb_b(3) = '1' AND fb_wr_n = '0' THEN vdl_vmd <= data_in(19 DOWNTO 16); END IF; - end PROCESS P_MISC_CTRL; + END PROCESS P_MISC_CTRL; blitter_on <= NOT sys_ctr(3); @@ -670,13 +670,13 @@ BEGIN BEGIN WAIT UNTIL rising_edge(clk33m); clk17m <= NOT clk17m; - end PROCESS P_CLK_16M5; + END PROCESS P_CLK_16M5; P_CLK_12M5 : PROCESS BEGIN WAIT UNTIL rising_edge(clk25m); clk13m <= NOT clk13m; - end PROCESS P_CLK_12M5; + END PROCESS P_CLK_12M5; clk_pixel_i <= clk13m WHEN fbee_video_on = '0' AND (falcon_video = '1' or st_video = '1') AND vdl_vmd(2) = '1' AND vdl_vct(2) = '1' ELSE clk13m WHEN fbee_video_on = '0' AND (falcon_video = '1' or st_video = '1') AND vdl_vmd(2) = '1' AND vdl_vct(0) = '1' ELSE @@ -688,32 +688,32 @@ BEGIN clk33m WHEN fbee_video_on = '1' AND fbee_vctr(9 DOWNTO 8) = "01" ELSE clk_video WHEN fbee_video_on = '1' AND fbee_vctr(9) = '1' ELSE '0'; - P_HSYN_LEN : PROCESS + p_hsyn_len : PROCESS -- Horizontal SYNC IN clk_pixel: BEGIN WAIT UNTIL rising_edge(clk_main); IF fbee_video_on = '0' AND (falcon_video = '1' or st_video = '1') AND vdl_vmd(2) = '1' AND vdl_vct(2) = '1' THEN - hsync_len <= x"0E"; + hsync_len <= 8D"14"; ELSIF fbee_video_on = '0' AND (falcon_video = '1' or st_video = '1') AND vdl_vmd(2) = '1' AND vdl_vct(0) = '1' THEN - hsync_len <= x"0E"; + hsync_len <= 8D"14"; ELSIF fbee_video_on = '0' AND (falcon_video or st_video) = '1' AND vdl_vmd(2) = '1' AND vdl_vct(2) = '0' THEN - hsync_len <= x"10"; + hsync_len <= 8D"16"; ELSIF fbee_video_on = '0' AND (falcon_video or st_video) = '1' AND vdl_vmd(2) = '1' AND vdl_vct(0) = '0' THEN - hsync_len <= x"10"; + hsync_len <= 8D"16"; ELSIF fbee_video_on = '0' AND (falcon_video or st_video) = '1' AND vdl_vmd(2) = '0' AND vdl_vct(2) = '1' AND vdl_vct(0) = '0' THEN - hsync_len <= x"1C"; + hsync_len <= 8D"28"; ELSIF fbee_video_on = '0' AND (falcon_video or st_video) = '1' AND vdl_vmd(2) = '0' AND vdl_vct(2) = '0' AND vdl_vct(0) = '0' THEN - hsync_len <= x"20"; + hsync_len <= 8D"32"; ELSIF fbee_video_on = '1' AND fbee_vctr(9 DOWNTO 8) = "00" THEN - hsync_len <= x"1C"; + hsync_len <= 8D"28"; ELSIF fbee_video_on = '1' AND fbee_vctr(9 DOWNTO 8) = "01" THEN - hsync_len <= x"20"; + hsync_len <= 8D"32"; ELSIF fbee_video_on = '1' AND fbee_vctr(9) = '1' THEN - hsync_len <= UNSIGNED (UNSIGNED'(x"10") + UNSIGNED('0' & vr_frq(7 DOWNTO 1))); -- hsync pulse length IN pixels = frequency/500ns. + hsync_len <= 8D"16" + vr_frq / 2; -- hsync pulse length IN pixels = frequency/500ns. ELSE hsync_len <= x"00"; END IF; - end PROCESS P_HSYN_LEN; + END PROCESS p_hsyn_len; mulf <= "000010" WHEN st_video = '0' AND vdl_vmd(2) = '1' ELSE -- Multiplier. "000100" WHEN st_video = '0' AND vdl_vmd(2) = '0' ELSE @@ -722,13 +722,13 @@ BEGIN hdis_len <= x"140" WHEN vdl_vmd(2) = '1' ELSE x"280"; -- Width IN pixels (320 / 640). - P_DOUBLE_LINE_1 : PROCESS + p_double_line_1 : PROCESS BEGIN WAIT UNTIL rising_edge(clk_main); dop_zei <= vdl_vmd(0) AND st_video; -- Line doubling on off. - end PROCESS P_DOUBLE_LINE_1; + END PROCESS p_double_line_1; - P_DOUBLE_LINE_2 : PROCESS + p_double_line_2 : PROCESS BEGIN WAIT UNTIL rising_edge(clk_pixel_i); IF dop_zei = '1' AND vvcnt(0) /= vdis_start(0) AND vvcnt /= "00000000000" AND vhcnt < hdis_end - 1 THEN @@ -739,8 +739,8 @@ BEGIN inter_zei_i <= '0'; END IF; -- - dop_fifo_clr <= inter_zei_i AND hsync_start AND sync_pix; -- Double line info erase at the end of a double line AND at main FIFO start. - end PROCESS P_DOUBLE_LINE_2; + dop_fifo_clr <= inter_zei_i AND hsync_start AND sync_pix; -- Double line info erase at the END of a double line AND at main FIFO start. + END PROCESS p_double_line_2; -- The following multiplications change every time the video resolution is changed. mul1 <= vdl_hbe * mulf(5 DOWNTO 1); @@ -841,7 +841,7 @@ BEGIN END IF; IF last = '1' AND vvcnt >= UNSIGNED (UNSIGNED(vdis_start) - 1) AND vvcnt < vdis_end THEN - vdo_zl <= '1'; -- Take over at the end of the line. + vdo_zl <= '1'; -- Take over at the END of the line. ELSIF last = '1' THEN vdo_zl <= '0'; -- 1 ZEILE DAVOR ON OFF END IF; @@ -867,7 +867,7 @@ BEGIN vsync_start <= '0'; END IF; - IF last = '1' AND vsync_start = '1' THEN -- Start at the end of the line before vsync. + IF last = '1' AND vsync_start = '1' THEN -- Start at the END of the line before vsync. vsync_i <= "011"; -- 3 lines vsync length. ELSIF last = '1' AND vsync_i > "000" THEN vsync_i <= UNSIGNED (UNSIGNED(vsync_i) - 1); -- Count down. @@ -955,5 +955,5 @@ BEGIN clut_mux_av_0 <= sub_pixel_cnt(3 DOWNTO 0); clut_mux_av_1 <= clut_mux_av_0; clut_mux_adr <= clut_mux_av_1; - end PROCESS VIDEO_CLOCK_DOMAIN; -end architecture BEHAVIOUR; + END PROCESS VIDEO_CLOCK_DOMAIN; +END architecture BEHAVIOUR; diff --git a/vhdl/rtl/vhdl/Video/Video_Top.vhd b/vhdl/rtl/vhdl/Video/Video_Top.vhd index ee24473..10921c6 100644 --- a/vhdl/rtl/vhdl/Video/Video_Top.vhd +++ b/vhdl/rtl/vhdl/Video/Video_Top.vhd @@ -56,51 +56,51 @@ ENTITY VIDEO_SYSTEM IS CLK_33M : IN STD_LOGIC; CLK_25M : IN STD_LOGIC; CLK_VIDEO : IN STD_LOGIC; - CLK_DDR3 : IN STD_LOGIC; - CLK_DDR2 : IN STD_LOGIC; - CLK_DDR0 : IN STD_LOGIC; - CLK_PIXEL : OUT STD_LOGIC; + clk_ddr3 : IN STD_LOGIC; + clk_ddr2 : IN STD_LOGIC; + clk_ddr0 : IN STD_LOGIC; + clk_pixel : OUT STD_LOGIC; VR_D : IN STD_LOGIC_VECTOR(8 DOWNTO 0); VR_BUSY : IN STD_LOGIC; FB_ADR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); FB_AD_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - FB_AD_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - FB_AD_EN_31_16 : OUT STD_LOGIC; -- Hi word. - FB_AD_EN_15_0 : OUT STD_LOGIC; -- Low word. + fb_ad_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + fb_ad_en_31_16 : OUT STD_LOGIC; -- Hi word. + fb_ad_en_15_0 : OUT STD_LOGIC; -- Low word. FB_ALE : IN STD_LOGIC; - fb_cs_n : IN STD_LOGIC_VECTOR(3 DOWNTO 1); - fb_oe_n : IN STD_LOGIC; + fb_cs_n : IN STD_LOGIC_VECTOR(3 DOWNTO 1); + fb_oe_n : IN STD_LOGIC; fb_wr_n : IN STD_LOGIC; FB_SIZE1 : IN STD_LOGIC; FB_SIZE0 : IN STD_LOGIC; - VDP_IN : IN STD_LOGIC_VECTOR(63 DOWNTO 0); + vdp_in : IN STD_LOGIC_VECTOR(63 DOWNTO 0); VR_RD : OUT STD_LOGIC; VR_WR : OUT STD_LOGIC; VIDEO_RECONFIG : OUT STD_LOGIC; - RED : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); - GREEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); - BLUE : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + red : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + green : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + blue : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); VSYNC : OUT STD_LOGIC; HSYNC : OUT STD_LOGIC; - sync_n : OUT STD_LOGIC; - blank_n : OUT STD_LOGIC; + sync_n : OUT STD_LOGIC; + blank_n : OUT STD_LOGIC; - pd_vga_n : OUT STD_LOGIC; + pd_vga_n : OUT STD_LOGIC; VIDEO_MOD_TA : OUT STD_LOGIC; - VD_VZ : OUT STD_LOGIC_VECTOR(127 DOWNTO 0); - SR_FIFO_WRE : IN STD_LOGIC; - SR_VDMP : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + vd_vz : OUT STD_LOGIC_VECTOR(127 DOWNTO 0); + sr_fifo_wre : IN STD_LOGIC; + sr_vdmp : IN STD_LOGIC_VECTOR(7 DOWNTO 0); FIFO_MW : OUT STD_LOGIC_VECTOR(8 DOWNTO 0); - VDM_SEL : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + vdm_sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0); VIDEO_RAM_CTR : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); - FIFO_CLR : OUT STD_LOGIC; - VDM : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + fifo_clr : OUT STD_LOGIC; + vdm : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); BLITTER_RUN : IN STD_LOGIC; BLITTER_ON : OUT STD_LOGIC @@ -129,360 +129,360 @@ ARCHITECTURE BEHAVIOUR OF VIDEO_SYSTEM is data : IN STD_LOGIC_VECTOR (127 DOWNTO 0); rdreq : IN STD_LOGIC ; wrreq : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (127 DOWNTO 0) + q : OUT STD_LOGIC_VECTOR (127 DOWNTO 0) ); END COMPONENT; - TYPE CLUT_SHIFTREG_TYPE is ARRAY(0 TO 7) OF STD_LOGIC_VECTOR(15 DOWNTO 0); - TYPE CLUT_ST_TYPE is ARRAY(0 TO 15) OF STD_LOGIC_VECTOR(11 DOWNTO 0); - TYPE CLUT_FA_TYPE is ARRAY(0 TO 255) OF STD_LOGIC_VECTOR(17 DOWNTO 0); - TYPE CLUT_FBEE_TYPE is ARRAY(0 TO 255) OF STD_LOGIC_VECTOR(23 DOWNTO 0); + TYPE clut_shiftreg_t IS ARRAY(0 TO 7) OF STD_LOGIC_VECTOR(15 DOWNTO 0); + TYPE clut_st_t IS ARRAY(0 TO 15) OF STD_LOGIC_VECTOR(11 DOWNTO 0); + TYPE clut_fa_t IS ARRAY(0 TO 255) OF STD_LOGIC_VECTOR(17 DOWNTO 0); + TYPE clut_fbee_t IS ARRAY(0 TO 255) OF STD_LOGIC_VECTOR(23 DOWNTO 0); - SIGNAL CLUT_FA : CLUT_FA_TYPE; - SIGNAL CLUT_FI : CLUT_FBEE_TYPE; - SIGNAL CLUT_ST : CLUT_ST_TYPE; + SIGNAL clut_fa : clut_fa_t; + SIGNAL clut_fi : clut_fbee_t; + SIGNAL clut_st : clut_st_t; - SIGNAL CLUT_FA_R : STD_LOGIC_VECTOR(5 DOWNTO 0); - SIGNAL CLUT_FA_G : STD_LOGIC_VECTOR(5 DOWNTO 0); - SIGNAL CLUT_FA_B : STD_LOGIC_VECTOR(5 DOWNTO 0); - SIGNAL CLUT_FBEE_R : STD_LOGIC_VECTOR(7 DOWNTO 0); - SIGNAL CLUT_FBEE_G : STD_LOGIC_VECTOR(7 DOWNTO 0); - SIGNAL CLUT_FBEE_B : STD_LOGIC_VECTOR(7 DOWNTO 0); - SIGNAL CLUT_ST_R : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL CLUT_ST_G : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL CLUT_ST_B : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL clut_fa_r : STD_LOGIC_VECTOR(5 DOWNTO 0); + SIGNAL clut_fa_g : STD_LOGIC_VECTOR(5 DOWNTO 0); + SIGNAL clut_fa_b : STD_LOGIC_VECTOR(5 DOWNTO 0); + SIGNAL clut_fbee_r : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL clut_fbee_g : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL clut_fbee_b : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL clut_st_r : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL clut_st_g : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL clut_st_b : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL CLUT_FA_OUT : STD_LOGIC_VECTOR(17 DOWNTO 0); - SIGNAL CLUT_FBEE_OUT : STD_LOGIC_VECTOR(23 DOWNTO 0); - SIGNAL CLUT_ST_OUT : STD_LOGIC_VECTOR(11 DOWNTO 0); + SIGNAL clut_fa_out : STD_LOGIC_VECTOR(17 DOWNTO 0); + SIGNAL clut_fbee_out : STD_LOGIC_VECTOR(23 DOWNTO 0); + SIGNAL clut_st_out : STD_LOGIC_VECTOR(11 DOWNTO 0); - SIGNAL CLUT_ADR : STD_LOGIC_VECTOR(7 DOWNTO 0); - SIGNAL CLUT_ADR_A : STD_LOGIC_VECTOR(7 DOWNTO 0); - SIGNAL CLUT_ADR_MUX : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL CLUT_SHIFT_IN : STD_LOGIC_VECTOR(5 DOWNTO 0); + SIGNAL clut_adr : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL clut_adr_a : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL clut_adr_mux : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL clut_shift_in : STD_LOGIC_VECTOR(5 DOWNTO 0); - SIGNAL CLUT_SHIFT_LOAD : STD_LOGIC; - SIGNAL CLUT_OFF : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL CLUT_FBEE_RD : STD_LOGIC; - SIGNAL CLUT_FBEE_WR : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL CLUT_FA_RDH : STD_LOGIC; - SIGNAL CLUT_FA_RDL : STD_LOGIC; - SIGNAL CLUT_FA_WR : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL CLUT_ST_RD : STD_LOGIC; - SIGNAL CLUT_ST_WR : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL clut_shift_load : STD_LOGIC; + SIGNAL clut_off : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL clut_fbee_rd : STD_LOGIC; + SIGNAL clut_fbee_wr : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL clut_fa_rdh : STD_LOGIC; + SIGNAL clut_fa_rdl : STD_LOGIC; + SIGNAL clut_fa_wr : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL clut_st_rd : STD_LOGIC; + SIGNAL clut_st_wr : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL DATA_OUT_VIDEO_CTRL : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL DATA_EN_H_VIDEO_CTRL : STD_LOGIC; - SIGNAL DATA_EN_L_VIDEO_CTRL : STD_LOGIC; + SIGNAL data_out_video_ctrl : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_en_h_video_ctrl : STD_LOGIC; + SIGNAL data_en_l_video_ctrl : STD_LOGIC; SIGNAL COLOR1 : STD_LOGIC; - SIGNAL COLOR2 : STD_LOGIC; - SIGNAL COLOR4 : STD_LOGIC; - SIGNAL COLOR8 : STD_LOGIC; - SIGNAL CCR : STD_LOGIC_VECTOR(23 DOWNTO 0); + SIGNAL color2 : STD_LOGIC; + SIGNAL color4 : STD_LOGIC; + SIGNAL color8 : STD_LOGIC; + SIGNAL ccr : STD_LOGIC_VECTOR(23 DOWNTO 0); SIGNAL CC_SEL : STD_LOGIC_VECTOR(2 DOWNTO 0); - SIGNAL FIFO_CLR_I : STD_LOGIC; + SIGNAL fifo_clr_i : STD_LOGIC; SIGNAL DOP_FIFO_CLR : STD_LOGIC; - SIGNAL FIFO_WRE : STD_LOGIC; + SIGNAL fifo_wre : STD_LOGIC; - SIGNAL FIFO_RD_REQ_128 : STD_LOGIC; - SIGNAL FIFO_RD_REQ_512 : STD_LOGIC; - SIGNAL FIFO_RDE : STD_LOGIC; - SIGNAL INTER_ZEI : STD_LOGIC; - SIGNAL FIFO_D_OUT_128 : STD_LOGIC_VECTOR(127 DOWNTO 0); - SIGNAL FIFO_D_OUT_512 : STD_LOGIC_VECTOR(127 DOWNTO 0); + SIGNAL fifo_rd_req_128 : STD_LOGIC; + SIGNAL fifo_rd_req_512 : STD_LOGIC; + SIGNAL fifo_rde : STD_LOGIC; + SIGNAL inter_zei : STD_LOGIC; + SIGNAL fifo_d_out_128 : STD_LOGIC_VECTOR(127 DOWNTO 0); + SIGNAL fifo_d_out_512 : STD_LOGIC_VECTOR(127 DOWNTO 0); SIGNAL FIFO_D_IN_512 : STD_LOGIC_VECTOR(127 DOWNTO 0); - SIGNAL FIFO_D : STD_LOGIC_VECTOR(127 DOWNTO 0); + SIGNAL fifo_d : STD_LOGIC_VECTOR(127 DOWNTO 0); - SIGNAL VD_VZ_I : STD_LOGIC_VECTOR(127 DOWNTO 0); - SIGNAL VDM_A : STD_LOGIC_VECTOR(127 DOWNTO 0); - SIGNAL VDM_B : STD_LOGIC_VECTOR(127 DOWNTO 0); - SIGNAL VDM_C : STD_LOGIC_VECTOR(127 DOWNTO 0); + SIGNAL vd_vz_i : STD_LOGIC_VECTOR(127 DOWNTO 0); + SIGNAL vdm_a : STD_LOGIC_VECTOR(127 DOWNTO 0); + SIGNAL vdm_b : STD_LOGIC_VECTOR(127 DOWNTO 0); + SIGNAL vdm_c : STD_LOGIC_VECTOR(127 DOWNTO 0); SIGNAL V_DMA_SEL : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL VDMP : STD_LOGIC_VECTOR(7 DOWNTO 0); - SIGNAL VDMP_I : STD_LOGIC_VECTOR(7 DOWNTO 0); - SIGNAL CC_24 : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL CC_16 : STD_LOGIC_VECTOR(23 DOWNTO 0); - SIGNAL CLK_PIXEL_I : STD_LOGIC; + SIGNAL vdmp : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL vdmp_i : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL cc_24 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL cc_16 : STD_LOGIC_VECTOR(23 DOWNTO 0); + SIGNAL clk_pixel_i : STD_LOGIC; SIGNAL VD_OUT_I : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL ZR_C8 : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL zr_c8 : STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN - CLK_PIXEL <= CLK_PIXEL_I; - FIFO_CLR <= FIFO_CLR_I; + clk_pixel <= clk_pixel_i; + fifo_clr <= fifo_clr_i; P_CLUT_ST_MC: PROCESS -- This is the dual ported ram FOR the ST colour lookup tables. - VARIABLE clut_fa_index : integer; - VARIABLE clut_st_index : integer; - VARIABLE clut_fi_index : integer; + VARIABLE clut_fa_index : INTEGER; + VARIABLE clut_st_index : INTEGER; + VARIABLE clut_fi_index : INTEGER; BEGIN clut_st_index := TO_INTEGER(UNSIGNED(FB_ADR(4 DOWNTO 1))); clut_fa_index := TO_INTEGER(UNSIGNED(FB_ADR(9 DOWNTO 2))); clut_fi_index := TO_INTEGER(UNSIGNED(FB_ADR(9 DOWNTO 2))); WAIT UNTIL RISING_EDGE(CLK_MAIN); - IF CLUT_ST_WR(0) = '1' THEN - CLUT_ST(clut_st_index)(11 DOWNTO 8) <= FB_AD_IN(27 DOWNTO 24); + IF clut_st_wr(0) = '1' THEN + clut_st(clut_st_index)(11 DOWNTO 8) <= FB_AD_IN(27 DOWNTO 24); END IF; - IF CLUT_ST_WR(1) = '1' THEN - CLUT_ST(clut_st_index)(7 DOWNTO 0) <= FB_AD_IN(23 DOWNTO 16); + IF clut_st_wr(1) = '1' THEN + clut_st(clut_st_index)(7 DOWNTO 0) <= FB_AD_IN(23 DOWNTO 16); END IF; - IF CLUT_FA_WR(0) = '1' THEN - CLUT_FA(clut_fa_index)(17 DOWNTO 12) <= FB_AD_IN(31 DOWNTO 26); + IF clut_fa_wr(0) = '1' THEN + clut_fa(clut_fa_index)(17 DOWNTO 12) <= FB_AD_IN(31 DOWNTO 26); END IF; - IF CLUT_FA_WR(1) = '1' THEN - CLUT_FA(clut_fa_index)(11 DOWNTO 6) <= FB_AD_IN(23 DOWNTO 18); + IF clut_fa_wr(1) = '1' THEN + clut_fa(clut_fa_index)(11 DOWNTO 6) <= FB_AD_IN(23 DOWNTO 18); END IF; - IF CLUT_FA_WR(3) = '1' THEN - CLUT_FA(clut_fa_index)(5 DOWNTO 0) <= FB_AD_IN(23 DOWNTO 18); + IF clut_fa_wr(3) = '1' THEN + clut_fa(clut_fa_index)(5 DOWNTO 0) <= FB_AD_IN(23 DOWNTO 18); END IF; - IF CLUT_FBEE_WR(1) = '1' THEN - CLUT_FI(clut_fi_index)(23 DOWNTO 16) <= FB_AD_IN(23 DOWNTO 16); + IF clut_fbee_wr(1) = '1' THEN + clut_fi(clut_fi_index)(23 DOWNTO 16) <= FB_AD_IN(23 DOWNTO 16); END IF; - IF CLUT_FBEE_WR(2) = '1' THEN - CLUT_FI(clut_fi_index)(15 DOWNTO 8) <= FB_AD_IN(15 DOWNTO 8); + IF clut_fbee_wr(2) = '1' THEN + clut_fi(clut_fi_index)(15 DOWNTO 8) <= FB_AD_IN(15 DOWNTO 8); END IF; - IF CLUT_FBEE_WR(3) = '1' THEN - CLUT_FI(clut_fi_index)(7 DOWNTO 0) <= FB_AD_IN(7 DOWNTO 0); + IF clut_fbee_wr(3) = '1' THEN + clut_fi(clut_fi_index)(7 DOWNTO 0) <= FB_AD_IN(7 DOWNTO 0); END IF; -- - CLUT_ST_OUT <= CLUT_ST(clut_st_index); - CLUT_FA_OUT <= CLUT_FA(clut_fa_index); - CLUT_FBEE_OUT <= CLUT_FI(clut_fi_index); + clut_st_out <= clut_st(clut_st_index); + clut_fa_out <= clut_fa(clut_fa_index); + clut_fbee_out <= clut_fi(clut_fi_index); END PROCESS P_CLUT_ST_MC; P_CLUT_ST_PX: PROCESS - VARIABLE clut_fa_index : integer; - VARIABLE clut_st_index : integer; - VARIABLE clut_fi_index : integer; + VARIABLE clut_fa_index : INTEGER; + VARIABLE clut_st_index : INTEGER; + VARIABLE clut_fi_index : INTEGER; -- This is the dual ported ram FOR the ST colour lookup tables. BEGIN - clut_st_index := TO_INTEGER(UNSIGNED(CLUT_ADR(3 DOWNTO 0))); - clut_fa_index := TO_INTEGER(UNSIGNED(CLUT_ADR)); - clut_fi_index := TO_INTEGER(UNSIGNED(ZR_C8)); + clut_st_index := TO_INTEGER(UNSIGNED(clut_adr(3 DOWNTO 0))); + clut_fa_index := TO_INTEGER(UNSIGNED(clut_adr)); + clut_fi_index := TO_INTEGER(UNSIGNED(zr_c8)); - WAIT UNTIL CLK_PIXEL_I = '1' and CLK_PIXEL_I' event; + WAIT UNTIL clk_pixel_i = '1' and clk_pixel_i' event; - CLUT_ST_R <= CLUT_ST(clut_st_index)(8) & CLUT_ST(clut_st_index)(11 DOWNTO 9); - CLUT_ST_G <= CLUT_ST(clut_st_index)(4) & CLUT_ST(clut_st_index)(7 DOWNTO 5); - CLUT_ST_B <= CLUT_ST(clut_st_index)(0) & CLUT_ST(clut_st_index)(3 DOWNTO 1); + clut_st_r <= clut_st(clut_st_index)(8) & clut_st(clut_st_index)(11 DOWNTO 9); + clut_st_g <= clut_st(clut_st_index)(4) & clut_st(clut_st_index)(7 DOWNTO 5); + clut_st_b <= clut_st(clut_st_index)(0) & clut_st(clut_st_index)(3 DOWNTO 1); - CLUT_FA_R <= CLUT_FA(clut_fa_index)(17 DOWNTO 12); - CLUT_FA_G <= CLUT_FA(clut_fa_index)(11 DOWNTO 6); - CLUT_FA_B <= CLUT_FA(clut_fa_index)(5 DOWNTO 0); + clut_fa_r <= clut_fa(clut_fa_index)(17 DOWNTO 12); + clut_fa_g <= clut_fa(clut_fa_index)(11 DOWNTO 6); + clut_fa_b <= clut_fa(clut_fa_index)(5 DOWNTO 0); - CLUT_FBEE_R <= CLUT_FI(clut_fi_index)(23 DOWNTO 16); - CLUT_FBEE_G <= CLUT_FI(clut_fi_index)(15 DOWNTO 8); - CLUT_FBEE_B <= CLUT_FI(clut_fi_index)(7 DOWNTO 0); + clut_fbee_r <= clut_fi(clut_fi_index)(23 DOWNTO 16); + clut_fbee_g <= clut_fi(clut_fi_index)(15 DOWNTO 8); + clut_fbee_b <= clut_fi(clut_fi_index)(7 DOWNTO 0); END PROCESS P_CLUT_ST_PX; P_VIDEO_OUT: PROCESS - VARIABLE VIDEO_OUT : STD_LOGIC_VECTOR(23 DOWNTO 0); + VARIABLE video_out : STD_LOGIC_VECTOR(23 DOWNTO 0); BEGIN - WAIT UNTIL RISING_EDGE(CLK_PIXEL_I); + WAIT UNTIL RISING_EDGE(clk_pixel_i); CASE CC_SEL is - WHEN "111" => VIDEO_OUT := CCR; -- Register TYPE video. - WHEN "110" => VIDEO_OUT := CC_24(23 DOWNTO 0); -- 3 byte FIFO TYPE video. - WHEN "101" => VIDEO_OUT := CC_16; -- 2 byte FIFO TYPE video. - WHEN "100" => VIDEO_OUT := CLUT_FBEE_R & CLUT_FBEE_G & CLUT_FBEE_B; -- Firebee TYPE video. - WHEN "001" => VIDEO_OUT := CLUT_FA_R & "00" & CLUT_FA_G & "00" & CLUT_FA_B & "00"; -- Falcon TYPE video. - WHEN "000" => VIDEO_OUT := CLUT_ST_R & x"0" & CLUT_ST_G & x"0" & CLUT_ST_B & x"0"; -- ST TYPE video. - WHEN OTHERS => VIDEO_OUT := (OTHERS => '0'); + WHEN "111" => video_out := ccr; -- Register TYPE video. + WHEN "110" => video_out := cc_24(23 DOWNTO 0); -- 3 byte FIFO TYPE video. + WHEN "101" => video_out := cc_16; -- 2 byte FIFO TYPE video. + WHEN "100" => video_out := clut_fbee_r & clut_fbee_g & clut_fbee_b; -- Firebee TYPE video. + WHEN "001" => video_out := clut_fa_r & "00" & clut_fa_g & "00" & clut_fa_b & "00"; -- Falcon TYPE video. + WHEN "000" => video_out := clut_st_r & x"0" & clut_st_g & x"0" & clut_st_b & x"0"; -- ST TYPE video. + WHEN OTHERS => video_out := (OTHERS => '0'); END CASE; - RED <= VIDEO_OUT(23 DOWNTO 16); - GREEN <= VIDEO_OUT(15 DOWNTO 8); - BLUE <= VIDEO_OUT(7 DOWNTO 0); + red <= video_out(23 DOWNTO 16); + green <= video_out(15 DOWNTO 8); + blue <= video_out(7 DOWNTO 0); END PROCESS P_VIDEO_OUT; P_CC: PROCESS - VARIABLE CC24_I : STD_LOGIC_VECTOR(31 DOWNTO 0); - VARIABLE CC_I : STD_LOGIC_VECTOR(15 DOWNTO 0); - VARIABLE ZR_C8_I : STD_LOGIC_VECTOR(7 DOWNTO 0); + VARIABLE cc24_i : STD_LOGIC_VECTOR(31 DOWNTO 0); + VARIABLE cc_i : STD_LOGIC_VECTOR(15 DOWNTO 0); + VARIABLE zr_c8_i : STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN - WAIT UNTIL CLK_PIXEL_I = '1' and CLK_PIXEL_I' event; - CASE CLUT_ADR_MUX(1 DOWNTO 0) is - WHEN "11" => CC24_I := FIFO_D(31 DOWNTO 0); - WHEN "10" => CC24_I := FIFO_D(63 DOWNTO 32); - WHEN "01" => CC24_I := FIFO_D(95 DOWNTO 64); - WHEN "00" => CC24_I := FIFO_D(127 DOWNTO 96); - WHEN OTHERS => CC24_I := (OTHERS => 'Z'); + WAIT UNTIL clk_pixel_i = '1' and clk_pixel_i' event; + CASE clut_adr_mux(1 DOWNTO 0) is + WHEN "11" => cc24_i := fifo_d(31 DOWNTO 0); + WHEN "10" => cc24_i := fifo_d(63 DOWNTO 32); + WHEN "01" => cc24_i := fifo_d(95 DOWNTO 64); + WHEN "00" => cc24_i := fifo_d(127 DOWNTO 96); + WHEN OTHERS => cc24_i := (OTHERS => 'Z'); END CASE; -- - CC_24 <= CC24_I; + cc_24 <= cc24_i; -- - CASE CLUT_ADR_MUX(2 DOWNTO 0) is - WHEN "111" => CC_I := FIFO_D(15 DOWNTO 0); - WHEN "110" => CC_I := FIFO_D(31 DOWNTO 16); - WHEN "101" => CC_I := FIFO_D(47 DOWNTO 32); - WHEN "100" => CC_I := FIFO_D(63 DOWNTO 48); - WHEN "011" => CC_I := FIFO_D(79 DOWNTO 64); - WHEN "010" => CC_I := FIFO_D(95 DOWNTO 80); - WHEN "001" => CC_I := FIFO_D(111 DOWNTO 96); - WHEN "000" => CC_I := FIFO_D(127 DOWNTO 112); - WHEN OTHERS => CC_I := (OTHERS => 'X'); + CASE clut_adr_mux(2 DOWNTO 0) is + WHEN "111" => cc_i := fifo_d(15 DOWNTO 0); + WHEN "110" => cc_i := fifo_d(31 DOWNTO 16); + WHEN "101" => cc_i := fifo_d(47 DOWNTO 32); + WHEN "100" => cc_i := fifo_d(63 DOWNTO 48); + WHEN "011" => cc_i := fifo_d(79 DOWNTO 64); + WHEN "010" => cc_i := fifo_d(95 DOWNTO 80); + WHEN "001" => cc_i := fifo_d(111 DOWNTO 96); + WHEN "000" => cc_i := fifo_d(127 DOWNTO 112); + WHEN OTHERS => cc_i := (OTHERS => 'X'); END CASE; -- - CC_16 <= CC_I(15 DOWNTO 11) & "000" & CC_I(10 DOWNTO 5) & "00" & CC_I(4 DOWNTO 0) & "000"; + cc_16 <= cc_i(15 DOWNTO 11) & "000" & cc_i(10 DOWNTO 5) & "00" & cc_i(4 DOWNTO 0) & "000"; -- - CASE CLUT_ADR_MUX(3 DOWNTO 0) is - WHEN x"F" => ZR_C8_I := FIFO_D(7 DOWNTO 0); - WHEN x"E" => ZR_C8_I := FIFO_D(15 DOWNTO 8); - WHEN x"D" => ZR_C8_I := FIFO_D(23 DOWNTO 16); - WHEN x"C" => ZR_C8_I := FIFO_D(31 DOWNTO 24); - WHEN x"B" => ZR_C8_I := FIFO_D(39 DOWNTO 32); - WHEN x"A" => ZR_C8_I := FIFO_D(47 DOWNTO 40); - WHEN x"9" => ZR_C8_I := FIFO_D(55 DOWNTO 48); - WHEN x"8" => ZR_C8_I := FIFO_D(63 DOWNTO 56); - WHEN x"7" => ZR_C8_I := FIFO_D(71 DOWNTO 64); - WHEN x"6" => ZR_C8_I := FIFO_D(79 DOWNTO 72); - WHEN x"5" => ZR_C8_I := FIFO_D(87 DOWNTO 80); - WHEN x"4" => ZR_C8_I := FIFO_D(95 DOWNTO 88); - WHEN x"3" => ZR_C8_I := FIFO_D(103 DOWNTO 96); - WHEN x"2" => ZR_C8_I := FIFO_D(111 DOWNTO 104); - WHEN x"1" => ZR_C8_I := FIFO_D(119 DOWNTO 112); - WHEN x"0" => ZR_C8_I := FIFO_D(127 DOWNTO 120); - WHEN OTHERS => ZR_C8_I := (OTHERS => 'X'); + CASE clut_adr_mux(3 DOWNTO 0) is + WHEN x"F" => zr_c8_i := fifo_d(7 DOWNTO 0); + WHEN x"E" => zr_c8_i := fifo_d(15 DOWNTO 8); + WHEN x"D" => zr_c8_i := fifo_d(23 DOWNTO 16); + WHEN x"C" => zr_c8_i := fifo_d(31 DOWNTO 24); + WHEN x"B" => zr_c8_i := fifo_d(39 DOWNTO 32); + WHEN x"A" => zr_c8_i := fifo_d(47 DOWNTO 40); + WHEN x"9" => zr_c8_i := fifo_d(55 DOWNTO 48); + WHEN x"8" => zr_c8_i := fifo_d(63 DOWNTO 56); + WHEN x"7" => zr_c8_i := fifo_d(71 DOWNTO 64); + WHEN x"6" => zr_c8_i := fifo_d(79 DOWNTO 72); + WHEN x"5" => zr_c8_i := fifo_d(87 DOWNTO 80); + WHEN x"4" => zr_c8_i := fifo_d(95 DOWNTO 88); + WHEN x"3" => zr_c8_i := fifo_d(103 DOWNTO 96); + WHEN x"2" => zr_c8_i := fifo_d(111 DOWNTO 104); + WHEN x"1" => zr_c8_i := fifo_d(119 DOWNTO 112); + WHEN x"0" => zr_c8_i := fifo_d(127 DOWNTO 120); + WHEN OTHERS => zr_c8_i := (OTHERS => 'X'); END CASE; -- CASE COLOR1 is - WHEN '1' => ZR_C8 <= ZR_C8_I; - WHEN OTHERS => ZR_C8 <= "0000000" & ZR_C8_I(0); + WHEN '1' => zr_c8 <= zr_c8_i; + WHEN OTHERS => zr_c8 <= "0000000" & zr_c8_i(0); END CASE; END PROCESS P_CC; - CLUT_SHIFT_IN <= CLUT_ADR_A(6 DOWNTO 1) WHEN COLOR4 = '0' and COLOR2 = '0' ELSE - CLUT_ADR_A(7 DOWNTO 2) WHEN COLOR4 = '0' and COLOR2 = '1' ELSE - "00" & CLUT_ADR_A(7 DOWNTO 4) WHEN COLOR4 = '1' and COLOR2 = '0' ELSE "000000"; + clut_shift_in <= clut_adr_a(6 DOWNTO 1) WHEN color4 = '0' and color2 = '0' ELSE + clut_adr_a(7 DOWNTO 2) WHEN color4 = '0' and color2 = '1' ELSE + "00" & clut_adr_a(7 DOWNTO 4) WHEN color4 = '1' and color2 = '0' ELSE "000000"; - FIFO_RD_REQ_128 <= '1' WHEN FIFO_RDE = '1' and INTER_ZEI = '1' ELSE '0'; - FIFO_RD_REQ_512 <= '1' WHEN FIFO_RDE = '1' and INTER_ZEI = '0' ELSE '0'; + fifo_rd_req_128 <= '1' WHEN fifo_rde = '1' and inter_zei = '1' ELSE '0'; + fifo_rd_req_512 <= '1' WHEN fifo_rde = '1' and inter_zei = '0' ELSE '0'; FIFO_DMUX: PROCESS BEGIN - WAIT UNTIL RISING_EDGE(CLK_PIXEL_I); - IF FIFO_RDE = '1' and INTER_ZEI = '1' THEN - FIFO_D <= FIFO_D_OUT_128; - ELSIF FIFO_RDE = '1' THEN - FIFO_D <= FIFO_D_OUT_512; + WAIT UNTIL RISING_EDGE(clk_pixel_i); + IF fifo_rde = '1' and inter_zei = '1' THEN + fifo_d <= fifo_d_out_128; + ELSIF fifo_rde = '1' THEN + fifo_d <= fifo_d_out_512; END IF; END PROCESS FIFO_DMUX; CLUT_SHIFTREGS: PROCESS - VARIABLE CLUT_SHIFTREG : CLUT_SHIFTREG_TYPE; + VARIABLE clut_shiftreg : clut_shiftreg_t; BEGIN - WAIT UNTIL RISING_EDGE(CLK_PIXEL_I); - CLUT_SHIFT_LOAD <= FIFO_RDE; - IF CLUT_SHIFT_LOAD = '1' THEN + WAIT UNTIL RISING_EDGE(clk_pixel_i); + clut_shift_load <= fifo_rde; + IF clut_shift_load = '1' THEN FOR i IN 0 TO 7 LOOP - CLUT_SHIFTREG(7 - i) := FIFO_D((i + 1) * 16 - 1 DOWNTO i * 16); + clut_shiftreg(7 - i) := fifo_d((i + 1) * 16 - 1 DOWNTO i * 16); END LOOP; ELSE - CLUT_SHIFTREG(7) := CLUT_SHIFTREG(7)(14 DOWNTO 0) & CLUT_ADR_A(0); - CLUT_SHIFTREG(6) := CLUT_SHIFTREG(6)(14 DOWNTO 0) & CLUT_ADR_A(7); - CLUT_SHIFTREG(5) := CLUT_SHIFTREG(5)(14 DOWNTO 0) & CLUT_SHIFT_IN(5); - CLUT_SHIFTREG(4) := CLUT_SHIFTREG(4)(14 DOWNTO 0) & CLUT_SHIFT_IN(4); - CLUT_SHIFTREG(3) := CLUT_SHIFTREG(3)(14 DOWNTO 0) & CLUT_SHIFT_IN(3); - CLUT_SHIFTREG(2) := CLUT_SHIFTREG(2)(14 DOWNTO 0) & CLUT_SHIFT_IN(2); - CLUT_SHIFTREG(1) := CLUT_SHIFTREG(1)(14 DOWNTO 0) & CLUT_SHIFT_IN(1); - CLUT_SHIFTREG(0) := CLUT_SHIFTREG(0)(14 DOWNTO 0) & CLUT_SHIFT_IN(0); + clut_shiftreg(7) := clut_shiftreg(7)(14 DOWNTO 0) & clut_adr_a(0); + clut_shiftreg(6) := clut_shiftreg(6)(14 DOWNTO 0) & clut_adr_a(7); + clut_shiftreg(5) := clut_shiftreg(5)(14 DOWNTO 0) & clut_shift_in(5); + clut_shiftreg(4) := clut_shiftreg(4)(14 DOWNTO 0) & clut_shift_in(4); + clut_shiftreg(3) := clut_shiftreg(3)(14 DOWNTO 0) & clut_shift_in(3); + clut_shiftreg(2) := clut_shiftreg(2)(14 DOWNTO 0) & clut_shift_in(2); + clut_shiftreg(1) := clut_shiftreg(1)(14 DOWNTO 0) & clut_shift_in(1); + clut_shiftreg(0) := clut_shiftreg(0)(14 DOWNTO 0) & clut_shift_in(0); END IF; -- FOR i IN 0 TO 7 LOOP - CLUT_ADR_A(i) <= CLUT_SHIFTREG(i)(15); + clut_adr_a(i) <= clut_shiftreg(i)(15); END LOOP; END PROCESS CLUT_SHIFTREGS; - CLUT_ADR(7) <= CLUT_OFF(3) or (CLUT_ADR_A(7) and COLOR8); - CLUT_ADR(6) <= CLUT_OFF(2) or (CLUT_ADR_A(6) and COLOR8); - CLUT_ADR(5) <= CLUT_OFF(1) or (CLUT_ADR_A(5) and COLOR8); - CLUT_ADR(4) <= CLUT_OFF(0) or (CLUT_ADR_A(4) and COLOR8); - CLUT_ADR(3) <= CLUT_ADR_A(3) and (COLOR8 or COLOR4); - CLUT_ADR(2) <= CLUT_ADR_A(2) and (COLOR8 or COLOR4); - CLUT_ADR(1) <= CLUT_ADR_A(1) and (COLOR8 or COLOR4 or COLOR2); - CLUT_ADR(0) <= CLUT_ADR_A(0); + clut_adr(7) <= clut_off(3) or (clut_adr_a(7) and color8); + clut_adr(6) <= clut_off(2) or (clut_adr_a(6) and color8); + clut_adr(5) <= clut_off(1) or (clut_adr_a(5) and color8); + clut_adr(4) <= clut_off(0) or (clut_adr_a(4) and color8); + clut_adr(3) <= clut_adr_a(3) and (color8 or color4); + clut_adr(2) <= clut_adr_a(2) and (color8 or color4); + clut_adr(1) <= clut_adr_a(1) and (color8 or color4 or color2); + clut_adr(0) <= clut_adr_a(0); - FB_AD_OUT <= x"0" & CLUT_ST_OUT & x"0000" WHEN CLUT_ST_RD = '1' ELSE - CLUT_FA_OUT(17 DOWNTO 12) & "00" & CLUT_FA_OUT(11 DOWNTO 6) & "00" & x"0000" WHEN CLUT_FA_RDH = '1' ELSE - x"00" & CLUT_FA_OUT(5 DOWNTO 0) & "00" & x"0000" WHEN CLUT_FA_RDL = '1' ELSE - x"00" & CLUT_FBEE_OUT WHEN CLUT_FBEE_RD = '1' ELSE - DATA_OUT_VIDEO_CTRL WHEN DATA_EN_H_VIDEO_CTRL = '1' ELSE -- Use upper word. - DATA_OUT_VIDEO_CTRL WHEN DATA_EN_L_VIDEO_CTRL = '1' ELSE (OTHERS => '0'); -- Use lower word. + fb_ad_out <= x"0" & clut_st_out & x"0000" WHEN clut_st_rd = '1' ELSE + clut_fa_out(17 DOWNTO 12) & "00" & clut_fa_out(11 DOWNTO 6) & "00" & x"0000" WHEN clut_fa_rdh = '1' ELSE + x"00" & clut_fa_out(5 DOWNTO 0) & "00" & x"0000" WHEN clut_fa_rdl = '1' ELSE + x"00" & clut_fbee_out WHEN clut_fbee_rd = '1' ELSE + data_out_video_ctrl WHEN data_en_h_video_ctrl = '1' ELSE -- Use upper word. + data_out_video_ctrl WHEN data_en_l_video_ctrl = '1' ELSE (OTHERS => '0'); -- Use lower word. - FB_AD_EN_31_16 <= '1' WHEN CLUT_FBEE_RD = '1' ELSE - '1' WHEN CLUT_FA_RDH = '1' ELSE - '1' WHEN DATA_EN_H_VIDEO_CTRL = '1' ELSE '0'; + fb_ad_en_31_16 <= '1' WHEN clut_fbee_rd = '1' ELSE + '1' WHEN clut_fa_rdh = '1' ELSE + '1' WHEN data_en_h_video_ctrl = '1' ELSE '0'; - FB_AD_EN_15_0 <= '1' WHEN CLUT_FBEE_RD = '1' ELSE - '1' WHEN CLUT_FA_RDL = '1' ELSE - '1' WHEN DATA_EN_L_VIDEO_CTRL = '1' ELSE '0'; + fb_ad_en_15_0 <= '1' WHEN clut_fbee_rd = '1' ELSE + '1' WHEN clut_fa_rdl = '1' ELSE + '1' WHEN data_en_l_video_ctrl = '1' ELSE '0'; - VD_VZ <= VD_VZ_I; + vd_vz <= vd_vz_i; DFF_CLK0: PROCESS BEGIN - WAIT UNTIL RISING_EDGE(CLK_DDR0); - VD_VZ_I <= VD_VZ_I(63 DOWNTO 0) & VDP_IN(63 DOWNTO 0); + WAIT UNTIL RISING_EDGE(clk_ddr0); + vd_vz_i <= vd_vz_i(63 DOWNTO 0) & vdp_in(63 DOWNTO 0); - IF FIFO_WRE = '1' THEN - VDM_A <= VD_VZ_I; - VDM_B <= VDM_A; + IF fifo_wre = '1' THEN + vdm_a <= vd_vz_i; + vdm_b <= vdm_a; END IF; END PROCESS DFF_CLK0; DFF_CLK2: PROCESS BEGIN - WAIT UNTIL RISING_EDGE(CLK_DDR2); - VDMP <= SR_VDMP; + WAIT UNTIL RISING_EDGE(clk_ddr2); + vdmp <= sr_vdmp; END PROCESS DFF_CLK2; DFF_CLK3: PROCESS BEGIN - WAIT UNTIL RISING_EDGE(CLK_DDR3); - VDMP_I <= VDMP; + WAIT UNTIL RISING_EDGE(clk_ddr3); + vdmp_i <= vdmp; END PROCESS DFF_CLK3; - VDM <= VDMP_I(7 DOWNTO 4) WHEN CLK_DDR3 = '1' ELSE VDMP_I(3 DOWNTO 0); + vdm <= vdmp_i(7 DOWNTO 4) WHEN clk_ddr3 = '1' ELSE vdmp_i(3 DOWNTO 0); SHIFT_CLK0: PROCESS - VARIABLE TMP : STD_LOGIC_VECTOR(4 DOWNTO 0); + VARIABLE tmp : STD_LOGIC_VECTOR(4 DOWNTO 0); BEGIN - WAIT UNTIL RISING_EDGE(CLK_DDR0); - TMP := SR_FIFO_WRE & TMP(4 DOWNTO 1); - FIFO_WRE <= TMP(0); + WAIT UNTIL RISING_EDGE(clk_ddr0); + tmp := sr_fifo_wre & tmp(4 DOWNTO 1); + fifo_wre <= tmp(0); END PROCESS SHIFT_CLK0; - with VDM_SEL select - VDM_C <= VDM_B WHEN x"0", - VDM_B(119 DOWNTO 0) & VDM_A(127 DOWNTO 120) WHEN x"1", - VDM_B(111 DOWNTO 0) & VDM_A(127 DOWNTO 112) WHEN x"2", - VDM_B(103 DOWNTO 0) & VDM_A(127 DOWNTO 104) WHEN x"3", - VDM_B(95 DOWNTO 0) & VDM_A(127 DOWNTO 96) WHEN x"4", - VDM_B(87 DOWNTO 0) & VDM_A(127 DOWNTO 88) WHEN x"5", - VDM_B(79 DOWNTO 0) & VDM_A(127 DOWNTO 80) WHEN x"6", - VDM_B(71 DOWNTO 0) & VDM_A(127 DOWNTO 72) WHEN x"7", - VDM_B(63 DOWNTO 0) & VDM_A(127 DOWNTO 64) WHEN x"8", - VDM_B(55 DOWNTO 0) & VDM_A(127 DOWNTO 56) WHEN x"9", - VDM_B(47 DOWNTO 0) & VDM_A(127 DOWNTO 48) WHEN x"A", - VDM_B(39 DOWNTO 0) & VDM_A(127 DOWNTO 40) WHEN x"B", - VDM_B(31 DOWNTO 0) & VDM_A(127 DOWNTO 32) WHEN x"C", - VDM_B(23 DOWNTO 0) & VDM_A(127 DOWNTO 24) WHEN x"D", - VDM_B(15 DOWNTO 0) & VDM_A(127 DOWNTO 16) WHEN x"E", - VDM_B(7 DOWNTO 0) & VDM_A(127 DOWNTO 8) WHEN x"F", + with vdm_sel select + vdm_c <= vdm_b WHEN x"0", + vdm_b(119 DOWNTO 0) & vdm_a(127 DOWNTO 120) WHEN x"1", + vdm_b(111 DOWNTO 0) & vdm_a(127 DOWNTO 112) WHEN x"2", + vdm_b(103 DOWNTO 0) & vdm_a(127 DOWNTO 104) WHEN x"3", + vdm_b(95 DOWNTO 0) & vdm_a(127 DOWNTO 96) WHEN x"4", + vdm_b(87 DOWNTO 0) & vdm_a(127 DOWNTO 88) WHEN x"5", + vdm_b(79 DOWNTO 0) & vdm_a(127 DOWNTO 80) WHEN x"6", + vdm_b(71 DOWNTO 0) & vdm_a(127 DOWNTO 72) WHEN x"7", + vdm_b(63 DOWNTO 0) & vdm_a(127 DOWNTO 64) WHEN x"8", + vdm_b(55 DOWNTO 0) & vdm_a(127 DOWNTO 56) WHEN x"9", + vdm_b(47 DOWNTO 0) & vdm_a(127 DOWNTO 48) WHEN x"A", + vdm_b(39 DOWNTO 0) & vdm_a(127 DOWNTO 40) WHEN x"B", + vdm_b(31 DOWNTO 0) & vdm_a(127 DOWNTO 32) WHEN x"C", + vdm_b(23 DOWNTO 0) & vdm_a(127 DOWNTO 24) WHEN x"D", + vdm_b(15 DOWNTO 0) & vdm_a(127 DOWNTO 16) WHEN x"E", + vdm_b(7 DOWNTO 0) & vdm_a(127 DOWNTO 8) WHEN x"F", (OTHERS => 'X') WHEN OTHERS; I_FIFO_DC0: lpm_fifo_dc0 PORT map( - aclr => FIFO_CLR_I, - data => VDM_C, - rdclk => CLK_PIXEL_I, - rdreq => FIFO_RD_REQ_512, - wrclk => CLK_DDR0, - wrreq => FIFO_WRE, - q => FIFO_D_OUT_512, + aclr => fifo_clr_i, + data => vdm_c, + rdclk => clk_pixel_i, + rdreq => fifo_rd_req_512, + wrclk => clk_ddr0, + wrreq => fifo_wre, + q => fifo_d_out_512, --rdempty =>, -- Not d. wrusedw => FIFO_MW ); @@ -490,20 +490,20 @@ BEGIN I_FIFO_DZ: lpm_fifoDZ PORT map( aclr => DOP_FIFO_CLR, - clock => CLK_PIXEL_I, - data => FIFO_D_OUT_512, - rdreq => FIFO_RD_REQ_128, - wrreq => FIFO_RD_REQ_512, - q => FIFO_D_OUT_128 + clock => clk_pixel_i, + data => fifo_d_out_512, + rdreq => fifo_rd_req_128, + wrreq => fifo_rd_req_512, + q => fifo_d_out_128 ); I_VIDEO_CTRL: VIDEO_CTRL PORT map( CLK_MAIN => CLK_MAIN, - fb_cs_n(1) => fb_cs_n(1), - fb_cs_n(2) => fb_cs_n(2), + fb_cs_n(1) => fb_cs_n(1), + fb_cs_n(2) => fb_cs_n(2), fb_wr_n => fb_wr_n, - fb_oe_n => fb_oe_n, + fb_oe_n => fb_oe_n, FB_SIZE(0) => FB_SIZE0, FB_SIZE(1) => FB_SIZE1, FB_ADR => FB_ADR, @@ -513,40 +513,40 @@ BEGIN CLK_VIDEO => CLK_VIDEO, VR_D => VR_D, VR_BUSY => VR_BUSY, - COLOR8 => COLOR8, - FBEE_CLUT_RD => CLUT_FBEE_RD, + color8 => color8, + FBEE_CLUT_RD => clut_fbee_rd, COLOR1 => COLOR1, - FALCON_CLUT_RDH => CLUT_FA_RDH, - FALCON_CLUT_RDL => CLUT_FA_RDL, - FALCON_CLUT_WR => CLUT_FA_WR, - CLUT_ST_RD => CLUT_ST_RD, - CLUT_ST_WR => CLUT_ST_WR, - CLUT_MUX_ADR => CLUT_ADR_MUX, + FALCON_CLUT_RDH => clut_fa_rdh, + FALCON_CLUT_RDL => clut_fa_rdl, + FALCON_CLUT_WR => clut_fa_wr, + clut_st_rd => clut_st_rd, + clut_st_wr => clut_st_wr, + CLUT_MUX_ADR => clut_adr_mux, HSYNC => HSYNC, VSYNC => VSYNC, - blank_n => blank_n, - sync_n => sync_n, - pd_vga_n => pd_vga_n, - FIFO_RDE => FIFO_RDE, - COLOR2 => COLOR2, - COLOR4 => COLOR4, - CLK_PIXEL => CLK_PIXEL_I, - CLUT_OFF => CLUT_OFF, + blank_n => blank_n, + sync_n => sync_n, + pd_vga_n => pd_vga_n, + fifo_rde => fifo_rde, + color2 => color2, + color4 => color4, + clk_pixel => clk_pixel_i, + clut_off => clut_off, BLITTER_ON => BLITTER_ON, VIDEO_RAM_CTR => VIDEO_RAM_CTR, VIDEO_MOD_TA => VIDEO_MOD_TA, - CCR => CCR, + ccr => ccr, CCSEL => CC_SEL, - FBEE_CLUT_WR => CLUT_FBEE_WR, - INTER_ZEI => INTER_ZEI, + FBEE_CLUT_WR => clut_fbee_wr, + inter_zei => inter_zei, DOP_FIFO_CLR => DOP_FIFO_CLR, VIDEO_RECONFIG => VIDEO_RECONFIG, VR_WR => VR_WR, VR_RD => VR_RD, - FIFO_CLR => FIFO_CLR_I, + fifo_clr => fifo_clr_i, DATA_IN => FB_AD_IN, - DATA_OUT => DATA_OUT_VIDEO_CTRL, - DATA_EN_H => DATA_EN_H_VIDEO_CTRL, - DATA_EN_L => DATA_EN_L_VIDEO_CTRL + DATA_OUT => data_out_video_ctrl, + DATA_EN_H => data_en_h_video_ctrl, + DATA_EN_L => data_en_l_video_ctrl ); END ARCHITECTURE; diff --git a/vhdl/testbenches/ddr2_ram_model.vhd b/vhdl/testbenches/ddr2_ram_model.vhd index c89f617..08f473f 100644 --- a/vhdl/testbenches/ddr2_ram_model.vhd +++ b/vhdl/testbenches/ddr2_ram_model.vhd @@ -42,13 +42,13 @@ PACKAGE ddr2_ram_model_pkg IS ras_n : IN STD_LOGIC; cas_n : IN STD_LOGIC; we_n : IN STD_LOGIC; - dm_rdqs : INOUT STD_LOGIC_VECTOR (DM_BITS - 1 DOWNTO 0); - ba : IN STD_LOGIC_VECTOR (BA_BITS - 1 DOWNTO 0); - addr : IN STD_LOGIC_VECTOR (ADDR_BITS - 1 DOWNTO 0); - dq : INOUT STD_LOGIC_VECTOR (DQ_BITS - 1 DOWNTO 0); - dqs : INOUT STD_LOGIC_VECTOR (DQS_BITS - 1 DOWNTO 0); - dqs_n : INOUT STD_LOGIC_VECTOR (DQS_BITS - 1 DOWNTO 0); - rdqs_n : OUT STD_LOGIC_VECTOR (DQS_BITS - 1 DOWNTO 0); + dm_rdqs : INOUT UNSIGNED (DM_BITS - 1 DOWNTO 0); + ba : IN UNSIGNED (BA_BITS - 1 DOWNTO 0); + addr : IN UNSIGNED (ADDR_BITS - 1 DOWNTO 0); + dq : INOUT UNSIGNED (DQ_BITS - 1 DOWNTO 0); + dqs : INOUT UNSIGNED (DQS_BITS - 1 DOWNTO 0); + dqs_n : INOUT UNSIGNED (DQS_BITS - 1 DOWNTO 0); + rdqs_n : OUT UNSIGNED (DQS_BITS - 1 DOWNTO 0); odt : IN STD_LOGIC ); END COMPONENT; @@ -87,13 +87,13 @@ ENTITY ddr2_ram_model IS ras_n : IN STD_LOGIC; cas_n : IN STD_LOGIC; we_n : IN STD_LOGIC; - dm_rdqs : INOUT STD_LOGIC_VECTOR (DM_BITS - 1 DOWNTO 0); - ba : IN STD_LOGIC_VECTOR (BA_BITS - 1 DOWNTO 0); - addr : IN STD_LOGIC_VECTOR (ADDR_BITS - 1 DOWNTO 0); - dq : INOUT STD_LOGIC_VECTOR (DQ_BITS - 1 DOWNTO 0); - dqs : INOUT STD_LOGIC_VECTOR (DQS_BITS - 1 DOWNTO 0); - dqs_n : INOUT STD_LOGIC_VECTOR (DQS_BITS - 1 DOWNTO 0); - rdqs_n : OUT STD_LOGIC_VECTOR (DQS_BITS - 1 DOWNTO 0); + dm_rdqs : INOUT UNSIGNED (DM_BITS - 1 DOWNTO 0); + ba : IN UNSIGNED (BA_BITS - 1 DOWNTO 0); + addr : IN UNSIGNED (ADDR_BITS - 1 DOWNTO 0); + dq : INOUT UNSIGNED (DQ_BITS - 1 DOWNTO 0); + dqs : INOUT UNSIGNED (DQS_BITS - 1 DOWNTO 0); + dqs_n : INOUT UNSIGNED (DQS_BITS - 1 DOWNTO 0); + rdqs_n : OUT UNSIGNED (DQS_BITS - 1 DOWNTO 0); odt : IN STD_LOGIC ); END ENTITY ddr2_ram_model; @@ -155,7 +155,7 @@ ARCHITECTURE rtl OF ddr2_ram_model IS -- mode registers SIGNAL burst_order : STD_LOGIC; - SIGNAL burst_length : STD_LOGIC_VECTOR (BL_BITS DOWNTO 0); + SIGNAL burst_length : UNSIGNED (BL_BITS DOWNTO 0); SIGNAL cas_latency : INTEGER; SIGNAL additive_latency : INTEGER; SIGNAL dll_reset : STD_LOGIC; @@ -163,9 +163,9 @@ ARCHITECTURE rtl OF ddr2_ram_model IS SIGNAL dll_en : STD_LOGIC; SIGNAL write_recovery : INTEGER; SIGNAL low_power : STD_LOGIC; - SIGNAL odt_rtt : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL odt_rtt : UNSIGNED (1 DOWNTO 0); SIGNAL odt_en : STD_LOGIC; - SIGNAL ocd : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL ocd : UNSIGNED (2 DOWNTO 0); SIGNAL dqs_n_en : STD_LOGIC; SIGNAL rdqs_en : STD_LOGIC; SIGNAL out_en : STD_LOGIC; @@ -173,7 +173,7 @@ ARCHITECTURE rtl OF ddr2_ram_model IS SIGNAL write_latency : INTEGER; TYPE cmd_type_t IS (LOAD_MODE, REFRESH, PRECHARGE, ACTIVATE, WRITE_CMD, READ_CMD, NOP, PWR_DOWN, SELF_REF); - TYPE cmd_type_encoding_array_t IS ARRAY(cmd_type_t) OF STD_LOGIC_VECTOR(3 DOWNTO 0); + TYPE cmd_type_encoding_array_t IS ARRAY(cmd_type_t) OF UNSIGNED(3 DOWNTO 0); CONSTANT cmd_type_encoding : cmd_type_encoding_array_t := ( "0000", "0001", "0010", "0011", @@ -195,16 +195,16 @@ ARCHITECTURE rtl OF ddr2_ram_model IS ); -- command state - SIGNAL active_bank : STD_LOGIC_VECTOR (BANKS - 1 DOWNTO 0); - SIGNAL auto_precharge_bank : STD_LOGIC_VECTOR (BANKS - 1 DOWNTO 0); - SIGNAL write_precharge_bank : STD_LOGIC_VECTOR (BANKS - 1 DOWNTO 0); - SIGNAL read_precharge_bank : STD_LOGIC_VECTOR (BANKS - 1 DOWNTO 0); + SIGNAL active_bank : UNSIGNED (BANKS - 1 DOWNTO 0); + SIGNAL auto_precharge_bank : UNSIGNED (BANKS - 1 DOWNTO 0); + SIGNAL write_precharge_bank : UNSIGNED (BANKS - 1 DOWNTO 0); + SIGNAL read_precharge_bank : UNSIGNED (BANKS - 1 DOWNTO 0); - TYPE row_array_t IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR (BANKS - 1 DOWNTO 0); + TYPE row_array_t IS ARRAY (INTEGER RANGE <>) OF UNSIGNED (BANKS - 1 DOWNTO 0); SIGNAL active_row : row_array_t (ROW_BITS - 1 DOWNTO 0); SIGNAL in_power_down : STD_LOGIC; SIGNAL in_self_refresh : STD_LOGIC; - SIGNAL init_mode_reg : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL init_mode_reg : UNSIGNED (3 DOWNTO 0); SIGNAL init_done : STD_LOGIC; SIGNAL init_step : INTEGER; SIGNAL er_trfc_max : STD_LOGIC; @@ -242,34 +242,34 @@ ARCHITECTURE rtl OF ddr2_ram_model IS SIGNAL tm_bank_read_end : time_array_t (BANKS - 1 DOWNTO 0); -- pipelines - SIGNAL al_pipeline : STD_LOGIC_VECTOR (MAX_PIPE DOWNTO 0); - SIGNAL wr_pipeline : STD_LOGIC_VECTOR (MAX_PIPE DOWNTO 0); - SIGNAL rd_pipeline : STD_LOGIC_VECTOR (MAX_PIPE DOWNTO 0); - SIGNAL odt_pipeline : STD_LOGIC_VECTOR (MAX_PIPE DOWNTO 0); + SIGNAL al_pipeline : UNSIGNED (MAX_PIPE DOWNTO 0); + SIGNAL wr_pipeline : UNSIGNED (MAX_PIPE DOWNTO 0); + SIGNAL rd_pipeline : UNSIGNED (MAX_PIPE DOWNTO 0); + SIGNAL odt_pipeline : UNSIGNED (MAX_PIPE DOWNTO 0); - TYPE ba_pipeline_t IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR (BA_BITS - 1 DOWNTO 0); + TYPE ba_pipeline_t IS ARRAY (NATURAL RANGE <>) OF UNSIGNED (BA_BITS - 1 DOWNTO 0); SIGNAL ba_pipeline : ba_pipeline_t (MAX_PIPE DOWNTO 0); - TYPE row_pipeline_t IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR (ROW_BITS - 1 DOWNTO 0); + TYPE row_pipeline_t IS ARRAY (NATURAL RANGE <>) OF UNSIGNED (ROW_BITS - 1 DOWNTO 0); SIGNAL row_pipeline : row_pipeline_t (MAX_PIPE DOWNTO 0); - TYPE col_pipeline_t IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR (COL_BITS - 1 DOWNTO 0); + TYPE col_pipeline_t IS ARRAY (NATURAL RANGE <>) OF UNSIGNED (COL_BITS - 1 DOWNTO 0); SIGNAL col_pipeline : col_pipeline_t (MAX_PIPE DOWNTO 0); SIGNAL prev_cke : STD_LOGIC; -- data state - SIGNAL memory_data : STD_LOGIC_VECTOR (BL_MAX * DQ_BITS - 1 DOWNTO 0); - SIGNAL bit_mask : STD_LOGIC_VECTOR (BL_MAX * DQ_BITS - 1 DOWNTO 0); - SIGNAL burst_position : STD_LOGIC_VECTOR (BL_BITS - 1 DOWNTO 0); - SIGNAL burst_cntr : STD_LOGIC_VECTOR (BL_BITS DOWNTO 0); - SIGNAL dq_temp : STD_LOGIC_VECTOR (DQ_BITS - 1 DOWNTO 0); - SIGNAL check_write_postamble: STD_LOGIC_VECTOR (35 DOWNTO 0); - SIGNAL check_write_preamble : STD_LOGIC_VECTOR (35 DOWNTO 0); - SIGNAL check_write_dqs_high : STD_LOGIC_VECTOR (35 DOWNTO 0); - SIGNAL check_write_dqs_low : STD_LOGIC_VECTOR (35 DOWNTO 0); - SIGNAL check_dm_tdipw : STD_LOGIC_VECTOR (17 DOWNTO 0); - SIGNAL check_dq_tdipw : STD_LOGIC_VECTOR (17 DOWNTO 0); + SIGNAL memory_data : UNSIGNED (BL_MAX * DQ_BITS - 1 DOWNTO 0); + SIGNAL bit_mask : UNSIGNED (BL_MAX * DQ_BITS - 1 DOWNTO 0); + SIGNAL burst_position : UNSIGNED (BL_BITS - 1 DOWNTO 0); + SIGNAL burst_cntr : UNSIGNED (BL_BITS DOWNTO 0); + SIGNAL dq_temp : UNSIGNED (DQ_BITS - 1 DOWNTO 0); + SIGNAL check_write_postamble: UNSIGNED (35 DOWNTO 0); + SIGNAL check_write_preamble : UNSIGNED (35 DOWNTO 0); + SIGNAL check_write_dqs_high : UNSIGNED (35 DOWNTO 0); + SIGNAL check_write_dqs_low : UNSIGNED (35 DOWNTO 0); + SIGNAL check_dm_tdipw : UNSIGNED (17 DOWNTO 0); + SIGNAL check_dq_tdipw : UNSIGNED (17 DOWNTO 0); -- data timers/counters SIGNAL tm_cke : TIME; @@ -319,12 +319,12 @@ ARCHITECTURE rtl OF ddr2_ram_model IS ); -- memory storage - TYPE mem_t IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR (BL_MAX * DQ_BITS - 1 DOWNTO 0); + TYPE mem_t IS ARRAY (INTEGER RANGE <>) OF UNSIGNED (BL_MAX * DQ_BITS - 1 DOWNTO 0); SIGNAL memory : mem_t(0 TO MEM_SIZE - 1); - TYPE adr_t IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR (MAX_BITS - 1 DOWNTO 0); + TYPE adr_t IS ARRAY (INTEGER RANGE <>) OF UNSIGNED (MAX_BITS - 1 DOWNTO 0); SIGNAL address : adr_t(0 TO MEM_SIZE - 1); - SIGNAL memory_index : STD_LOGIC_VECTOR(MEM_BITS DOWNTO 0); - SIGNAL memory_used : STD_LOGIC_VECTOR(MEM_BITS DOWNTO 0); + SIGNAL memory_index : UNSIGNED(MEM_BITS DOWNTO 0); + SIGNAL memory_used : UNSIGNED(MEM_BITS DOWNTO 0); SIGNAL ck_in : STD_LOGIC; SIGNAL ck_n_in : STD_LOGIC; @@ -333,17 +333,17 @@ ARCHITECTURE rtl OF ddr2_ram_model IS SIGNAL ras_n_in : STD_LOGIC; SIGNAL cas_n_in : STD_LOGIC; SIGNAL we_n_in : STD_LOGIC; - SIGNAL dm_in : STD_LOGIC_VECTOR (17 DOWNTO 0); - SIGNAL ba_in : STD_LOGIC_VECTOR (2 DOWNTO 0); - SIGNAL addr_in : STD_LOGIC_VECTOR (15 DOWNTO 0); - SIGNAL dq_in : STD_LOGIC_VECTOR (71 DOWNTO 0); - SIGNAL dqs_in : STD_LOGIC_VECTOR (35 DOWNTO 0); + SIGNAL dm_in : UNSIGNED (17 DOWNTO 0); + SIGNAL ba_in : UNSIGNED (2 DOWNTO 0); + SIGNAL addr_in : UNSIGNED (15 DOWNTO 0); + SIGNAL dq_in : UNSIGNED (71 DOWNTO 0); + SIGNAL dqs_in : UNSIGNED (35 DOWNTO 0); SIGNAL odt_in : STD_LOGIC; - SIGNAL dm_in_pos : STD_LOGIC_VECTOR (17 DOWNTO 0); - SIGNAL dm_in_neg : STD_LOGIC_VECTOR (17 DOWNTO 0); - SIGNAL dq_in_pos : STD_LOGIC_VECTOR (71 DOWNTO 0); - SIGNAL dq_in_neg : STD_LOGIC_VECTOR (71 DOWNTO 0); + SIGNAL dm_in_pos : UNSIGNED (17 DOWNTO 0); + SIGNAL dm_in_neg : UNSIGNED (17 DOWNTO 0); + SIGNAL dq_in_pos : UNSIGNED (71 DOWNTO 0); + SIGNAL dq_in_neg : UNSIGNED (71 DOWNTO 0); SIGNAL dq_in_valid : STD_LOGIC; SIGNAL dqs_in_valid : STD_LOGIC; SIGNAL wdqs_cntr : INTEGER; @@ -353,22 +353,22 @@ ARCHITECTURE rtl OF ddr2_ram_model IS SIGNAL wdqs_pos_cntr : integer_array_t(35 DOWNTO 0); SIGNAL b2b_write : STD_LOGIC; - SIGNAL prev_dqs_in : STD_LOGIC_VECTOR (35 DOWNTO 0); + SIGNAL prev_dqs_in : UNSIGNED (35 DOWNTO 0); SIGNAL diff_ck : STD_LOGIC; - SIGNAL dqs_even : STD_LOGIC_VECTOR (17 DOWNTO 0); - SIGNAL dqs_odd : STD_LOGIC_VECTOR (17 DOWNTO 0); - SIGNAL cmd_n_in : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL dqs_even : UNSIGNED (17 DOWNTO 0); + SIGNAL dqs_odd : UNSIGNED (17 DOWNTO 0); + SIGNAL cmd_n_in : UNSIGNED (3 DOWNTO 0); -- transmit SIGNAL dqs_out_en : STD_LOGIC; - SIGNAL dqs_out_en_dly : STD_LOGIC_VECTOR (DQS_BITS - 1 DOWNTO 0); + SIGNAL dqs_out_en_dly : UNSIGNED (DQS_BITS - 1 DOWNTO 0); SIGNAL dqs_out : STD_LOGIC; - SIGNAL dqs_out_dly : STD_LOGIC_VECTOR (DQS_BITS - 1 DOWNTO 0); + SIGNAL dqs_out_dly : UNSIGNED (DQS_BITS - 1 DOWNTO 0); SIGNAL dq_out_en : STD_LOGIC; - SIGNAL dq_out_en_dly : STD_LOGIC_VECTOR (DQ_BITS - 1 DOWNTO 0); - SIGNAL dq_out : STD_LOGIC_VECTOR (DQ_BITS - 1 DOWNTO 0); - SIGNAL dq_out_dly : STD_LOGIC_VECTOR (DQ_BITS - 1 DOWNTO 0); + SIGNAL dq_out_en_dly : UNSIGNED (DQ_BITS - 1 DOWNTO 0); + SIGNAL dq_out : UNSIGNED (DQ_BITS - 1 DOWNTO 0); + SIGNAL dq_out_dly : UNSIGNED (DQ_BITS - 1 DOWNTO 0); SIGNAL rdqsen_cntr : INTEGER; SIGNAL rdqs_cntr : INTEGER; SIGNAL rdqen_cntr : INTEGER; @@ -403,9 +403,9 @@ ARCHITECTURE rtl OF ddr2_ram_model IS PROCEDURE cmd_task( cke : IN STD_LOGIC; - cmd : IN STD_LOGIC_VECTOR (3 DOWNTO 0); - bank : IN STD_LOGIC_VECTOR (BA_BITS - 1 DOWNTO 0); - addr : IN STD_LOGIC_VECTOR (ADDR_BITS - 1 DOWNTO 0)) IS + cmd : IN UNSIGNED (3 DOWNTO 0); + bank : IN UNSIGNED (BA_BITS - 1 DOWNTO 0); + addr : IN UNSIGNED (ADDR_BITS - 1 DOWNTO 0)) IS VARIABLE i : UNSIGNED (BANKS DOWNTO 0); VARIABLE j : INTEGER; @@ -416,27 +416,27 @@ ARCHITECTURE rtl OF ddr2_ram_model IS PROCEDURE initialize( - SIGNAL mode_reg0 : IN STD_LOGIC_VECTOR (ADDR_BITS - 1 DOWNTO 0); - SIGNAL mode_reg1 : IN STD_LOGIC_VECTOR (ADDR_BITS - 1 DOWNTO 0); - SIGNAL mode_reg2 : IN STD_LOGIC_VECTOR (ADDR_BITS - 1 DOWNTO 0); - SIGNAL mode_reg3 : IN STD_LOGIC_VECTOR (ADDR_BITS - 1 DOWNTO 0)) IS + SIGNAL mode_reg0 : IN UNSIGNED (ADDR_BITS - 1 DOWNTO 0); + SIGNAL mode_reg1 : IN UNSIGNED (ADDR_BITS - 1 DOWNTO 0); + SIGNAL mode_reg2 : IN UNSIGNED (ADDR_BITS - 1 DOWNTO 0); + SIGNAL mode_reg3 : IN UNSIGNED (ADDR_BITS - 1 DOWNTO 0)) IS - CONSTANT AP_BIT : STD_LOGIC_VECTOR (ADDR_BITS - 1 DOWNTO 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(2 ** AP, ADDR_BITS)); + CONSTANT AP_BIT : UNSIGNED (ADDR_BITS - 1 DOWNTO 0) := UNSIGNED(TO_UNSIGNED(2 ** AP, ADDR_BITS)); BEGIN REPORT("at time " & TIME'IMAGE(NOW) & "INFO: performing initialization sequence"); cmd_task('1', cmd_type_encoding(NOP), (OTHERS => 'X'), (OTHERS => 'X')); cmd_task('1', cmd_type_encoding(PRECHARGE), (OTHERS => 'X'), AP_BIT); - cmd_task('1', cmd_type_encoding(LOAD_MODE), STD_LOGIC_VECTOR(TO_UNSIGNED(3, BA_BITS)), mode_reg3); - cmd_task('1', cmd_type_encoding(LOAD_MODE), STD_LOGIC_VECTOR(TO_UNSIGNED(2, BA_BITS)), mode_reg2); - cmd_task('1', cmd_type_encoding(LOAD_MODE), STD_LOGIC_VECTOR(TO_UNSIGNED(1, BA_BITS)), mode_reg1); - cmd_task('1', cmd_type_encoding(LOAD_MODE), STD_LOGIC_VECTOR(TO_UNSIGNED(0, BA_BITS)), mode_reg0 OR "100"); -- DLL reset + cmd_task('1', cmd_type_encoding(LOAD_MODE), UNSIGNED(TO_UNSIGNED(3, BA_BITS)), mode_reg3); + cmd_task('1', cmd_type_encoding(LOAD_MODE), UNSIGNED(TO_UNSIGNED(2, BA_BITS)), mode_reg2); + cmd_task('1', cmd_type_encoding(LOAD_MODE), UNSIGNED(TO_UNSIGNED(1, BA_BITS)), mode_reg1); + cmd_task('1', cmd_type_encoding(LOAD_MODE), UNSIGNED(TO_UNSIGNED(0, BA_BITS)), mode_reg0 OR "100"); -- DLL reset cmd_task('1', cmd_type_encoding(PRECHARGE), (OTHERS => 'X'), AP_BIT); -- Precharge all cmd_task('1', cmd_type_encoding(REFRESH), (OTHERS => 'X'), (OTHERS => 'X')); cmd_task('1', cmd_type_encoding(REFRESH), (OTHERS => 'X'), (OTHERS => 'X')); - cmd_task('1', cmd_type_encoding(LOAD_MODE), STD_LOGIC_VECTOR(TO_UNSIGNED(0, BA_BITS)), mode_reg0); - cmd_task('1', cmd_type_encoding(LOAD_MODE), STD_LOGIC_VECTOR(TO_UNSIGNED(1, BA_BITS)), mode_reg1 OR x"380"); -- OCD default - cmd_task('1', cmd_type_encoding(LOAD_MODE), STD_LOGIC_VECTOR(TO_UNSIGNED(1, BA_BITS)), mode_reg1); + cmd_task('1', cmd_type_encoding(LOAD_MODE), UNSIGNED(TO_UNSIGNED(0, BA_BITS)), mode_reg0); + cmd_task('1', cmd_type_encoding(LOAD_MODE), UNSIGNED(TO_UNSIGNED(1, BA_BITS)), mode_reg1 OR x"380"); -- OCD default + cmd_task('1', cmd_type_encoding(LOAD_MODE), UNSIGNED(TO_UNSIGNED(1, BA_BITS)), mode_reg1); cmd_task('1', cmd_type_encoding(NOP), (OTHERS => 'X'), (OTHERS => 'X')); END initialize; @@ -487,27 +487,27 @@ BEGIN PROCESS (dm_rdqs) BEGIN - dm_in <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(dm_rdqs), dm_in'LENGTH)) AFTER BUS_DELAY; + dm_in <= UNSIGNED(RESIZE(UNSIGNED(dm_rdqs), dm_in'LENGTH)) AFTER BUS_DELAY; END PROCESS; PROCESS (ba) BEGIN - ba_in <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(ba), ba_in'LENGTH)) AFTER BUS_DELAY; + ba_in <= UNSIGNED(RESIZE(UNSIGNED(ba), ba_in'LENGTH)) AFTER BUS_DELAY; END PROCESS; PROCESS (addr) BEGIN - addr_in <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(addr), addr_in'LENGTH)) AFTER BUS_DELAY; + addr_in <= UNSIGNED(RESIZE(UNSIGNED(addr), addr_in'LENGTH)) AFTER BUS_DELAY; END PROCESS; PROCESS (dq) BEGIN - dq_in <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(dq), dq_in'LENGTH)) AFTER BUS_DELAY; + dq_in <= UNSIGNED(RESIZE(UNSIGNED(dq), dq_in'LENGTH)) AFTER BUS_DELAY; END PROCESS; PROCESS (dqs, dqs_n) BEGIN - dqs_in <= STD_LOGIC_VECTOR(SHIFT_LEFT(RESIZE(UNSIGNED(dqs_n), dqs_in'LENGTH), 18)) OR STD_LOGIC_VECTOR(RESIZE(UNSIGNED(dqs), dqs_in'LENGTH)); + dqs_in <= UNSIGNED(SHIFT_LEFT(RESIZE(UNSIGNED(dqs_n), dqs_in'LENGTH), 18)) OR UNSIGNED(RESIZE(UNSIGNED(dqs), dqs_in'LENGTH)); END PROCESS; PROCESS (odt) @@ -533,25 +533,25 @@ BEGIN cmd_n_in <= '0' & ras_n_in & cas_n_in & we_n_in WHEN NOT(cs_n_in) ELSE cmd_type_encoding(NOP); -- bufif1 buf_dqs - dqs <= dqs_out_dly WHEN (dqs_out_en_dly AND STD_LOGIC_VECTOR'(0 TO DQS_BITS - 1 => out_en)) /= x"0" ELSE (OTHERS => 'Z'); + dqs <= dqs_out_dly WHEN (dqs_out_en_dly AND UNSIGNED'(0 TO DQS_BITS - 1 => out_en)) /= x"0" ELSE (OTHERS => 'Z'); -- bufif1 buf_dm dm_rdqs <= dqs_out_dly WHEN (dqs_out_en_dly AND - STD_LOGIC_VECTOR'(0 TO DM_BITS - 1 => out_en) AND - STD_LOGIC_VECTOR'(0 TO DM_BITS - 1 => rdqs_en)) /= x"0" ELSE (OTHERS => 'Z'); + UNSIGNED'(0 TO DM_BITS - 1 => out_en) AND + UNSIGNED'(0 TO DM_BITS - 1 => rdqs_en)) /= x"0" ELSE (OTHERS => 'Z'); -- bufif1 buf_dqs_n dqs_n <= NOT dqs_out_dly WHEN (dqs_out_en_dly AND - STD_LOGIC_VECTOR'(0 TO DQS_BITS - 1 => out_en) AND - STD_LOGIC_VECTOR'(0 TO DQS_BITS - 1 => dqs_n_en)) /= x"0" ELSE (OTHERS => 'Z'); + UNSIGNED'(0 TO DQS_BITS - 1 => out_en) AND + UNSIGNED'(0 TO DQS_BITS - 1 => dqs_n_en)) /= x"0" ELSE (OTHERS => 'Z'); -- bufif1 buf_rdqs_n rdqs_n <= NOT dqs_out_dly WHEN (dqs_out_en_dly AND - STD_LOGIC_VECTOR'(0 TO DQS_BITS - 1 => out_en) AND - STD_LOGIC_VECTOR'(0 to DQS_BITS - 1 => dqs_n_en) AND - STD_LOGIC_VECTOR'(0 TO DQS_BITS - 1 => rdqs_en)) /= x"0" ELSE (OTHERS => 'Z'); + UNSIGNED'(0 TO DQS_BITS - 1 => out_en) AND + UNSIGNED'(0 to DQS_BITS - 1 => dqs_n_en) AND + UNSIGNED'(0 TO DQS_BITS - 1 => rdqs_en)) /= x"0" ELSE (OTHERS => 'Z'); -- bufif1 buf_dq dq <= dq_out_dly WHEN (dq_out_en_dly AND - STD_LOGIC_VECTOR'(0 TO DQ_BITS - 1 => out_en)) /= x"0" ELSE (OTHERS => 'Z'); + UNSIGNED'(0 TO DQ_BITS - 1 => out_en)) /= x"0" ELSE (OTHERS => 'Z'); -- initial block init : PROCESS @@ -647,17 +647,17 @@ BEGIN err : PROCESS PROCEDURE chk_err( - samebank : IN STD_LOGIC_VECTOR (0 DOWNTO 0); - bank : IN STD_LOGIC_VECTOR (BA_BITS - 1 DOWNTO 0); - fromcmd : IN STD_LOGIC_VECTOR (3 DOWNTO 0); - cmd : IN STD_LOGIC_VECTOR (3 DOWNTO 0) + samebank : IN UNSIGNED (0 DOWNTO 0); + bank : IN UNSIGNED (BA_BITS - 1 DOWNTO 0); + fromcmd : IN UNSIGNED (3 DOWNTO 0); + cmd : IN UNSIGNED (3 DOWNTO 0) ) IS VARIABLE err : STD_LOGIC; BEGIN -- all matching case expression will be evaluated - CASE? (STD_LOGIC_VECTOR'(samebank & fromcmd & cmd)) IS + CASE? (UNSIGNED'(samebank & fromcmd & cmd)) IS WHEN "0" & cmd_type_encoding(LOAD_MODE) & "0---" => IF ck_cntr - ck_load_mode < TMRD THEN REPORT("at time " & TIME'IMAGE(NOW) & " ERROR: tMRD violation during " & cmd_string(TO_INTEGER(UNSIGNED(cmd)))); diff --git a/vhdl/testbenches/ddr_ctlr_tb.vhd b/vhdl/testbenches/ddr_ctlr_tb.vhd index d38eb0d..4a0935e 100644 --- a/vhdl/testbenches/ddr_ctlr_tb.vhd +++ b/vhdl/testbenches/ddr_ctlr_tb.vhd @@ -17,7 +17,7 @@ ARCHITECTURE beh OF ddr_ctlr_tb IS SIGNAL clock : STD_LOGIC := '0'; -- main clock SIGNAL ddr_clk : STD_LOGIC := '0'; -- ddr clock - SIGNAL fb_adr : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL fb_adr : UNSIGNED(31 DOWNTO 0); SIGNAL ddr_sync_66m : STD_LOGIC := '0'; SIGNAL fb_cs1_n : STD_LOGIC; SIGNAL fb_oe_n : STD_LOGIC := '1'; -- only write cycles for now @@ -26,33 +26,33 @@ ARCHITECTURE beh OF ddr_ctlr_tb IS SIGNAL fb_ale : STD_LOGIC := 'Z'; -- defined reset state SIGNAL fb_wr_n : STD_LOGIC; SIGNAL fifo_clr : STD_LOGIC; - SIGNAL video_ram_ctr : STD_LOGIC_VECTOR(15 DOWNTO 0); - SIGNAL blitter_adr : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL video_ram_ctr : UNSIGNED(15 DOWNTO 0); + SIGNAL blitter_adr : UNSIGNED(31 DOWNTO 0); SIGNAL blitter_sig : STD_LOGIC; SIGNAL blitter_wr : STD_LOGIC; SIGNAL ddrclk0 : STD_LOGIC; SIGNAL clk_33m : STD_LOGIC := '0'; SIGNAL fifo_mw : UNSIGNED (8 DOWNTO 0) := (OTHERS => '0'); - SIGNAL va : STD_LOGIC_VECTOR(12 DOWNTO 0); + SIGNAL va : UNSIGNED(12 DOWNTO 0); SIGNAL vwe_n : STD_LOGIC; SIGNAL vras_n : STD_LOGIC; SIGNAL vcs_n : STD_LOGIC; SIGNAL vcke : STD_LOGIC; SIGNAL vcas_n : STD_LOGIC; - SIGNAL fb_le : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL fb_vdoe : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL fb_le : UNSIGNED(3 DOWNTO 0); + SIGNAL fb_vdoe : UNSIGNED(3 DOWNTO 0); SIGNAL sr_fifo_wre : STD_LOGIC; SIGNAL sr_ddr_fb : STD_LOGIC; SIGNAL sr_ddr_wr : STD_LOGIC; SIGNAL sr_ddrwr_d_sel : STD_LOGIC; - SIGNAL sr_vdmp : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL sr_vdmp : UNSIGNED(7 DOWNTO 0); SIGNAL video_ddr_ta : STD_LOGIC; SIGNAL sr_blitter_dack : STD_LOGIC; - SIGNAL ba : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL ba : UNSIGNED(1 DOWNTO 0); SIGNAL ddrwr_d_sel1 : STD_LOGIC; - SIGNAL vdm_sel : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL data_in : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL data_out : STD_LOGIC_VECTOR(31 DOWNTO 16); + SIGNAL vdm_sel : UNSIGNED(3 DOWNTO 0); + SIGNAL data_in : UNSIGNED(31 DOWNTO 0); + SIGNAL data_out : UNSIGNED(31 DOWNTO 16); SIGNAL data_en_h : STD_LOGIC; SIGNAL data_en_l : STD_LOGIC; @@ -63,109 +63,109 @@ BEGIN i_ddr_ctrl : DDR_CTRL PORT map ( - clk_main => clock, - ddr_sync_66m => ddr_sync_66m, - fb_adr => fb_adr, - fb_cs1_n => fb_cs1_n, - fb_oe_n => fb_oe_n, - fb_size0 => fb_size0, - fb_size1 => fb_size1, - fb_ale => fb_ale, - FB_WR_n => fb_wr_n, - fifo_clr => fifo_clr, + clk_main => clock, + ddr_sync_66m => ddr_sync_66m, + fb_adr => fb_adr, + fb_cs1_n => fb_cs1_n, + fb_oe_n => fb_oe_n, + fb_size0 => fb_size0, + fb_size1 => fb_size1, + fb_ale => fb_ale, + FB_WR_n => fb_wr_n, + fifo_clr => fifo_clr, video_control_register => video_ram_ctr, - blitter_adr => blitter_adr, - blitter_sig => blitter_sig, - blitter_wr => blitter_wr, - ddrclk0 => ddrclk0, - clk_33m => clk_33m, - fifo_mw => fifo_mw, - va => va, - vwe_n => vwe_n, - vras_n => vras_n, - vcs_n => vcs_n, - vcke => vcke, - vcas_n => vcas_n, - fb_le => fb_le, - fb_vdoe => fb_vdoe, - sr_fifo_wre => sr_fifo_wre, - sr_ddr_fb => sr_ddr_fb, - sr_ddr_wr => sr_ddr_wr, - sr_ddrwr_d_sel => sr_ddrwr_d_sel, - sr_vdmp => sr_vdmp, - video_ddr_ta => video_ddr_ta, + blitter_adr => blitter_adr, + blitter_sig => blitter_sig, + blitter_wr => blitter_wr, + ddrclk0 => ddrclk0, + clk_33m => clk_33m, + fifo_mw => fifo_mw, + va => va, + vwe_n => vwe_n, + vras_n => vras_n, + vcs_n => vcs_n, + vcke => vcke, + vcas_n => vcas_n, + fb_le => fb_le, + fb_vdoe => fb_vdoe, + sr_fifo_wre => sr_fifo_wre, + sr_ddr_fb => sr_ddr_fb, + sr_ddr_wr => sr_ddr_wr, + sr_ddrwr_d_sel => sr_ddrwr_d_sel, + sr_vdmp => sr_vdmp, + video_ddr_ta => video_ddr_ta, sr_blitter_dack => sr_blitter_dack, - ba => ba, - ddrwr_d_sel1 => ddrwr_d_sel1, - vdm_sel => vdm_sel, - data_in => data_in, - data_out => data_out, - data_en_h => data_en_h, - data_en_l => data_en_l + ba => ba, + ddrwr_d_sel1 => ddrwr_d_sel1, + vdm_sel => vdm_sel, + data_in => data_in, + data_out => data_out, + data_en_h => data_en_h, + data_en_l => data_en_l ); i_ddr2_ram_1 : ddr2_ram_model GENERIC MAP ( - VERBOSE => TRUE, -- define if you want additional debug output + VERBOSE => TRUE, -- define if you want additional debug output - CLOCK_TICK => (1000000 / 132000) * 1 ps, -- time for one clock tick + CLOCK_TICK => (1000000 / 132000) * 1 ps, -- time for one clock tick - BA_BITS => 2, -- number of banks - ADDR_BITS => 13, -- number of address bits - DM_BITS => 2, -- number of data mask bits - DQ_BITS => 8, -- number of data bits - DQS_BITS => 2 -- number of data strobes + BA_BITS => 2, -- number of banks + ADDR_BITS => 13, -- number of address bits + DM_BITS => 2, -- number of data mask bits + DQ_BITS => 8, -- number of data bits + DQS_BITS => 2 -- number of data strobes ) PORT map ( - ck => ddrclk0, - ck_n => NOT ddrclk0, - cke => vcke, - cs_n => vcs_n, - ras_n => vras_n, - cas_n => vcas_n, - we_n => vwe_n, - dm_rdqs(0) => data_en_l, - dm_rdqs(1) => data_en_h, - ba => ba, - addr => va, - dq => sr_vdmp, - dqs(0) => data_en_l, - dqs(1) => data_en_h, - odt => '0' + ck => ddrclk0, + ck_n => NOT ddrclk0, + cke => vcke, + cs_n => vcs_n, + ras_n => vras_n, + cas_n => vcas_n, + we_n => vwe_n, + dm_rdqs(0) => data_en_l, + dm_rdqs(1) => data_en_h, + ba => ba, + addr => va, + dq => sr_vdmp, + dqs(0) => data_en_l, + dqs(1) => data_en_h, + odt => '0' ); i_ddr2_ram_2 : ddr2_ram_model GENERIC MAP ( - VERBOSE => TRUE, -- define if you want additional debug output + VERBOSE => TRUE, -- define if you want additional debug output - CLOCK_TICK => (1000000 / 132000) * 1 ps, -- time for one clock tick + CLOCK_TICK => (1000000 / 132000) * 1 ps, -- time for one clock tick - BA_BITS => 2, -- number of banks - ADDR_BITS => 13, -- number of address bits - DM_BITS => 2, -- number of data mask bits - DQ_BITS => 8, -- number of data bits - DQS_BITS => 2 -- number of data strobes + BA_BITS => 2, -- number of banks + ADDR_BITS => 13, -- number of address bits + DM_BITS => 2, -- number of data mask bits + DQ_BITS => 8, -- number of data bits + DQS_BITS => 2 -- number of data strobes ) PORT map ( - ck => ddrclk0, - ck_n => NOT ddrclk0, - cke => vcke, - cs_n => vcs_n, - ras_n => vras_n, - cas_n => vcas_n, - we_n => vwe_n, - dm_rdqs(0) => data_en_l, - dm_rdqs(1) => data_en_h, - ba => ba, - addr => va, - dq => sr_vdmp, - dqs(0) => data_en_l, - dqs(1) => data_en_h, - odt => '0' + ck => ddrclk0, + ck_n => NOT ddrclk0, + cke => vcke, + cs_n => vcs_n, + ras_n => vras_n, + cas_n => vcas_n, + we_n => vwe_n, + dm_rdqs(0) => data_en_l, + dm_rdqs(1) => data_en_h, + ba => ba, + addr => va, + dq => sr_vdmp, + dqs(0) => data_en_l, + dqs(1) => data_en_h, + odt => '0' ); stimulate_main_clock : process @@ -188,7 +188,7 @@ BEGIN END process; stimulate : process - VARIABLE adr : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"00000000"; + VARIABLE adr : UNSIGNED (31 DOWNTO 0) := x"00000000"; BEGIN WAIT UNTIL RISING_EDGE(clock); CASE bus_state IS @@ -210,7 +210,7 @@ BEGIN fb_cs1_n <= '0'; bus_state <= S3; WHEN S3 => - fb_adr <= STD_LOGIC_VECTOR(UNSIGNED(fb_adr) + 4); + fb_adr <= fb_adr + 4; bus_state <= S0; fb_wr_n <= 'Z'; WHEN others =>