added Firetos' radeon PCI driver

2013-12-26 21:20:47 +00:00
parent 9ca272dd76
commit 0d845e2c14
23 changed files with 9822 additions and 93 deletions
--- a/4
+++ b/4
@@ -43,7 +43,7 @@ TRGTDIRS= ./firebee ./m5484lite
 OBJDIRS=$(patsubst %, %/objs,$(TRGTDIRS))
 TOOLDIR=util

-VPATH=dma exe flash fs if kbd pci spi sys usb net util video xhdi
+VPATH=dma exe flash fs if kbd pci spi sys usb net util video radeon xhdi

 # Linker control file. The final $(LDCFILE) is intermediate only (preprocessed  version of $(LDCSRC)
 LDCFILE=bas.lk
@@ -106,6 +106,8 @@ CSRCS= \
 	videl.c \
 	video.c \
 	\
+	radeon_base.c \
+	\
 	basflash.c \
 	basflash_start.c 

--- a/dma/MCD_dmaApi.c
+++ b/dma/MCD_dmaApi.c
@@ -36,9 +36,12 @@ TaskTableEntry *MCD_modelTaskTable;
 * status, etc.
 */
 static int MCD_chStatus[NCHANNELS] =
-{ MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA,
-		MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA,
-		MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA };
+{
+	MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA,
+	MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA,
+	MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA,
+	MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA
+};

 /*
 * Prototypes for local functions
@@ -349,17 +352,17 @@ int MCD_dmaStatus(int channel)
 * Returns:     MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
 */

-int MCD_startDma(int channel, /* the channel on which to run the DMA */
-int8_t *srcAddr, /* the address to move data from, or physical buffer-descriptor address */
-int16_t srcIncr, /* the amount to increment the source address per transfer */
-int8_t *destAddr, /* the address to move data to */
-int16_t destIncr, /* the amount to increment the destination address per transfer */
-uint32_t dmaSize, /* the number of bytes to transfer independent of the transfer size */
-uint32_t xferSize, /* the number bytes in of each data movement (1, 2, or 4) */
-uint32_t initiator, /* what device initiates the DMA */
-int priority, /* priority of the DMA */
-uint32_t flags, /* flags describing the DMA */
-uint32_t funcDesc /* a description of byte swapping, bit swapping, and CRC actions */
+int __attribute__((flatten)) MCD_startDma(int channel, /* the channel on which to run the DMA */
+		int8_t *srcAddr, /* the address to move data from, or physical buffer-descriptor address */
+		int16_t srcIncr, /* the amount to increment the source address per transfer */
+		int8_t *destAddr, /* the address to move data to */
+		int16_t destIncr, /* the amount to increment the destination address per transfer */
+		uint32_t dmaSize, /* the number of bytes to transfer independent of the transfer size */
+		uint32_t xferSize, /* the number bytes in of each data movement (1, 2, or 4) */
+		uint32_t initiator, /* what device initiates the DMA */
+		int priority, /* priority of the DMA */
+		uint32_t flags, /* flags describing the DMA */
+		uint32_t funcDesc /* a description of byte swapping, bit swapping, and CRC actions */
 #ifdef MCD_NEED_ADDR_TRANS
 		int8_t *srcAddrVirt /* virtual buffer descriptor address TBD*/
 #endif
@@ -412,15 +415,15 @@ uint32_t funcDesc /* a description of byte swapping, bit swapping, and CRC actio
 #ifdef MCD_INCLUDE_EU /* may move this to EU specific calls */
 	realFuncArray = (uint32_t *) (MCD_taskTable[channel].FDTandFlags & 0xffffff00);
 	/* Modify the LURC's normal and byte-residue-loop functions according to parameter. */
-	realFuncArray[(LURC*16)] = xferSize == 4 ?
-	funcDesc : xferSize == 2 ?
-	funcDesc & 0xfffff00f : funcDesc & 0xffff000f;
+	realFuncArray[(LURC*16)] = xferSize == 4 ? funcDesc : xferSize == 2 ? funcDesc & 0xfffff00f : funcDesc & 0xffff000f;
 	realFuncArray[(LURC*16+1)] = (funcDesc & MCD_BYTE_SWAP_KILLER) | MCD_NO_BYTE_SWAP_ATALL;
 #endif
-	/* Write the initiator field in the TCR, and also set the initiator-hold
-	 bit.  Note that,due to a hardware quirk, this could collide with an
-	 MDE access to the initiator-register file, so we have to verify that the write
-	 reads back correctly. */
+	/*
+	 * Write the initiator field in the TCR, and also set the initiator-hold
+	 * bit.  Note that,due to a hardware quirk, this could collide with an
+	 * MDE access to the initiator-register file, so we have to verify that the write
+	 * reads back correctly.
+	 */

 	MCD_dmaBar->taskControl[channel] = (initiator << 8) | TASK_CTL_HIPRITSKEN
 			| TASK_CTL_HLDINITNUM;
@@ -436,6 +439,7 @@ uint32_t funcDesc /* a description of byte swapping, bit swapping, and CRC actio
 	}

 	MCD_dmaBar->priority[channel] = (uint8_t) priority & PRIORITY_PRI_MASK;
+
 	/* should be albe to handle this stuff with only one write to ts reg - tbd */
 	if (channel < 8 && channel >= 0)
 	{
@@ -460,8 +464,7 @@ uint32_t funcDesc /* a description of byte swapping, bit swapping, and CRC actio
 		MCD_taskTable[channel].TDTstart =
 				MCD_modelTaskTable[TASK_FECTX].TDTstart;
 		MCD_taskTable[channel].TDTend = MCD_modelTaskTable[TASK_FECTX].TDTend;
-		MCD_startDmaENetXmit(srcAddr, srcAddr, destAddr, MCD_taskTable,
-				channel);
+		MCD_startDmaENetXmit(srcAddr, srcAddr, destAddr, MCD_taskTable, channel);
 	}
 	else if (flags & MCD_FECRX_DMA)
 	{
@@ -473,10 +476,12 @@ uint32_t funcDesc /* a description of byte swapping, bit swapping, and CRC actio
 	}
 	else if (flags & MCD_SINGLE_DMA)
 	{
-		/* this buffer descriptor is used for storing off initial parameters for later
-		 progress query calculation and for the DMA to write the resulting checksum
-		 The DMA does not use this to determine how to operate, that info is passed
-		 with the init routine*/
+		/*
+		 * this buffer descriptor is used for storing off initial parameters for later
+		 * progress query calculation and for the DMA to write the resulting checksum
+		 * The DMA does not use this to determine how to operate, that info is passed
+		 * with the init routine
+		 */
 		MCD_relocBuffDesc[channel].srcAddr = srcAddr;
 		MCD_relocBuffDesc[channel].destAddr = destAddr;
 		MCD_relocBuffDesc[channel].lastDestAddr = destAddr; /* definitely not its final value */
@@ -529,6 +534,7 @@ uint32_t funcDesc /* a description of byte swapping, bit swapping, and CRC actio
 		((volatile int *) MCD_taskTable[channel].contextSaveSpace)[DESTPTR
 				+ CSAVE_OFFSET] = (int) ((MCD_bufDesc*) srcAddr)->destAddr;
 #else /* if using address translation, need the virtual addr of the first buffdesc */
+
 		((volatile int *)MCD_taskTable[channel].contextSaveSpace)[SRCPTR + CSAVE_OFFSET]
 		= (int)((MCD_bufDesc*) srcAddrVirt)->srcAddr;
 		((volatile int *)MCD_taskTable[channel].contextSaveSpace)[DESTPTR + CSAVE_OFFSET]
--- a/dma/MCD_tasksInit.c
+++ b/dma/MCD_tasksInit.c
@@ -57,7 +57,7 @@ void  MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr, int xfer
 * Task 1
 */
 
-void  MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel)
+void  MCD_startDmaSingleNoEu(int8_t *srcAddr, short srcIncr, int8_t *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel)
 {

    MCD_SET_VAR(taskTable+channel, 7, (uint32_t)srcAddr);    /* var[7] */
@@ -127,7 +127,7 @@ void  MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr, int xferSi
 * Task 3
 */
 
-void  MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel)
+void  MCD_startDmaSingleEu(int8_t *srcAddr, short srcIncr, int8_t *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel)
 {

    MCD_SET_VAR(taskTable+channel, 8, (uint32_t)srcAddr);    /* var[8] */
@@ -161,7 +161,7 @@ void  MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr, short d
 * Task 4
 */
 
-void  MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr, volatile TaskTableEntry *taskTable, int channel)
+void  MCD_startDmaENetRcv(int8_t *bDBase, int8_t *currBD, int8_t *rcvFifoPtr, volatile TaskTableEntry *taskTable, int channel)
 {

    MCD_SET_VAR(taskTable+channel, 0, (uint32_t)bDBase); /* var[0] */
@@ -191,7 +191,7 @@ void  MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr, volatile
 * Task 5
 */
 
-void  MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr, volatile TaskTableEntry *taskTable, int channel)
+void  MCD_startDmaENetXmit(int8_t *bDBase, int8_t *currBD, int8_t *xmitFifoPtr, volatile TaskTableEntry *taskTable, int channel)
 {

    MCD_SET_VAR(taskTable+channel, 0, (uint32_t)bDBase); /* var[0] */
--- a/include/MCD_tasksInit.h
+++ b/include/MCD_tasksInit.h
@@ -15,7 +15,7 @@ void  MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr, int xfer
 /*
 * Task 1
 */
-void  MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel);
+void  MCD_startDmaSingleNoEu(int8_t *srcAddr, short srcIncr, int8_t *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel);


 /*
@@ -27,18 +27,18 @@ void  MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr, int xferSi
 /*
 * Task 3
 */
-void  MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel);
+void  MCD_startDmaSingleEu(int8_t *srcAddr, short srcIncr, int8_t *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel);


 /*
 * Task 4
 */
-void  MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr, volatile TaskTableEntry *taskTable, int channel);
+void  MCD_startDmaENetRcv(int8_t *bDBase, int8_t *currBD, int8_t *rcvFifoPtr, volatile TaskTableEntry *taskTable, int channel);


 /*
 * Task 5
 */
-void  MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr, volatile TaskTableEntry *taskTable, int channel);
+void  MCD_startDmaENetXmit(int8_t *bDBase, int8_t *currBD, int8_t *xmitFifoPtr, volatile TaskTableEntry *taskTable, int channel);

 #endif  /* MCD_TSK_INIT_H */
--- a/include/ati_ids.h
+++ b/include/ati_ids.h
@@ -0,0 +1,211 @@
+/*
+ * ATI PCI IDs from XFree86, kept here to make sync'ing with
+ * XFree much simpler. Currently, this list is only used by
+ * radeonfb
+ */
+
+#define PCI_CHIP_RV380_3150             0x3150
+#define PCI_CHIP_RV380_3151             0x3151
+#define PCI_CHIP_RV380_3152             0x3152
+#define PCI_CHIP_RV380_3153             0x3153
+#define PCI_CHIP_RV380_3154             0x3154
+#define PCI_CHIP_RV380_3156             0x3156
+#define PCI_CHIP_RV380_3E50             0x3E50
+#define PCI_CHIP_RV380_3E51             0x3E51
+#define PCI_CHIP_RV380_3E52             0x3E52
+#define PCI_CHIP_RV380_3E53             0x3E53
+#define PCI_CHIP_RV380_3E54             0x3E54
+#define PCI_CHIP_RV380_3E56             0x3E56
+#define PCI_CHIP_RS100_4136		0x4136
+#define PCI_CHIP_RS200_4137		0x4137
+#define PCI_CHIP_R300_AD		0x4144
+#define PCI_CHIP_R300_AE		0x4145
+#define PCI_CHIP_R300_AF		0x4146
+#define PCI_CHIP_R300_AG		0x4147
+#define PCI_CHIP_R350_AH                0x4148
+#define PCI_CHIP_R350_AI                0x4149
+#define PCI_CHIP_R350_AJ                0x414A
+#define PCI_CHIP_R350_AK                0x414B
+#define PCI_CHIP_RV350_AP               0x4150
+#define PCI_CHIP_RV350_AQ               0x4151
+#define PCI_CHIP_RV360_AR               0x4152
+#define PCI_CHIP_RV350_AS               0x4153
+#define PCI_CHIP_RV350_AT               0x4154
+#define PCI_CHIP_RV350_AV               0x4156
+#define PCI_CHIP_MACH32			0x4158
+#define PCI_CHIP_RS250_4237		0x4237
+#define PCI_CHIP_R200_BB		0x4242
+#define PCI_CHIP_R200_BC		0x4243
+#define PCI_CHIP_RS100_4336		0x4336
+#define PCI_CHIP_RS200_4337		0x4337
+#define PCI_CHIP_MACH64CT		0x4354
+#define PCI_CHIP_MACH64CX		0x4358
+#define PCI_CHIP_RS250_4437		0x4437
+#define PCI_CHIP_MACH64ET		0x4554
+#define PCI_CHIP_MACH64GB		0x4742
+#define PCI_CHIP_MACH64GD		0x4744
+#define PCI_CHIP_MACH64GI		0x4749
+#define PCI_CHIP_MACH64GL		0x474C
+#define PCI_CHIP_MACH64GM		0x474D
+#define PCI_CHIP_MACH64GN		0x474E
+#define PCI_CHIP_MACH64GO		0x474F
+#define PCI_CHIP_MACH64GP		0x4750
+#define PCI_CHIP_MACH64GQ		0x4751
+#define PCI_CHIP_MACH64GR		0x4752
+#define PCI_CHIP_MACH64GS		0x4753
+#define PCI_CHIP_MACH64GT		0x4754
+#define PCI_CHIP_MACH64GU		0x4755
+#define PCI_CHIP_MACH64GV		0x4756
+#define PCI_CHIP_MACH64GW		0x4757
+#define PCI_CHIP_MACH64GX		0x4758
+#define PCI_CHIP_MACH64GY		0x4759
+#define PCI_CHIP_MACH64GZ		0x475A
+#define PCI_CHIP_RV250_Id		0x4964
+#define PCI_CHIP_RV250_Ie		0x4965
+#define PCI_CHIP_RV250_If		0x4966
+#define PCI_CHIP_RV250_Ig		0x4967
+#define PCI_CHIP_R420_JH                0x4A48
+#define PCI_CHIP_R420_JI                0x4A49
+#define PCI_CHIP_R420_JJ                0x4A4A
+#define PCI_CHIP_R420_JK                0x4A4B
+#define PCI_CHIP_R420_JL                0x4A4C
+#define PCI_CHIP_R420_JM                0x4A4D
+#define PCI_CHIP_R420_JN                0x4A4E
+#define PCI_CHIP_R420_JP                0x4A50
+#define PCI_CHIP_MACH64LB		0x4C42
+#define PCI_CHIP_MACH64LD		0x4C44
+#define PCI_CHIP_RAGE128LE		0x4C45
+#define PCI_CHIP_RAGE128LF		0x4C46
+#define PCI_CHIP_MACH64LG		0x4C47
+#define PCI_CHIP_MACH64LI		0x4C49
+#define PCI_CHIP_MACH64LM		0x4C4D
+#define PCI_CHIP_MACH64LN		0x4C4E
+#define PCI_CHIP_MACH64LP		0x4C50
+#define PCI_CHIP_MACH64LQ		0x4C51
+#define PCI_CHIP_MACH64LR		0x4C52
+#define PCI_CHIP_MACH64LS		0x4C53
+#define PCI_CHIP_MACH64LT		0x4C54
+#define PCI_CHIP_RADEON_LW		0x4C57
+#define PCI_CHIP_RADEON_LX		0x4C58
+#define PCI_CHIP_RADEON_LY		0x4C59
+#define PCI_CHIP_RADEON_LZ		0x4C5A
+#define PCI_CHIP_RV250_Ld		0x4C64
+#define PCI_CHIP_RV250_Le		0x4C65
+#define PCI_CHIP_RV250_Lf		0x4C66
+#define PCI_CHIP_RV250_Lg		0x4C67
+#define PCI_CHIP_RV250_Ln		0x4C6E
+#define PCI_CHIP_RAGE128MF		0x4D46
+#define PCI_CHIP_RAGE128ML		0x4D4C
+#define PCI_CHIP_R300_ND		0x4E44
+#define PCI_CHIP_R300_NE		0x4E45
+#define PCI_CHIP_R300_NF		0x4E46
+#define PCI_CHIP_R300_NG		0x4E47
+#define PCI_CHIP_R350_NH                0x4E48  
+#define PCI_CHIP_R350_NI                0x4E49  
+#define PCI_CHIP_R360_NJ                0x4E4A  
+#define PCI_CHIP_R350_NK                0x4E4B  
+#define PCI_CHIP_RV350_NP               0x4E50
+#define PCI_CHIP_RV350_NQ               0x4E51
+#define PCI_CHIP_RV350_NR               0x4E52
+#define PCI_CHIP_RV350_NS               0x4E53
+#define PCI_CHIP_RV350_NT               0x4E54
+#define PCI_CHIP_RV350_NV               0x4E56
+#define PCI_CHIP_RAGE128PA		0x5041
+#define PCI_CHIP_RAGE128PB		0x5042
+#define PCI_CHIP_RAGE128PC		0x5043
+#define PCI_CHIP_RAGE128PD		0x5044
+#define PCI_CHIP_RAGE128PE		0x5045
+#define PCI_CHIP_RAGE128PF		0x5046
+#define PCI_CHIP_RAGE128PG		0x5047
+#define PCI_CHIP_RAGE128PH		0x5048
+#define PCI_CHIP_RAGE128PI		0x5049
+#define PCI_CHIP_RAGE128PJ		0x504A
+#define PCI_CHIP_RAGE128PK		0x504B
+#define PCI_CHIP_RAGE128PL		0x504C
+#define PCI_CHIP_RAGE128PM		0x504D
+#define PCI_CHIP_RAGE128PN		0x504E
+#define PCI_CHIP_RAGE128PO		0x504F
+#define PCI_CHIP_RAGE128PP		0x5050
+#define PCI_CHIP_RAGE128PQ		0x5051
+#define PCI_CHIP_RAGE128PR		0x5052
+#define PCI_CHIP_RAGE128PS		0x5053
+#define PCI_CHIP_RAGE128PT		0x5054
+#define PCI_CHIP_RAGE128PU		0x5055
+#define PCI_CHIP_RAGE128PV		0x5056
+#define PCI_CHIP_RAGE128PW		0x5057
+#define PCI_CHIP_RAGE128PX		0x5058
+#define PCI_CHIP_RADEON_QD		0x5144
+#define PCI_CHIP_RADEON_QE		0x5145
+#define PCI_CHIP_RADEON_QF		0x5146
+#define PCI_CHIP_RADEON_QG		0x5147
+#define PCI_CHIP_R200_QH		0x5148
+#define PCI_CHIP_R200_QI		0x5149
+#define PCI_CHIP_R200_QJ		0x514A
+#define PCI_CHIP_R200_QK		0x514B
+#define PCI_CHIP_R200_QL		0x514C
+#define PCI_CHIP_R200_QM		0x514D
+#define PCI_CHIP_R200_QN		0x514E
+#define PCI_CHIP_R200_QO		0x514F
+#define PCI_CHIP_RV200_QW		0x5157
+#define PCI_CHIP_RV200_QX		0x5158
+#define PCI_CHIP_RV100_QY		0x5159
+#define PCI_CHIP_RV100_QZ		0x515A
+#define PCI_CHIP_RAGE128RE		0x5245
+#define PCI_CHIP_RAGE128RF		0x5246
+#define PCI_CHIP_RAGE128RG		0x5247
+#define PCI_CHIP_RAGE128RK		0x524B
+#define PCI_CHIP_RAGE128RL		0x524C
+#define PCI_CHIP_RAGE128SE		0x5345
+#define PCI_CHIP_RAGE128SF		0x5346
+#define PCI_CHIP_RAGE128SG		0x5347
+#define PCI_CHIP_RAGE128SH		0x5348
+#define PCI_CHIP_RAGE128SK		0x534B
+#define PCI_CHIP_RAGE128SL		0x534C
+#define PCI_CHIP_RAGE128SM		0x534D
+#define PCI_CHIP_RAGE128SN		0x534E
+#define PCI_CHIP_RAGE128TF		0x5446
+#define PCI_CHIP_RAGE128TL		0x544C
+#define PCI_CHIP_RAGE128TR		0x5452
+#define PCI_CHIP_RAGE128TS		0x5453
+#define PCI_CHIP_RAGE128TT		0x5454
+#define PCI_CHIP_RAGE128TU		0x5455
+#define PCI_CHIP_RV370_5460             0x5460
+#define PCI_CHIP_RV370_5461             0x5461
+#define PCI_CHIP_RV370_5462             0x5462
+#define PCI_CHIP_RV370_5463             0x5463
+#define PCI_CHIP_RV370_5464             0x5464
+#define PCI_CHIP_RV370_5465             0x5465
+#define PCI_CHIP_RV370_5466             0x5466
+#define PCI_CHIP_RV370_5467             0x5467
+#define PCI_CHIP_R423_UH                0x5548
+#define PCI_CHIP_R423_UI                0x5549
+#define PCI_CHIP_R423_UJ                0x554A
+#define PCI_CHIP_R423_UK                0x554B
+#define PCI_CHIP_R423_UQ                0x5551
+#define PCI_CHIP_R423_UR                0x5552
+#define PCI_CHIP_R423_UT                0x5554
+#define PCI_CHIP_MACH64VT		0x5654
+#define PCI_CHIP_MACH64VU		0x5655
+#define PCI_CHIP_MACH64VV		0x5656
+#define PCI_CHIP_RS300_5834		0x5834
+#define PCI_CHIP_RS300_5835		0x5835
+#define PCI_CHIP_RS300_5836		0x5836
+#define PCI_CHIP_RS300_5837		0x5837
+#define PCI_CHIP_RV370_5B60             0x5B60
+#define PCI_CHIP_RV370_5B61             0x5B61
+#define PCI_CHIP_RV370_5B62             0x5B62
+#define PCI_CHIP_RV370_5B63             0x5B63
+#define PCI_CHIP_RV370_5B64             0x5B64
+#define PCI_CHIP_RV370_5B65             0x5B65
+#define PCI_CHIP_RV370_5B66             0x5B66
+#define PCI_CHIP_RV370_5B67             0x5B67
+#define PCI_CHIP_RV280_5960		0x5960
+#define PCI_CHIP_RV280_5961		0x5961
+#define PCI_CHIP_RV280_5962		0x5962
+#define PCI_CHIP_RV280_5964		0x5964
+#define PCI_CHIP_RV280_5C61		0x5C61
+#define PCI_CHIP_RV280_5C63		0x5C63
+#define PCI_CHIP_R423_5D57              0x5D57
+#define PCI_CHIP_RS350_7834             0x7834
+#define PCI_CHIP_RS350_7835             0x7835
+
--- a/include/edid.h
+++ b/include/edid.h
@@ -0,0 +1,138 @@
+/* 
+ * edid.h - EDID/DDC Header
+ *
+ * Based on:
+ *   1. XFree86 4.3.0, edid.h
+ *      Copyright 1998 by Egbert Eich <Egbert.Eich@Physik.TU-Darmstadt.DE>
+ * 
+ *   2. John Fremlin <vii@users.sourceforge.net> and 
+ *      Ani Joshi <ajoshi@unixbox.com>
+ *
+ * DDC is a Trademark of VESA (Video Electronics Standard Association).
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file COPYING in the main directory of this archive
+ * for more details.
+*/
+
+#ifndef __EDID_H__
+#define __EDID_H__
+
+#define EDID_LENGTH				0x80
+#define EDID_HEADER				0x00
+#define EDID_HEADER_END				0x07
+
+#define ID_MANUFACTURER_NAME			0x08
+#define ID_MANUFACTURER_NAME_END		0x09
+#define ID_MODEL				0x0a
+
+#define ID_SERIAL_NUMBER			0x0c
+
+#define MANUFACTURE_WEEK			0x10
+#define MANUFACTURE_YEAR			0x11
+
+#define EDID_STRUCT_VERSION			0x12
+#define EDID_STRUCT_REVISION			0x13
+
+#define EDID_STRUCT_DISPLAY                     0x14
+
+#define DPMS_FLAGS				0x18
+#define ESTABLISHED_TIMING_1			0x23
+#define ESTABLISHED_TIMING_2			0x24
+#define MANUFACTURERS_TIMINGS			0x25
+
+/* standard timings supported */
+#define STD_TIMING                              8
+#define STD_TIMING_DESCRIPTION_SIZE             2
+#define STD_TIMING_DESCRIPTIONS_START           0x26
+
+#define DETAILED_TIMING_DESCRIPTIONS_START	0x36
+#define DETAILED_TIMING_DESCRIPTION_SIZE	18
+#define NO_DETAILED_TIMING_DESCRIPTIONS		4
+
+#define DETAILED_TIMING_DESCRIPTION_1		0x36
+#define DETAILED_TIMING_DESCRIPTION_2		0x48
+#define DETAILED_TIMING_DESCRIPTION_3		0x5a
+#define DETAILED_TIMING_DESCRIPTION_4		0x6c
+
+#define DESCRIPTOR_DATA				5
+
+#define UPPER_NIBBLE( x ) \
+        (((128|64|32|16) & (x)) >> 4)
+
+#define LOWER_NIBBLE( x ) \
+        ((1|2|4|8) & (x))
+
+#define COMBINE_HI_8LO( hi, lo ) \
+        ( (((unsigned)hi) << 8) | (unsigned)lo )
+
+#define COMBINE_HI_4LO( hi, lo ) \
+        ( (((unsigned)hi) << 4) | (unsigned)lo )
+
+#define PIXEL_CLOCK_LO     (unsigned)block[ 0 ]
+#define PIXEL_CLOCK_HI     (unsigned)block[ 1 ]
+#define PIXEL_CLOCK	   (COMBINE_HI_8LO( PIXEL_CLOCK_HI,PIXEL_CLOCK_LO )*10000)
+#define H_ACTIVE_LO        (unsigned)block[ 2 ]
+#define H_BLANKING_LO      (unsigned)block[ 3 ]
+#define H_ACTIVE_HI        UPPER_NIBBLE( (unsigned)block[ 4 ] )
+#define H_ACTIVE           COMBINE_HI_8LO( H_ACTIVE_HI, H_ACTIVE_LO )
+#define H_BLANKING_HI      LOWER_NIBBLE( (unsigned)block[ 4 ] )
+#define H_BLANKING         COMBINE_HI_8LO( H_BLANKING_HI, H_BLANKING_LO )
+
+#define V_ACTIVE_LO        (unsigned)block[ 5 ]
+#define V_BLANKING_LO      (unsigned)block[ 6 ]
+#define V_ACTIVE_HI        UPPER_NIBBLE( (unsigned)block[ 7 ] )
+#define V_ACTIVE           COMBINE_HI_8LO( V_ACTIVE_HI, V_ACTIVE_LO )
+#define V_BLANKING_HI      LOWER_NIBBLE( (unsigned)block[ 7 ] )
+#define V_BLANKING         COMBINE_HI_8LO( V_BLANKING_HI, V_BLANKING_LO )
+
+#define H_SYNC_OFFSET_LO   (unsigned)block[ 8 ]
+#define H_SYNC_WIDTH_LO    (unsigned)block[ 9 ]
+
+#define V_SYNC_OFFSET_LO   UPPER_NIBBLE( (unsigned)block[ 10 ] )
+#define V_SYNC_WIDTH_LO    LOWER_NIBBLE( (unsigned)block[ 10 ] )
+
+#define V_SYNC_WIDTH_HI    ((unsigned)block[ 11 ] & (1|2))
+#define V_SYNC_OFFSET_HI   (((unsigned)block[ 11 ] & (4|8)) >> 2)
+
+#define H_SYNC_WIDTH_HI    (((unsigned)block[ 11 ] & (16|32)) >> 4)
+#define H_SYNC_OFFSET_HI   (((unsigned)block[ 11 ] & (64|128)) >> 6)
+
+#define V_SYNC_WIDTH       COMBINE_HI_4LO( V_SYNC_WIDTH_HI, V_SYNC_WIDTH_LO )
+#define V_SYNC_OFFSET      COMBINE_HI_4LO( V_SYNC_OFFSET_HI, V_SYNC_OFFSET_LO )
+
+#define H_SYNC_WIDTH       COMBINE_HI_4LO( H_SYNC_WIDTH_HI, H_SYNC_WIDTH_LO )
+#define H_SYNC_OFFSET      COMBINE_HI_4LO( H_SYNC_OFFSET_HI, H_SYNC_OFFSET_LO )
+
+#define H_SIZE_LO          (unsigned)block[ 12 ]
+#define V_SIZE_LO          (unsigned)block[ 13 ]
+
+#define H_SIZE_HI          UPPER_NIBBLE( (unsigned)block[ 14 ] )
+#define V_SIZE_HI          LOWER_NIBBLE( (unsigned)block[ 14 ] )
+
+#define H_SIZE             COMBINE_HI_8LO( H_SIZE_HI, H_SIZE_LO )
+#define V_SIZE             COMBINE_HI_8LO( V_SIZE_HI, V_SIZE_LO )
+
+#define H_BORDER           (unsigned)block[ 15 ]
+#define V_BORDER           (unsigned)block[ 16 ]
+
+#define FLAGS              (unsigned)block[ 17 ]
+
+#define INTERLACED         (FLAGS&128)
+#define SYNC_TYPE          (FLAGS&3<<3)	/* bits 4,3 */
+#define SYNC_SEPARATE      (3<<3)
+#define HSYNC_POSITIVE     (FLAGS & 4)
+#define VSYNC_POSITIVE     (FLAGS & 2)
+
+#define V_MIN_RATE              block[ 5 ]
+#define V_MAX_RATE              block[ 6 ]
+#define H_MIN_RATE              block[ 7 ]
+#define H_MAX_RATE              block[ 8 ]
+#define MAX_PIXEL_CLOCK         (((int)block[ 9 ]) * 10)
+#define GTF_SUPPORT		block[10]
+
+#define DPMS_ACTIVE_OFF		(1 << 5)
+#define DPMS_SUSPEND		(1 << 6)
+#define DPMS_STANDBY		(1 << 7)
+
+#endif /* __EDID_H__ */
--- a/include/fb.h
+++ b/include/fb.h
@@ -0,0 +1,600 @@
+#ifndef _FB_H
+#define _FB_H
+
+/* Definitions of frame buffers						*/
+
+#define FB_MAJOR		29
+#define FB_MAX			32	/* sufficient for now */
+
+/* ioctls
+   0x46 is 'F'								*/
+#define FBIOGET_VSCREENINFO	0x4600
+#define FBIOPUT_VSCREENINFO	0x4601
+#define FBIOGET_FSCREENINFO	0x4602
+#define FBIOPAN_DISPLAY     0x4606
+#define FBIOBLANK		        0x4611		/* arg: 0 or vesa level + 1 */
+#define FBIO_ALLOC          0x4613
+#define FBIO_FREE           0x4614
+
+/* picture format */
+#define PICT_FORMAT(bpp,type,a,r,g,b)	(((bpp) << 24) | ((type) << 16) | ((a) << 12) | ((r) << 8) | ((g) << 4) | ((b)))
+/* gray/color formats use a visual index instead of argb */
+#define PICT_VISFORMAT(bpp,type,vi)	(((bpp) << 24) | ((type) << 16) | ((vi)))
+#define PICT_FORMAT_BPP(f)	(((f) >> 24)       )
+#define PICT_FORMAT_TYPE(f)	(((f) >> 16) & 0xff)
+#define PICT_FORMAT_A(f)	(((f) >> 12) & 0x0f)
+#define PICT_FORMAT_R(f)	(((f) >>  8) & 0x0f)
+#define PICT_FORMAT_G(f)	(((f) >>  4) & 0x0f)
+#define PICT_FORMAT_B(f)	(((f)      ) & 0x0f)
+#define PICT_FORMAT_RGB(f)	(((f)      ) & 0xfff)
+#define PICT_FORMAT_VIS(f)	(((f)      ) & 0xffff)
+#define PICT_TYPE_OTHER	0
+#define PICT_TYPE_A	1
+#define PICT_TYPE_ARGB	2
+#define PICT_TYPE_ABGR	3
+#define PICT_TYPE_COLOR	4
+#define PICT_TYPE_GRAY	5
+#define PICT_FORMAT_COLOR(f)	(PICT_FORMAT_TYPE(f) & 2)
+/* 32bpp formats */
+#define PICT_a8r8g8b8	PICT_FORMAT(32,PICT_TYPE_ARGB,8,8,8,8)
+#define PICT_x8r8g8b8	PICT_FORMAT(32,PICT_TYPE_ARGB,0,8,8,8)
+#define PICT_a8b8g8r8	PICT_FORMAT(32,PICT_TYPE_ABGR,8,8,8,8)
+#define PICT_x8b8g8r8	PICT_FORMAT(32,PICT_TYPE_ABGR,0,8,8,8)
+/* 24bpp formats */
+#define PICT_r8g8b8	PICT_FORMAT(24,PICT_TYPE_ARGB,0,8,8,8)
+#define PICT_b8g8r8	PICT_FORMAT(24,PICT_TYPE_ABGR,0,8,8,8)
+/* 16bpp formats */
+#define PICT_r5g6b5	PICT_FORMAT(16,PICT_TYPE_ARGB,0,5,6,5)
+#define PICT_b5g6r5	PICT_FORMAT(16,PICT_TYPE_ABGR,0,5,6,5)
+#define PICT_a1r5g5b5	PICT_FORMAT(16,PICT_TYPE_ARGB,1,5,5,5)
+#define PICT_x1r5g5b5	PICT_FORMAT(16,PICT_TYPE_ARGB,0,5,5,5)
+#define PICT_a1b5g5r5	PICT_FORMAT(16,PICT_TYPE_ABGR,1,5,5,5)
+#define PICT_x1b5g5r5	PICT_FORMAT(16,PICT_TYPE_ABGR,0,5,5,5)
+#define PICT_a4r4g4b4	PICT_FORMAT(16,PICT_TYPE_ARGB,4,4,4,4)
+#define PICT_x4r4g4b4	PICT_FORMAT(16,PICT_TYPE_ARGB,4,4,4,4)
+#define PICT_a4b4g4r4	PICT_FORMAT(16,PICT_TYPE_ARGB,4,4,4,4)
+#define PICT_x4b4g4r4	PICT_FORMAT(16,PICT_TYPE_ARGB,4,4,4,4)
+/* 8bpp formats */
+#define PICT_a8 PICT_FORMAT(8,PICT_TYPE_A,8,0,0,0)
+#define PICT_r3g3b2	PICT_FORMAT(8,PICT_TYPE_ARGB,0,3,3,2)
+#define PICT_b2g3r3	PICT_FORMAT(8,PICT_TYPE_ABGR,0,3,3,2)
+#define PICT_a2r2g2b2 PICT_FORMAT(8,PICT_TYPE_ARGB,2,2,2,2)
+#define PICT_a2b2g2r2 PICT_FORMAT(8,PICT_TYPE_ABGR,2,2,2,2)
+#define PICT_c8 PICT_FORMAT(8,PICT_TYPE_COLOR,0,0,0,0)
+#define PICT_g8 PICT_FORMAT(8,PICT_TYPE_GRAY,0,0,0,0)
+
+/* fVDI */
+#define MODE_EMUL_MONO_FLAG 1
+#define MODE_VESA_FLAG 2 /* for modedb.c */
+struct mode_option {
+	short used; /* Whether the mode option was used or not. */
+	short width;
+	short height;
+	short bpp;
+	short freq;
+	short flags;
+};
+
+extern struct mode_option resolution; /* fVDI */
+
+#define FB_TYPE_PACKED_PIXELS		0	/* Packed Pixels	*/
+#define FB_TYPE_PLANES			1	/* Non interleaved planes */
+#define FB_TYPE_INTERLEAVED_PLANES	2	/* Interleaved planes	*/
+#define FB_TYPE_TEXT			3	/* Text/attributes	*/
+#define FB_TYPE_VGA_PLANES		4	/* EGA/VGA planes	*/
+
+#define FB_AUX_TEXT_MDA		0	/* Monochrome text */
+#define FB_AUX_TEXT_CGA		1	/* CGA/EGA/VGA Color text */
+#define FB_AUX_TEXT_S3_MMIO	2	/* S3 MMIO fasttext */
+#define FB_AUX_TEXT_MGA_STEP16	3	/* MGA Millenium I: text, attr, 14 reserved bytes */
+#define FB_AUX_TEXT_MGA_STEP8	4	/* other MGAs:      text, attr,  6 reserved bytes */
+
+#define FB_AUX_VGA_PLANES_VGA4		0	/* 16 color planes (EGA/VGA) */
+#define FB_AUX_VGA_PLANES_CFB4		1	/* CFB4 in planes (VGA) */
+#define FB_AUX_VGA_PLANES_CFB8		2	/* CFB8 in planes (VGA) */
+
+#define FB_VISUAL_MONO01		0	/* Monochr. 1=Black 0=White */
+#define FB_VISUAL_MONO10		1	/* Monochr. 1=White 0=Black */
+#define FB_VISUAL_TRUECOLOR		2	/* True color	*/
+#define FB_VISUAL_PSEUDOCOLOR		3	/* Pseudo color (like atari) */
+#define FB_VISUAL_DIRECTCOLOR		4	/* Direct color */
+#define FB_VISUAL_STATIC_PSEUDOCOLOR	5	/* Pseudo color readonly */
+
+#define FB_ACCEL_NONE		0	/* no hardware accelerator	*/
+#define FB_ACCEL_ATARIBLITT	1	/* Atari Blitter		*/
+#define FB_ACCEL_AMIGABLITT	2	/* Amiga Blitter                */
+#define FB_ACCEL_S3_TRIO64	3	/* Cybervision64 (S3 Trio64)    */
+#define FB_ACCEL_NCR_77C32BLT	4	/* RetinaZ3 (NCR 77C32BLT)      */
+#define FB_ACCEL_S3_VIRGE	5	/* Cybervision64/3D (S3 ViRGE)	*/
+#define FB_ACCEL_ATI_MACH64GX	6	/* ATI Mach 64GX family		*/
+#define FB_ACCEL_DEC_TGA	7	/* DEC 21030 TGA		*/
+#define FB_ACCEL_ATI_MACH64CT	8	/* ATI Mach 64CT family		*/
+#define FB_ACCEL_ATI_MACH64VT	9	/* ATI Mach 64CT family VT class */
+#define FB_ACCEL_ATI_MACH64GT	10	/* ATI Mach 64CT family GT class */
+#define FB_ACCEL_SUN_CREATOR	11	/* Sun Creator/Creator3D	*/
+#define FB_ACCEL_SUN_CGSIX	12	/* Sun cg6			*/
+#define FB_ACCEL_SUN_LEO	13	/* Sun leo/zx			*/
+#define FB_ACCEL_IMS_TWINTURBO	14	/* IMS Twin Turbo		*/
+#define FB_ACCEL_3DLABS_PERMEDIA2 15	/* 3Dlabs Permedia 2		*/
+#define FB_ACCEL_MATROX_MGA2064W 16	/* Matrox MGA2064W (Millenium)	*/
+#define FB_ACCEL_MATROX_MGA1064SG 17	/* Matrox MGA1064SG (Mystique)	*/
+#define FB_ACCEL_MATROX_MGA2164W 18	/* Matrox MGA2164W (Millenium II) */
+#define FB_ACCEL_MATROX_MGA2164W_AGP 19	/* Matrox MGA2164W (Millenium II) */
+#define FB_ACCEL_MATROX_MGAG100	20	/* Matrox G100 (Productiva G100) */
+#define FB_ACCEL_MATROX_MGAG200	21	/* Matrox G200 (Myst, Mill, ...) */
+#define FB_ACCEL_SUN_CG14	22	/* Sun cgfourteen		 */
+#define FB_ACCEL_SUN_BWTWO	23	/* Sun bwtwo			*/
+#define FB_ACCEL_SUN_CGTHREE	24	/* Sun cgthree			*/
+#define FB_ACCEL_SUN_TCX	25	/* Sun tcx			*/
+#define FB_ACCEL_MATROX_MGAG400	26	/* Matrox G400			*/
+#define FB_ACCEL_NV3		27	/* nVidia RIVA 128              */
+#define FB_ACCEL_NV4		28	/* nVidia RIVA TNT		*/
+#define FB_ACCEL_NV5		29	/* nVidia RIVA TNT2		*/
+#define FB_ACCEL_CT_6555x	30	/* C&T 6555x			*/
+#define FB_ACCEL_3DFX_BANSHEE	31	/* 3Dfx Banshee			*/
+#define FB_ACCEL_ATI_RAGE128	32	/* ATI Rage128 family		*/
+#define FB_ACCEL_IGS_CYBER2000	33	/* CyberPro 2000		*/
+#define FB_ACCEL_IGS_CYBER2010	34	/* CyberPro 2010		*/
+#define FB_ACCEL_IGS_CYBER5000	35	/* CyberPro 5000		*/
+#define FB_ACCEL_SIS_GLAMOUR    36	/* SiS 300/630/540              */
+#define FB_ACCEL_3DLABS_PERMEDIA3 37	/* 3Dlabs Permedia 3		*/
+#define FB_ACCEL_ATI_RADEON	38	/* ATI Radeon family		*/
+#define FB_ACCEL_I810           39      /* Intel 810/815                */
+#define FB_ACCEL_SIS_GLAMOUR_2  40	/* SiS 315, 650, 740		*/
+#define FB_ACCEL_SIS_XABRE      41	/* SiS 330 ("Xabre")		*/
+#define FB_ACCEL_I830           42      /* Intel 830M/845G/85x/865G     */
+#define FB_ACCEL_NV_10          43      /* nVidia Arch 10               */
+#define FB_ACCEL_NV_20          44      /* nVidia Arch 20               */
+#define FB_ACCEL_NV_30          45      /* nVidia Arch 30               */
+#define FB_ACCEL_NV_40          46      /* nVidia Arch 40               */
+#define FB_ACCEL_NEOMAGIC_NM2070 90	/* NeoMagic NM2070              */
+#define FB_ACCEL_NEOMAGIC_NM2090 91	/* NeoMagic NM2090              */
+#define FB_ACCEL_NEOMAGIC_NM2093 92	/* NeoMagic NM2093              */
+#define FB_ACCEL_NEOMAGIC_NM2097 93	/* NeoMagic NM2097              */
+#define FB_ACCEL_NEOMAGIC_NM2160 94	/* NeoMagic NM2160              */
+#define FB_ACCEL_NEOMAGIC_NM2200 95	/* NeoMagic NM2200              */
+#define FB_ACCEL_NEOMAGIC_NM2230 96	/* NeoMagic NM2230              */
+#define FB_ACCEL_NEOMAGIC_NM2360 97	/* NeoMagic NM2360              */
+#define FB_ACCEL_NEOMAGIC_NM2380 98	/* NeoMagic NM2380              */
+
+#define FB_ACCEL_SAVAGE4        0x80	/* S3 Savage4                   */
+#define FB_ACCEL_SAVAGE3D       0x81	/* S3 Savage3D                  */
+#define FB_ACCEL_SAVAGE3D_MV    0x82	/* S3 Savage3D-MV               */
+#define FB_ACCEL_SAVAGE2000     0x83	/* S3 Savage2000                */
+#define FB_ACCEL_SAVAGE_MX_MV   0x84	/* S3 Savage/MX-MV              */
+#define FB_ACCEL_SAVAGE_MX      0x85	/* S3 Savage/MX                 */
+#define FB_ACCEL_SAVAGE_IX_MV   0x86	/* S3 Savage/IX-MV              */
+#define FB_ACCEL_SAVAGE_IX      0x87	/* S3 Savage/IX                 */
+#define FB_ACCEL_PROSAVAGE_PM   0x88	/* S3 ProSavage PM133           */
+#define FB_ACCEL_PROSAVAGE_KM   0x89	/* S3 ProSavage KM133           */
+#define FB_ACCEL_S3TWISTER_P    0x8a	/* S3 Twister                   */
+#define FB_ACCEL_S3TWISTER_K    0x8b	/* S3 TwisterK                  */
+#define FB_ACCEL_SUPERSAVAGE    0x8c    /* S3 Supersavage               */
+#define FB_ACCEL_PROSAVAGE_DDR  0x8d	/* S3 ProSavage DDR             */
+#define FB_ACCEL_PROSAVAGE_DDRK 0x8e	/* S3 ProSavage DDR-K           */
+
+struct fb_fix_screeninfo {
+	char id[16];			/* identification string eg "TT Builtin" */
+	unsigned long smem_start;	/* Start of frame buffer mem */
+					/* (physical address) */
+	unsigned long smem_len;			/* Length of frame buffer mem */
+	unsigned long type;			/* see FB_TYPE_*		*/
+	unsigned long type_aux;			/* Interleave for interleaved Planes */
+	unsigned long visual;			/* see FB_VISUAL_*		*/ 
+	unsigned short xpanstep;			/* zero if no hardware panning  */
+	unsigned short ypanstep;			/* zero if no hardware panning  */
+	unsigned short ywrapstep;		/* zero if no hardware ywrap    */
+	unsigned long line_length;		/* length of a line in bytes    */
+	unsigned long mmio_start;	/* Start of Memory Mapped I/O   */
+					/* (physical address) */
+	unsigned long mmio_len;			/* Length of Memory Mapped I/O  */
+	unsigned long accel;			/* Indicate to driver which	*/
+					/*  specific chip/card we have	*/
+	unsigned short reserved[3];		/* Reserved for future compatibility */
+};
+
+/* Interpretation of offset for color fields: All offsets are from the right,
+ * inside a "pixel" value, which is exactly 'bits_per_pixel' wide (means: you
+ * can use the offset as right argument to <<). A pixel afterwards is a bit
+ * stream and is written to video memory as that unmodified. This implies
+ * big-endian byte order if bits_per_pixel is greater than 8.
+ */
+struct fb_bitfield {
+	unsigned long offset;			/* beginning of bitfield	*/
+	unsigned long length;			/* length of bitfield		*/
+	unsigned long msb_right;		/* != 0 : Most significant bit is */ 
+					/* right */ 
+};
+
+#define FB_NONSTD_HAM		1	/* Hold-And-Modify (HAM)        */
+
+#define FB_ACTIVATE_NOW		0	/* set values immediately (or vbl)*/
+#define FB_ACTIVATE_NXTOPEN	1	/* activate on next open	*/
+#define FB_ACTIVATE_TEST	2	/* don't set, round up impossible */
+#define FB_ACTIVATE_MASK       15
+					/* values			*/
+#define FB_ACTIVATE_VBL	       16	/* activate values on next vbl  */
+#define FB_CHANGE_CMAP_VBL     32	/* change colormap on vbl	*/
+#define FB_ACTIVATE_ALL	       64	/* change all VCs on this fb	*/
+#define FB_ACTIVATE_FORCE     128	/* force apply even when no change*/
+#define FB_ACTIVATE_INV_MODE  256 /* invalidate videomode */
+
+#define FB_ACCELF_TEXT		1	/* (OBSOLETE) see fb_info.flags and vc_mode */
+
+#define FB_SYNC_HOR_HIGH_ACT	1	/* horizontal sync high active	*/
+#define FB_SYNC_VERT_HIGH_ACT	2	/* vertical sync high active	*/
+#define FB_SYNC_EXT		4	/* external sync		*/
+#define FB_SYNC_COMP_HIGH_ACT	8	/* composite sync high active   */
+#define FB_SYNC_BROADCAST	16	/* broadcast video timings      */
+					/* vtotal = 144d/288n/576i => PAL  */
+					/* vtotal = 121d/242n/484i => NTSC */
+#define FB_SYNC_ON_GREEN	32	/* sync on green */
+
+#define FB_VMODE_NONINTERLACED  0	/* non interlaced */
+#define FB_VMODE_INTERLACED	1	/* interlaced	*/
+#define FB_VMODE_DOUBLE		2	/* double scan */
+#define FB_VMODE_MASK		255
+
+#define FB_VMODE_YWRAP		256	/* ywrap instead of panning     */
+#define FB_VMODE_SMOOTH_XPAN	512	/* smooth xpan possible (internally used) */
+#define FB_VMODE_CONUPDATE	512	/* don't update x/yoffset	*/
+
+#define PICOS2KHZ(a) (1000000000UL/(a))
+#define KHZ2PICOS(a) (1000000000UL/(a))
+
+struct fb_var_screeninfo {
+	unsigned long xres;			/* visible resolution		*/
+	unsigned long yres;
+	unsigned long xres_virtual;		/* virtual resolution		*/
+	unsigned long yres_virtual;
+	unsigned long xoffset;			/* offset from virtual to visible */
+	unsigned long yoffset;			/* resolution			*/
+
+	unsigned long bits_per_pixel;		/* guess what			*/
+	unsigned long grayscale;		/* != 0 Graylevels instead of colors */
+
+	struct fb_bitfield red;		/* bitfield in fb mem if true color, */
+	struct fb_bitfield green;	/* else only length is significant */
+	struct fb_bitfield blue;
+	struct fb_bitfield transp;	/* transparency			*/	
+
+	unsigned long nonstd;			/* != 0 Non standard pixel format */
+
+	unsigned long activate;			/* see FB_ACTIVATE_*		*/
+
+	unsigned long height;			/* height of picture in mm    */
+	unsigned long width;			/* width of picture in mm     */
+
+	unsigned long accel_flags;		/* (OBSOLETE) see fb_info.flags */
+
+	/* Timing: All values in pixclocks, except pixclock (of course) */
+	unsigned long pixclock;			/* pixel clock in ps (pico seconds) */
+	unsigned long left_margin;		/* time from sync to picture	*/
+	unsigned long right_margin;		/* time from picture to sync	*/
+	unsigned long upper_margin;		/* time from sync to picture	*/
+	unsigned long lower_margin;
+	unsigned long hsync_len;		/* length of horizontal sync	*/
+	unsigned long vsync_len;		/* length of vertical sync	*/
+	unsigned long sync;			/* see FB_SYNC_*		*/
+	unsigned long vmode;			/* see FB_VMODE_*		*/
+	unsigned long rotate;			/* angle we rotate counter clockwise */
+	unsigned long refresh;
+	unsigned long reserved[4];		/* Reserved for future compatibility */
+};
+
+/* VESA Blanking Levels */
+#define VESA_NO_BLANKING        0
+#define VESA_VSYNC_SUSPEND      1
+#define VESA_HSYNC_SUSPEND      2
+#define VESA_POWERDOWN          3
+
+enum {
+	/* screen: unblanked, hsync: on,  vsync: on */
+	FB_BLANK_UNBLANK       = VESA_NO_BLANKING,
+	/* screen: blanked,   hsync: on,  vsync: on */
+	FB_BLANK_NORMAL        = VESA_NO_BLANKING + 1,
+	/* screen: blanked,   hsync: on,  vsync: off */
+	FB_BLANK_VSYNC_SUSPEND = VESA_VSYNC_SUSPEND + 1,
+	/* screen: blanked,   hsync: off, vsync: on */
+	FB_BLANK_HSYNC_SUSPEND = VESA_HSYNC_SUSPEND + 1,
+	/* screen: blanked,   hsync: off, vsync: off */
+	FB_BLANK_POWERDOWN     = VESA_POWERDOWN + 1
+};
+
+#define FB_VBLANK_VBLANKING	0x001	/* currently in a vertical blank */
+#define FB_VBLANK_HBLANKING	0x002	/* currently in a horizontal blank */
+#define FB_VBLANK_HAVE_VBLANK	0x004	/* vertical blanks can be detected */
+#define FB_VBLANK_HAVE_HBLANK	0x008	/* horizontal blanks can be detected */
+#define FB_VBLANK_HAVE_COUNT	0x010	/* global retrace counter is available */
+#define FB_VBLANK_HAVE_VCOUNT	0x020	/* the vcount field is valid */
+#define FB_VBLANK_HAVE_HCOUNT	0x040	/* the hcount field is valid */
+#define FB_VBLANK_VSYNCING	0x080	/* currently in a vsync */
+#define FB_VBLANK_HAVE_VSYNC	0x100	/* verical syncs can be detected */
+
+struct fb_vblank {
+	unsigned long flags;			/* FB_VBLANK flags */
+	unsigned long count;			/* counter of retraces since boot */
+	unsigned long vcount;			/* current scanline position */
+	unsigned long hcount;			/* current scandot position */
+	unsigned long reserved[4];		/* reserved for future compatibility */
+};
+
+struct vm_area_struct;
+struct fb_info;
+struct device;
+struct file;
+
+/* Definitions below are used in the parsed monitor specs */
+#define FB_DPMS_ACTIVE_OFF	1
+#define FB_DPMS_SUSPEND		2
+#define FB_DPMS_STANDBY		4
+
+#define FB_DISP_DDI		1
+#define FB_DISP_ANA_700_300	2
+#define FB_DISP_ANA_714_286	4
+#define FB_DISP_ANA_1000_400	8
+#define FB_DISP_ANA_700_000	16
+
+#define FB_DISP_MONO		32
+#define FB_DISP_RGB		64
+#define FB_DISP_MULTI		128
+#define FB_DISP_UNKNOWN		256
+
+#define FB_SIGNAL_NONE		0
+#define FB_SIGNAL_BLANK_BLANK	1
+#define FB_SIGNAL_SEPARATE	2
+#define FB_SIGNAL_COMPOSITE	4
+#define FB_SIGNAL_SYNC_ON_GREEN	8
+#define FB_SIGNAL_SERRATION_ON	16
+
+#define FB_MISC_PRIM_COLOR	1
+#define FB_MISC_1ST_DETAIL	2	/* First Detailed Timing is preferred */
+struct fb_chroma {
+	unsigned long redx;	/* in fraction of 1024 */
+	unsigned long greenx;
+	unsigned long bluex;
+	unsigned long whitex;
+	unsigned long redy;
+	unsigned long greeny;
+	unsigned long bluey;
+	unsigned long whitey;
+};
+
+struct fb_monspecs {
+	struct fb_chroma chroma;
+	struct fb_videomode *modedb;	/* mode database */
+	unsigned char  manufacturer[4];		/* Manufacturer */
+	unsigned char  monitor[14];		/* Monitor String */
+	unsigned char  serial_no[14];		/* Serial Number */
+	unsigned char  ascii[14];		/* ? */
+	unsigned long modedb_len;		/* mode database length */
+	unsigned long model;			/* Monitor Model */
+	unsigned long serial;			/* Serial Number - Integer */
+	unsigned long year;			/* Year manufactured */
+	unsigned long week;			/* Week Manufactured */
+	unsigned long hfmin;			/* hfreq lower limit (Hz) */
+	unsigned long hfmax;			/* hfreq upper limit (Hz) */
+	unsigned long dclkmin;			/* pixelclock lower limit (Hz) */
+	unsigned long dclkmax;			/* pixelclock upper limit (Hz) */
+	unsigned short input;			/* display type - see FB_DISP_* */
+	unsigned short dpms;			/* DPMS support - see FB_DPMS_ */
+	unsigned short signal;			/* Signal Type - see FB_SIGNAL_* */
+	unsigned short vfmin;			/* vfreq lower limit (Hz) */
+	unsigned short vfmax;			/* vfreq upper limit (Hz) */
+	unsigned short gamma;			/* Gamma - in fractions of 100 */
+	unsigned short gtf	: 1;		/* supports GTF */
+	unsigned short misc;			/* Misc flags - see FB_MISC_* */
+	unsigned char  version;			/* EDID version... */
+	unsigned char  revision;			/* ...and revision */
+	unsigned char  max_x;			/* Maximum horizontal size (cm) */
+	unsigned char  max_y;			/* Maximum vertical size (cm) */
+};
+
+struct fb_ops {
+	/* checks var and eventually tweaks if to soomething supported,
+	 * DO NOT MODIFY PAR  */
+	int (*fb_check_var)(struct fb_var_screeninfo *var, struct fb_info *info);
+	/* set the video mode according to info->var */
+	int (*fb_set_par)(struct fb_info *info);
+	/* set color register */
+	int (*fb_setcolreg)(unsigned regno, unsigned red, unsigned green,
+	                    unsigned blue, unsigned transp, struct fb_info *info);
+	/* pan display */
+	int (*fb_pan_display)(struct fb_var_screeninfo *var, struct fb_info *info);
+	/* blank display */
+	int (*fb_blank)(int blank, struct fb_info *info);
+	/* wait for blit idle */
+	int (*fb_sync)(struct fb_info *info);
+	/* perform fb specific ioctl */
+	int (*fb_ioctl)(unsigned int cmd, unsigned long arg, struct fb_info *info);
+	/* Buildthe modedb for head 1 (head 2 will come later), check panel infos
+	 * from either BIOS or EDID, and pick up the default mode */
+	void (*fb_check_modes)(struct fb_info *info, struct mode_option *resolution);
+  /* Accel functions */
+#define DEGREES_0	0
+#define DEGREES_90	1
+#define DEGREES_180	2
+#define DEGREES_270	3
+#define OMIT_LAST	1
+	void (*SetupForSolidFill)(struct fb_info *info, int color, int rop, unsigned int planemask);
+	void (*SubsequentSolidFillRect)(struct fb_info *info, int x, int y, int w, int h);
+	void (*SetupForSolidLine)(struct fb_info *info, int color, int rop, unsigned int planemask);
+	void (*SubsequentSolidHorVertLine)(struct fb_info *info, int x, int y, int len, int dir);   
+	void (*SubsequentSolidTwoPointLine)(struct fb_info *info, int xa, int ya, int xb, int yb, int flags);  
+	void (*SetupForDashedLine)(struct fb_info *info, int fg, int bg, int rop, unsigned int planemask, int length, unsigned char *pattern);
+	void (*SubsequentDashedTwoPointLine)(struct fb_info *info, int xa, int ya, int xb, int yb, int flags, int phase);  
+	void (*SetupForScreenToScreenCopy)(struct fb_info *info, int xdir, int ydir, int rop, unsigned int planemask, int trans_color);
+	void (*SubsequentScreenToScreenCopy)(struct fb_info *info, int xa, int ya, int xb, int yb, int w, int h);   
+	void (*ScreenToScreenCopy)(struct fb_info *info, int xa, int ya, int xb, int yb, int w, int h, int rop);
+	void (*SetupForMono8x8PatternFill)(struct fb_info *info, int patternx, int patterny, int fg, int bg, int rop, unsigned int planemask);
+	void (*SubsequentMono8x8PatternFillRect)(struct fb_info *info, int patternx, int patterny, int x, int y, int w, int h);
+	void (*SetupForScanlineCPUToScreenColorExpandFill)(struct fb_info *info, int fg, int bg, int rop, unsigned int planemask);
+	void (*SubsequentScanlineCPUToScreenColorExpandFill)(struct fb_info *info, int x, int y, int w, int h, int skipleft);
+	void (*SubsequentScanline)(struct fb_info *info, unsigned long *buf);
+	void (*SetupForScanlineImageWrite)(struct fb_info *info, int rop, unsigned int planemask, int trans_color, int bpp);
+	void (*SubsequentScanlineImageWriteRect)(struct fb_info *info, int x, int y, int w, int h, int skipleft);  
+	void (*SetClippingRectangle)(struct fb_info *info, int xa, int ya, int xb, int yb);
+	void (*DisableClipping)(struct fb_info *info);
+	int (*SetupForCPUToScreenAlphaTexture)(struct fb_info *info, 
+      int op, unsigned short red, unsigned short green, unsigned short blue, unsigned short alpha, unsigned long maskFormat, unsigned long dstFormat, unsigned char *alphaPtr, int alphaPitch, int width, int height, int flags);
+	int (*SetupForCPUToScreenTexture)(struct fb_info *info, int op, unsigned long srcFormat, unsigned long dstFormat, unsigned char *texPtr, int texPitch, int width, int height, int flags);
+	void (*SubsequentCPUToScreenTexture)(struct fb_info *info, int dstx, int dsty, int srcx, int srcy, int width, int height);
+	/* Cursor functions */
+	void (*SetCursorColors)(struct fb_info *info, int bg, int fg);
+	void (*SetCursorPosition)(struct fb_info *info, int x, int y);
+	void (*LoadCursorImage)(struct fb_info *info, unsigned short *mask, unsigned short *data, int zoom);
+	void (*HideCursor)(struct fb_info *info);
+	void (*ShowCursor)(struct fb_info *info);
+	long (*CursorInit)(struct fb_info *info);
+	void (*WaitVbl)(struct fb_info *info);
+};
+
+struct fb_info {
+	struct fb_var_screeninfo var;	/* Current var */
+	struct fb_fix_screeninfo fix;	/* Current fix */
+	struct fb_monspecs monspecs;	/* Current Monitor specs */
+	struct fb_videomode *mode;	/* current mode */
+	char *screen_base;	/* Virtual address */
+	unsigned long screen_size;
+	char *ram_base;	        /* base vram */
+	unsigned long ram_size; /* vram size */
+	char *screen_mono;
+	long update_mono;
+	struct fb_ops *fbops;
+	void *par; /* device dependent */
+};
+
+/* fbmem.c */
+extern int fb_pan_display(struct fb_info *info, struct fb_var_screeninfo *var); 
+extern int fb_set_var(struct fb_info *info, struct fb_var_screeninfo *var); 
+extern int fb_blank(struct fb_info *info, int blank);
+extern int fb_ioctl(unsigned int cmd, unsigned long arg);
+extern struct fb_info *framebuffer_alloc(unsigned long size);
+extern void framebuffer_release(struct fb_info *info);
+
+/* offscreen.c */
+extern long offscreen_free(struct fb_info *info, long addr);
+extern long offscreen_alloc(struct fb_info *info, long amount);
+extern long offscren_reserved(void);
+extern void offscreen_init(struct fb_info *info);
+
+/* fbmon.c */
+#define FB_MAXTIMINGS		0
+#define FB_VSYNCTIMINGS		1
+#define FB_HSYNCTIMINGS		2
+#define FB_DCLKTIMINGS		3
+#define FB_IGNOREMON		0x100
+
+#define FB_MODE_IS_UNKNOWN	0
+#define FB_MODE_IS_DETAILED	1
+#define FB_MODE_IS_STANDARD	2
+#define FB_MODE_IS_VESA		4
+#define FB_MODE_IS_CALCULATED	8
+#define FB_MODE_IS_FIRST	16
+#define FB_MODE_IS_FROM_VAR     32
+
+extern void fb_destroy_modedb(struct fb_videomode *modedb);
+extern int fb_parse_edid(unsigned char *edid, struct fb_var_screeninfo *var);
+extern void fb_edid_to_monspecs(unsigned char *edid, struct fb_monspecs *specs);
+extern int fb_get_mode(int flags, unsigned long val, struct fb_var_screeninfo *var, struct fb_info *info);
+extern int fb_validate_mode(const struct fb_var_screeninfo *var, struct fb_info *info);
+
+/* modedb.c */
+#define VESA_MODEDB_SIZE 34
+extern int fb_find_mode(struct fb_var_screeninfo *var,
+           struct fb_info *info, struct mode_option *resolution ,
+           const struct fb_videomode *db, unsigned int dbsize,
+           const struct fb_videomode *default_mode, unsigned int default_bpp);
+extern void fb_var_to_videomode(struct fb_videomode *mode, struct fb_var_screeninfo *var);
+extern void fb_videomode_to_var(struct fb_var_screeninfo *var, struct fb_videomode *mode);
+extern int fb_mode_is_equal(struct fb_videomode *mode1, struct fb_videomode *mode2);
+
+struct fb_videomode {
+	unsigned short refresh;		/* optional */
+	unsigned short xres;
+	unsigned short yres;
+	unsigned long pixclock;
+	unsigned short left_margin;
+	unsigned short right_margin;
+	unsigned short upper_margin;
+	unsigned short lower_margin;
+	unsigned short hsync_len;
+	unsigned short vsync_len;
+	unsigned short sync;
+	unsigned short vmode;
+	unsigned short flag;
+};
+
+extern const struct fb_videomode vesa_modes[];
+
+/* timer */
+extern void udelay(long usec);
+#ifdef COLDFIRE
+#ifdef MCF5445X
+#define US_TO_TIMER(a) (a)
+#define TIMER_TO_US(a) (a)
+#else /* MCF548X */
+#define US_TO_TIMER(a) ((a)*100)
+#define TIMER_TO_US(a) ((a)/100)
+#endif
+#else
+#define US_TO_TIMER(a) (((a)*256)/5000)
+#define TIMER_TO_US(a) (((a)*5000)/256)
+#endif
+extern long get_timer(void);
+extern void start_timeout(void);
+extern int end_timeout(long msec);
+extern void mdelay(long msec);
+extern void install_vbl_timer(void *func, int remove);
+extern void uninstall_vbl_timer(void *func);
+
+/*
+ * fVDI access
+ */
+extern void Funcs_copymem(const void *s, void *d, long n);
+extern const char *Funcs_next_line(const char *ptr);
+extern const char *Funcs_skip_space(const char *ptr);
+extern const char *Funcs_get_token(const char *ptr, char *buf, long n);
+extern long Funcs_equal(const char *str1, const char *str2);
+extern long Funcs_length(const char *text);
+extern void Funcs_copy(const char *src, char *dest);
+extern void Funcs_cat(const char *src, char *dest);
+extern long Funcs_numeric(long ch);
+extern long Funcs_atol(const char *text);
+extern void Funcs_error(const char *text1, const char *text2);
+extern void *Funcs_malloc(long size, long type);
+extern long Funcs_free(void *addr);
+extern int Funcs_puts(const char *text);
+extern void Funcs_ltoa(char *buf, long n, unsigned long base);
+extern long Funcs_get_cookie(const unsigned char *cname, long super);
+extern long Funcs_set_cookie(const unsigned char *cname, long value);
+//extern long Funcs_fixup_font(Fontheader *font, char *buffer, long flip);
+//extern long Funcs_unpack_font(Fontheader *header, long format);
+//extern long Funcs_insert_font(Fontheader **first_font, Fontheader *new_font);
+extern long Funcs_get_size(const char *name);
+extern char *Funcs_allocate_block(long size);
+extern void Funcs_free_block(void *address);
+extern void Funcs_cache_flush(void);
+extern long Funcs_misc(long func, long par, const char *token);
+extern long Funcs_event(long id_type, long data); 
+
+extern struct fb_info *info_fvdi;
+
+/*
+ * Debugging stuffs
+ */
+extern short debug;
+extern void debug_print(const char *string);
+extern void debug_print_value(const char *string, long val);
+extern void debug_print_value_hex(const char *string, long val);
+extern void debug_print_value_hex_byte(const char *string, unsigned char val);
+extern void debug_print_value_hex_word(const char *string, unsigned short val);
+extern void debug_print_value_hex_long(const char *string, unsigned long val);
+#define DPRINT debug_print
+#define DPRINTVAL debug_print_value
+#define DPRINTVALHEX debug_print_value_hex
+#define DPRINTVALHEXBYTE debug_print_value_hex_byte
+#define DPRINTVALHEXWORD debug_print_value_hex_word
+#define DPRINTVALHEXLONG debug_print_value_hex_long
+
+#endif /* _FB_H */
--- a/include/i2c-algo-bit.h
+++ b/include/i2c-algo-bit.h
@@ -0,0 +1,54 @@
+/* ------------------------------------------------------------------------- */
+/* i2c-algo-bit.h i2c driver algorithms for bit-shift adapters               */
+/* ------------------------------------------------------------------------- */
+/*   Copyright (C) 1995-99 Simon G. Vogl
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.                */
+/* ------------------------------------------------------------------------- */
+
+/* With some changes from Ky<4B>sti M<>lkki <kmalkki@cc.hut.fi> and even
+   Frodo Looijaard <frodol@dds.nl> */
+
+/* $Id: i2c-algo-bit.h,v 1.1.1.1 2012/08/16 18:43:05 mfro Exp $ */
+
+#ifndef I2C_ALGO_BIT_H
+#define I2C_ALGO_BIT_H
+
+/* --- Defines for bit-adapters ---------------------------------------	*/
+/*
+ * This struct contains the hw-dependent functions of bit-style adapters to 
+ * manipulate the line states, and to init any hw-specific features. This is
+ * only used if you have more than one hw-type of adapter running. 
+ */
+struct i2c_algo_bit_data {
+	void *data;		/* private data for lowlevel routines */
+	void (*setsda) (void *data, int state);
+	void (*setscl) (void *data, int state);
+	int  (*getsda) (void *data);
+	int  (*getscl) (void *data);
+
+	/* local settings */
+	int udelay;		/* half-clock-cycle time in microsecs */
+				/* i.e. clock is (500 / udelay) KHz */
+	int mdelay;		/* in millisecs, unused */
+	int timeout;		/* in jiffies */
+};
+
+#define I2C_BIT_ADAP_MAX	16
+
+int i2c_bit_add_bus(struct i2c_adapter *);
+int i2c_bit_del_bus(struct i2c_adapter *);
+
+#endif /* I2C_ALGO_BIT_H */
--- a/include/i2c.h
+++ b/include/i2c.h
@@ -0,0 +1,82 @@
+/* ------------------------------------------------------------------------- */
+/*                                                                           */
+/* i2c.h - definitions for the i2c-bus interface                             */
+/*                                                                           */
+/* ------------------------------------------------------------------------- */
+/*   Copyright (C) 1995-2000 Simon G. Vogl
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.		     */
+/* ------------------------------------------------------------------------- */
+
+/* With some changes from Ky<4B>sti M<>lkki <kmalkki@cc.hut.fi> and
+   Frodo Looijaard <frodol@dds.nl> */
+
+/* $Id: i2c.h,v 1.1.1.1 2012/08/16 18:43:05 mfro Exp $ */
+
+#ifndef _I2C_H
+#define _I2C_H
+
+/* --- General options ------------------------------------------------	*/
+
+struct i2c_msg;
+struct i2c_algorithm;
+struct i2c_adapter;
+
+/* Transfer num messages.
+ */
+extern int i2c_transfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num);
+
+/*
+ * The following structs are for those who like to implement new bus drivers:
+ * i2c_algorithm is the interface to a class of hardware solutions which can
+ * be addressed using the same bus algorithms - i.e. bit-banging or the PCF8584
+ * to name two of the most common.
+ */
+struct i2c_algorithm {
+	unsigned int id;
+	int (*master_xfer)(struct i2c_adapter *adap,struct i2c_msg *msgs, int num);
+	/* --- ioctl like call to set div. parameters. */
+	int (*algo_control)(struct i2c_adapter *, unsigned int, unsigned long);
+};
+
+/*
+ * i2c_adapter is the structure used to identify a physical i2c bus along
+ * with the access algorithms necessary to access it.
+ */
+struct i2c_adapter {
+	struct i2c_algorithm *algo;/* the algorithm to access the bus	*/
+	void *algo_data;
+	int timeout;
+	int retries;
+	int nr;
+};
+
+/*
+ * I2C Message - used for pure i2c transaction, also from /dev interface
+ */
+struct i2c_msg {
+	unsigned short addr;	/* slave address			*/
+ 	unsigned short flags;		
+#define I2C_M_TEN	0x10	/* we have a ten bit chip address	*/
+#define I2C_M_RD	0x01
+#define I2C_M_NOSTART	0x4000
+#define I2C_M_REV_DIR_ADDR	0x2000
+#define I2C_M_IGNORE_NAK	0x1000
+#define I2C_M_NO_RD_ACK		0x0800
+ 	unsigned short len;		/* msg length				*/
+ 	unsigned char *buf;		/* pointer to msg data			*/
+};
+
+#endif /* _I2C_H */
--- a/include/radeon_reg.h
+++ b/include/radeon_reg.h
--- a/include/radeonfb.h
+++ b/include/radeonfb.h
@@ -0,0 +1,690 @@
+#ifndef __RADEONFB_H__
+#define __RADEONFB_H__
+
+//#include "config.h"
+#include <bas_string.h>
+#include "pci.h"
+#include "mod_devicetable.h"
+#include "pci_ids.h"
+#include "fb.h"
+#include "i2c.h"
+#include "i2c-algo-bit.h"
+//#include "radeon_theatre.h"
+#include "radeon_reg.h"
+
+#ifndef point32_ter
+#define point32_ter void*
+#endif
+#ifndef FALSE
+#define FALSE 0
+#endif
+#ifndef TRUE
+#define TRUE 1
+#endif
+
+/* Buffer are aligned on 4096 byte boundaries */
+#define RADEON_BUFFER_ALIGN           0x00000fff
+
+#define RADEON_IDLE_RETRY      16 /* Fall out of idle loops after this count */
+#define RADEON_TIMEOUT    2000000 /* Fall out of wait loops after this count */
+#define RADEON_MMIOSIZE   0x80000
+
+#define RADEON_ALIGN(x,bytes) (((x) + ((bytes) - 1)) & ~((bytes) - 1))
+  
+#define ATY_RADEON_LCD_ON	0x00000001
+#define ATY_RADEON_CRT_ON	0x00000002
+
+#define FBIO_RADEON_GET_MIRROR	0x80044003
+#define FBIO_RADEON_SET_MIRROR	0xC0044004
+
+/***************************************************************
+ * Most of the definitions here are adapted right from XFree86 *
+ ***************************************************************/
+
+/*
+ * Chip families. Must fit in the low 16 bits of a int32_t word
+ */
+enum radeon_family
+{
+	CHIP_FAMILY_UNKNOW,
+	CHIP_FAMILY_LEGACY,
+	CHIP_FAMILY_RADEON,
+	CHIP_FAMILY_RV100,
+	CHIP_FAMILY_RS100,    /* U1 (IGP320M) or A3 (IGP320)*/
+	CHIP_FAMILY_RV200,
+	CHIP_FAMILY_RS200,    /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350), RS250 (IGP 7000) */
+	CHIP_FAMILY_R200,
+	CHIP_FAMILY_RV250,
+	CHIP_FAMILY_RS300,    /* Radeon 9000 IGP */
+	CHIP_FAMILY_RV280,
+	CHIP_FAMILY_R300,
+	CHIP_FAMILY_R350,
+	CHIP_FAMILY_RV350,
+	CHIP_FAMILY_RV380,    /* RV370/RV380/M22/M24 */
+	CHIP_FAMILY_R420,     /* R420/R423/M18 */
+	CHIP_FAMILY_LAST,
+};
+
+#define IS_RV100_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_RV100)  || \
+				 ((rinfo)->family == CHIP_FAMILY_RV200)  || \
+				 ((rinfo)->family == CHIP_FAMILY_RS100)  || \
+				 ((rinfo)->family == CHIP_FAMILY_RS200)  || \
+				 ((rinfo)->family == CHIP_FAMILY_RV250)  || \
+				 ((rinfo)->family == CHIP_FAMILY_RV280)  || \
+				 ((rinfo)->family == CHIP_FAMILY_RS300))
+
+
+#define IS_R300_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_R300)  || \
+				((rinfo)->family == CHIP_FAMILY_RV350) || \
+				((rinfo)->family == CHIP_FAMILY_R350)  || \
+				((rinfo)->family == CHIP_FAMILY_RV380) || \
+				((rinfo)->family == CHIP_FAMILY_R420))
+
+/*
+ * Chip flags
+ */
+enum radeon_chip_flags
+{
+	CHIP_FAMILY_MASK	= 0x0000ffffUL,
+	CHIP_FLAGS_MASK		= 0xffff0000UL,
+	CHIP_IS_MOBILITY	= 0x00010000UL,
+	CHIP_IS_IGP		= 0x00020000UL,
+	CHIP_HAS_CRTC2		= 0x00040000UL,	
+};
+
+/*
+ * Errata workarounds
+ */
+enum radeon_errata
+{
+	CHIP_ERRATA_R300_CG		= 0x00000001,
+	CHIP_ERRATA_PLL_DUMMYREADS	= 0x00000002,
+	CHIP_ERRATA_PLL_DELAY		= 0x00000004,
+};
+
+
+/*
+ * Monitor types
+ */
+enum radeon_montype
+{
+	MT_NONE = 0,
+	MT_CRT,		/* CRT */
+	MT_LCD,		/* LCD */
+	MT_DFP,		/* DVI */
+	MT_CTV,		/* composite TV */
+	MT_STV		/* S-Video out */
+};
+
+/*
+ * DDC i2c ports
+ */
+enum ddc_type
+{
+	ddc_none,
+	ddc_monid,
+	ddc_dvi,
+	ddc_vga,
+	ddc_crt2,
+};
+
+/*
+ * Connector types
+ */
+enum conn_type
+{
+	conn_none,
+	conn_proprietary,
+	conn_crt,
+	conn_DVI_I,
+	conn_DVI_D,
+};
+
+
+/*
+ * PLL infos
+ */
+struct pll_info
+{
+	int32_t ppll_max;
+	int32_t ppll_min;
+	int32_t sclk, mclk;
+	int32_t ref_div;
+	int32_t ref_clk;
+};
+
+
+/*
+ * This structure contains the various registers manipulated by this
+ * driver for setting or restoring a mode. It's mostly copied from
+ * XFree's RADEONSaveRec structure. A few chip settings might still be
+ * tweaked without beeing reflected or saved in these registers though
+ */
+struct radeon_regs
+{
+	/* Common registers */
+	uint32_t		ovr_clr;
+	uint32_t		ovr_wid_left_right;
+	uint32_t		ovr_wid_top_bottom;
+	uint32_t		ov0_scale_cntl;
+	uint32_t		mpp_tb_config;
+	uint32_t		mpp_gp_config;
+	uint32_t		subpic_cntl;
+	uint32_t		viph_control;
+	uint32_t		i2c_cntl_1;
+	uint32_t		gen_int32_t_cntl;
+	uint32_t		cap0_trig_cntl;
+	uint32_t		cap1_trig_cntl;
+	uint32_t		bus_cntl;
+	uint32_t		surface_cntl;
+	uint32_t		bios_5_scratch;
+
+	/* Other registers to save for VT switches or driver load/unload */
+	uint32_t		dp_datatype;
+	uint32_t		rbbm_soft_reset;
+	uint32_t		clock_cntl_index;
+	uint32_t		amcgpio_en_reg;
+	uint32_t		amcgpio_mask;
+
+	/* Surface/tiling registers */
+	uint32_t		surf_lower_bound[8];
+	uint32_t		surf_upper_bound[8];
+	uint32_t		surf_info[8];
+
+	/* CRTC registers */
+	uint32_t		crtc_gen_cntl;
+	uint32_t		crtc_ext_cntl;
+	uint32_t		dac_cntl;
+	uint32_t		crtc_h_total_disp;
+	uint32_t		crtc_h_sync_strt_wid;
+	uint32_t		crtc_v_total_disp;
+	uint32_t		crtc_v_sync_strt_wid;
+	uint32_t		crtc_offset;
+	uint32_t		crtc_offset_cntl;
+	uint32_t		crtc_pitch;
+	uint32_t		disp_merge_cntl;
+	uint32_t		grph_buffer_cntl;
+	uint32_t		crtc_more_cntl;
+
+	/* CRTC2 registers */
+	uint32_t		crtc2_gen_cntl;
+	uint32_t		dac2_cntl;
+	uint32_t		disp_output_cntl;
+	uint32_t		disp_hw_debug;
+	uint32_t		disp2_merge_cntl;
+	uint32_t		grph2_buffer_cntl;
+	uint32_t		crtc2_h_total_disp;
+	uint32_t		crtc2_h_sync_strt_wid;
+	uint32_t		crtc2_v_total_disp;
+	uint32_t		crtc2_v_sync_strt_wid;
+	uint32_t		crtc2_offset;
+	uint32_t		crtc2_offset_cntl;
+	uint32_t		crtc2_pitch;
+
+	/* Flat panel regs */
+	uint32_t 	fp_crtc_h_total_disp;
+	uint32_t		fp_crtc_v_total_disp;
+	uint32_t		fp_gen_cntl;
+	uint32_t		fp2_gen_cntl;
+	uint32_t		fp_h_sync_strt_wid;
+	uint32_t		fp2_h_sync_strt_wid;
+	uint32_t		fp_horz_stretch;
+	uint32_t		fp_panel_cntl;
+	uint32_t		fp_v_sync_strt_wid;
+	uint32_t		fp2_v_sync_strt_wid;
+	uint32_t		fp_vert_stretch;
+	uint32_t		lvds_gen_cntl;
+	uint32_t		lvds_pll_cntl;
+	uint32_t		tmds_crc;
+	uint32_t		tmds_transmitter_cntl;
+
+	/* Computed values for PLL */
+	uint32_t		dot_clock_freq;
+	uint32_t		pll_output_freq;
+	int32_t		feedback_div;
+	int32_t		post_div;	
+
+	/* PLL registers */
+	uint32_t		ppll_div_3;
+	uint32_t		ppll_ref_div;
+	uint32_t		vclk_ecp_cntl;
+	uint32_t		clk_cntl_index;
+	uint32_t		htotal_cntl;
+
+	/* Computed values for PLL2 */
+	uint32_t		dot_clock_freq_2;
+	uint32_t		pll_output_freq_2;
+	int32_t		feedback_div_2;
+	int32_t		post_div_2;
+
+	/* PLL2 registers */
+	uint32_t		p2pll_ref_div;
+	uint32_t		p2pll_div_0;
+	uint32_t		htotal_cntl2;
+};
+
+struct panel_info
+{
+	int32_t xres, yres;
+	int32_t valid;
+	int32_t clock;
+	int32_t hOver_plus, hSync_width, hblank;
+	int32_t vOver_plus, vSync_width, vblank;
+	int32_t hAct_high, vAct_high, int32_terlaced;
+	int32_t pwr_delay;
+	int32_t use_bios_dividers;
+	int32_t ref_divider;
+	int32_t post_divider;
+	int32_t fbk_divider;
+};
+
+struct radeonfb_info;
+
+#ifdef CONFIG_FB_RADEON_I2C
+struct radeon_i2c_chan
+{
+	struct radeonfb_info		*rinfo;
+	uint32_t ddc_reg;
+	struct i2c_adapter		adapter;
+	struct i2c_algo_bit_data	algo;
+};
+#endif
+
+enum radeon_pm_mode {
+	radeon_pm_none	= 0,		/* Nothing supported */
+	radeon_pm_d2	= 0x00000001,	/* Can do D2 state */
+	radeon_pm_off	= 0x00000002,	/* Can resume from D3 cold */
+};
+
+typedef struct
+{
+	uint8_t table_revision;
+	uint8_t table_size;
+	uint8_t tuner_type;
+	uint8_t audio_chip;
+	uint8_t product_id;
+	uint8_t tuner_voltage_teletext_fm;
+	uint8_t i2s_config; /* configuration of the sound chip */
+	uint8_t video_decoder_type;
+	uint8_t video_decoder_host_config;
+	uint8_t input[5];
+} _MM_TABLE;
+
+struct radeonfb_info
+{
+	int32_t handle;     /* PCI BIOS, must be 1st place */
+	int32_t big_endian; /* PCI BIOS */
+	
+	uint32_t cursor_x;
+	uint32_t cursor_y;
+	int32_t cursor_show;
+	uint32_t cursor_start;
+	uint32_t cursor_end;
+	int32_t cursor_fg;
+	int32_t cursor_bg;
+
+	int32_t fifo_slots;       /* Free slots in the FIFO (64 max)   */
+
+	/* Computed values for Radeon */
+	uint32_t dp_gui_master_cntl_clip;
+	uint32_t trans_color;
+
+	/* Saved values for ScreenToScreenCopy */
+	int32_t xdir;
+	int32_t ydir;
+
+	/* ScanlineScreenToScreenColorExpand support */
+	int32_t scanline_h;
+	int32_t scanline_words;
+	int32_t scanline_bpp;     /* Only used for ImageWrite */
+
+	/* Saved values for DashedTwoPoint32_tLine */
+	int32_t dashLen;
+	uint32_t dashPattern;
+	int32_t dash_fg;
+	int32_t dash_bg;
+
+	struct fb_info *info;
+
+	struct radeon_regs state;
+	struct radeon_regs init_state;
+
+	uint8_t name[50];
+
+	uint32_t io_base_phys;
+	uint32_t mmio_base_phys;
+	uint32_t fb_base_phys;
+
+	void *io_base;
+	void *mmio_base;
+	void *fb_base;
+	
+	uint32_t fb_local_base;
+	uint32_t fb_offset;
+	
+	uint32_t bios_seg_phys;
+	void *bios_seg;
+	int32_t fp_bios_start;
+
+	struct
+	{
+		uint8_t red, green, blue, pad;
+	} palette[256];
+
+	int32_t	chipset;
+	uint8_t family;
+	uint8_t rev;
+	int32_t errata;
+	uint32_t video_ram;
+	uint32_t mapped_vram;
+	int32_t vram_width;
+	int32_t vram_ddr;
+
+	int32_t pitch, bpp, depth;
+
+	int32_t has_CRTC2;
+	int32_t is_mobility;
+	int32_t is_IGP;
+	int32_t reversed_DAC;
+	int32_t reversed_TMDS;
+	struct panel_info	panel_info;
+	int32_t mon1_type;
+	uint8_t *mon1_EDID;
+	struct fb_videomode	*mon1_modedb;
+	int32_t mon1_dbsize;
+	int32_t mon2_type;
+	uint8_t *mon2_EDID;
+
+	uint32_t dp_gui_master_cntl;
+
+	struct pll_info bios_pll;
+	struct pll_info pll;
+
+	uint32_t save_regs[100];
+	int32_t asleep;
+	int32_t lock_blank;
+	int32_t dynclk;
+	int32_t no_schedule;
+	enum radeon_pm_mode	pm_mode;
+
+	/* Timer used for delayed LVDS operations */
+  int32_t lvds_timer;
+	uint32_t pending_lvds_gen_cntl;
+
+#ifdef CONFIG_FB_RADEON_I2C
+	struct radeon_i2c_chan i2c[4];
+#endif
+
+  /* Texture */
+  
+	int32_t RenderInited3D;
+	int32_t tilingEnabled;
+	void *RenderTex;
+	uint32_t RenderTexOffset;
+	int32_t RenderTexSize;
+	void (*RenderCallback)(struct radeonfb_info *rinfo);
+	uint32_t RenderTimeout;
+	uint32_t dst_pitch_offset;
+
+
+#ifdef _NOT_USED_
+	/* Video & theatre */
+
+	TheatrePtr theatre;
+
+	int32_t MM_TABLE_valid;
+	_MM_TABLE MM_TABLE;
+
+  int32_t RageTheatreCrystal;
+	int32_t RageTheatreTunerPort;
+	int32_t RageTheatreCompositePort;
+	int32_t RageTheatreSVideoPort;
+	int32_t tunerType;
+	
+	int32_t videoStatus;
+	int32_t encoding;
+	int32_t overlay_deint32_terlacing_method;
+	int32_t video_stream_active;
+	int32_t capture_vbi_data;
+	int32_t v;
+	void *videoLinear;
+	int32_t videoLinearSize;
+	struct
+	{
+		uint32_t y,u,v;
+	} videoLinearOffset;
+#endif /* _NOT_USED_ */
+	
+	int32_t dec_hue;
+	int32_t dec_saturation;
+	int32_t dec_contrast;
+	int32_t dec_brightness;
+};
+
+#define PRIMARY_MONITOR(rinfo)	(rinfo->mon1_type)
+
+/*
+ * IO macros
+ */
+
+/* Note about this function: we have some rare cases where we must not schedule,
+ * this typically happen with our special "wake up early" hook which allows us to
+ * wake up the graphic chip (and thus get the console back) before everything else
+ * on some machines that support that mecanism. At this point32_t, int32_terrupts are off
+ * and scheduling is not permitted
+ */
+static inline void _radeon_msleep(struct radeonfb_info *rinfo, uint32_t ms)
+{
+		mdelay(ms);
+}
+
+#define radeon_msleep(ms)		_radeon_msleep(rinfo,ms)
+
+extern void _OUTREGP(struct radeonfb_info *rinfo, uint32_t addr, uint32_t val, uint32_t mask);
+extern void radeon_pll_errata_after_index(struct radeonfb_info *rinfo);
+extern void radeon_pll_errata_after_data(struct radeonfb_info *rinfo);
+extern uint32_t __INPLL(struct radeonfb_info *rinfo, uint32_t addr);
+extern void __OUTPLL(struct radeonfb_info *rinfo, uint32_t index, uint32_t val);
+extern void __OUTPLLP(struct radeonfb_info *rinfo, uint32_t index, uint32_t val, uint32_t mask);
+
+extern uint16_t _swap_int16_t(uint16_t val);
+extern uint32_t _swap_int32_t(uint32_t val);
+
+#define INREG8(addr)		*((uint8_t *)(rinfo->mmio_base+addr))
+#define INREG16(addr)		_swap_int16_t(*(uint16_t *)(rinfo->mmio_base+addr))
+#define INREG(addr)			_swap_int32_t(*(uint32_t *)(rinfo->mmio_base+addr))
+#define OUTREG8(addr,val)	(*((uint8_t *)(rinfo->mmio_base+addr)) = val)
+#define OUTREG16(addr,val)	(*((uint16_t *)(rinfo->mmio_base+addr)) = _swap_int16_t(val))
+#define OUTREG(addr,val)	(*((uint32_t *)(rinfo->mmio_base+addr)) = _swap_int32_t(val))
+
+extern int32_t *tab_funcs_pci;
+
+#define BIOS_IN8(v)  	(Fast_read_mem_byte(rinfo->handle,rinfo->bios_seg_phys+v))
+#define BIOS_IN16(v) 	((uint16_t)Fast_read_mem_byte(rinfo->handle,rinfo->bios_seg_phys+v) | \
+			  ((uint16_t)Fast_read_mem_byte(rinfo->handle,rinfo->bios_seg_phys+v+1) << 8))
+#define BIOS_IN32(v) 	((uint32_t)Fast_read_mem_byte(rinfo->handle,rinfo->bios_seg_phys+v) | \
+			  ((uint32_t)Fast_read_mem_byte(rinfo->handle,rinfo->bios_seg_phys+v+1) << 8) | \
+			  ((uint32_t)Fast_read_mem_byte(rinfo->handle,rinfo->bios_seg_phys+v+2) << 16) | \
+			  ((uint32_t)Fast_read_mem_byte(rinfo->handle,rinfo->bios_seg_phys+v+3) << 24))
+
+#define ADDRREG(addr)			((volatile uint32_t *)(rinfo->mmio_base + (addr)))
+#define OUTREGP(addr,val,mask)	_OUTREGP(rinfo, addr, val, mask)
+#define INPLL(addr)				__INPLL(rinfo, addr)
+#define OUTPLL(index,val)		__OUTPLL(rinfo, index, val)
+#define OUTPLLP(index,val,mask)	__OUTPLLP(rinfo, index, val, mask)
+
+/*
+ * Inline utilities
+ */
+
+static inline uint32_t radeon_get_dstbpp(uint16_t depth)
+{
+	switch(depth)
+	{
+		case 8: return DST_8BPP;
+		case 15: return DST_15BPP;
+		case 16: return DST_16BPP;
+		case 32: return DST_32BPP;
+		default: return 0;
+	}
+}
+
+/* I2C Functions */
+extern void radeon_create_i2c_busses(struct radeonfb_info *rinfo);
+extern void radeon_delete_i2c_busses(struct radeonfb_info *rinfo);
+extern int32_t radeon_probe_i2c_connector(struct radeonfb_info *rinfo, int32_t conn, uint8_t **out_edid);
+
+/* PM Functions */
+/* extern int32_t radeonfb_pci_suspend(struct pci_dev *pdev, uint32_t state);
+extern int32_t radeonfb_pci_resume(struct pci_dev *pdev);  */
+extern void radeonfb_pm_init(struct radeonfb_info *rinfo, int32_t dynclk);
+extern void radeonfb_pm_exit(struct radeonfb_info *rinfo);
+
+/* Monitor probe functions */
+extern void radeon_probe_screens(struct radeonfb_info *rinfo,
+				 const uint8_t *monitor_layout, int32_t ignore_edid);
+extern void radeon_check_modes(struct radeonfb_info *rinfo, struct mode_option *resolution);
+extern int32_t radeon_match_mode(struct radeonfb_info *rinfo,
+			     struct fb_var_screeninfo *dest,
+			     const struct fb_var_screeninfo *src);
+
+/* Video functions */
+void RADEONResetVideo(struct radeonfb_info *rinfo);
+int32_t RADEONVIP_read(struct radeonfb_info *rinfo, uint32_t address, uint32_t count, uint8_t *buffer);
+int32_t RADEONVIP_fifo_read(struct radeonfb_info *rinfo, uint32_t address, uint32_t count, uint8_t *buffer);
+int32_t RADEONVIP_write(struct radeonfb_info *rinfo, uint32_t address, uint32_t count, uint8_t *buffer);
+int32_t RADEONVIP_fifo_write(struct radeonfb_info *rinfo, uint32_t address, uint32_t count, uint8_t *buffer);
+void RADEONVIP_reset(struct radeonfb_info *rinfo);
+
+void RADEONInitVideo(struct radeonfb_info *rinfo);
+void RADEONShutdownVideo(struct radeonfb_info *rinfo);
+int32_t RADEONPutVideo(struct radeonfb_info *rinfo, int32_t src_x, int32_t src_y, int32_t src_w, int32_t src_h,
+						int32_t drw_x, int32_t drw_y, int32_t drw_w, int32_t drw_h);
+void RADEONStopVideo(struct radeonfb_info *rinfo, int32_t cleanup);
+
+/* Theatre functions */
+//extern TheatrePtr DetectTheatre(struct radeonfb_info *rinfo);
+//extern void RT_SetTint32_t(TheatrePtr t, int32_t hue);
+//extern void RT_SetSaturation(TheatrePtr t, int32_t Saturation);
+//extern void RT_SetBrightness(TheatrePtr t, int32_t Brightness);
+//extern void RT_SetSharpness(TheatrePtr t, uint16_t wSharpness);
+//extern void RT_SetContrast(TheatrePtr t, int32_t Contrast);
+//extern void RT_SetInterlace(TheatrePtr t, uint8_t bInterlace);
+//extern void RT_SetStandard(TheatrePtr t, uint16_t wStandard);
+//extern void RT_SetCombFilter(TheatrePtr t, uint16_t wStandard, uint16_t wConnector);
+//extern void RT_SetOutputVideoSize(TheatrePtr t, uint16_t wHorzSize, uint16_t wVertSize, uint8_t fCC_On, uint8_t fVBICap_On);
+//extern void RT_SetConnector(TheatrePtr t, uint16_t wConnector, int32_t tunerFlag);
+//extern void InitTheatre(TheatrePtr t);
+//extern void ShutdownTheatre(TheatrePtr t);
+//extern void ResetTheatreRegsForNoTVout(TheatrePtr t);
+//extern void ResetTheatreRegsForTVout(TheatrePtr t);
+extern void RADEONVIP_reset(struct radeonfb_info *rinfo);
+
+/* Accel functions */
+
+extern void RADEONWaitForFifoFunction(struct radeonfb_info *rinfo, int32_t entries);
+extern void RADEONEngineFlush(struct radeonfb_info *rinfo);
+extern void RADEONEngineReset(struct radeonfb_info *rinfo);
+extern void RADEONEngineRestore(struct radeonfb_info *rinfo);
+extern void RADEONEngineInit(struct radeonfb_info *rinfo);
+extern void RADEONWaitForIdleMMIO(struct radeonfb_info *rinfo);
+
+#define RADEONWaitForFifo(rinfo, entries)				\
+do {									\
+	if(rinfo->fifo_slots < entries)					\
+		RADEONWaitForFifoFunction(rinfo, entries);			\
+	rinfo->fifo_slots -= entries;					\
+} while(0)
+
+#define radeon_fifo_wait(entries) RADEONWaitForFifo(rinfo, entries)
+#define radeon_engine_flush(rinfo) RADEONEngineFlush(rinfo)
+#define radeonfb_engine_reset(rinfo) RADEONEngineReset(rinfo)
+#define radeonfb_engine_init(rinfo) RADEONEngineInit(rinfo)
+#define radeon_engine_idle() RADEONWaitForIdleMMIO(rinfo)
+
+static inline int32_t radeonfb_sync(struct fb_info *info)
+{
+	struct radeonfb_info *rinfo = info->par;
+	radeon_engine_idle();
+	return 0;
+}
+
+extern void RADEONRestoreAccelStateMMIO(struct fb_info *info);
+extern void RADEONSetupForSolidFillMMIO(struct fb_info *info, int32_t color, int32_t rop, int32_t planemask);
+extern void RADEONSubsequentSolidFillRectMMIO(struct fb_info *info, int32_t x, int32_t y, int32_t w, int32_t h);
+extern void RADEONSetupForSolidLineMMIO(struct fb_info *info, int32_t color, int32_t rop, int32_t planemask);
+extern void RADEONSubsequentSolidHorVertLineMMIO(struct fb_info *info, int32_t x, int32_t y, int32_t len, int32_t dir);   
+
+extern void RADEONSubsequentSolidTwoPointLineMMIO(struct fb_info *info, int32_t xa, int32_t ya, int32_t xb,
+						int32_t yb, int32_t flags);  
+extern void RADEONSetupForDashedLineMMIO(struct fb_info *info, int32_t fg, int32_t bg,
+							int32_t rop, int32_t planemask, int32_t length, uint8_t *pattern);
+extern void RADEONSubsequentDashedTwoPointLineMMIO(struct fb_info *info,
+            int32_t xa, int32_t ya, int32_t xb, int32_t yb, int32_t flags, int32_t phase);  
+extern void RADEONSetupForScreenToScreenCopyMMIO(struct fb_info *info,
+            int32_t xdir, int32_t ydir, int32_t rop, int32_t planemask, int32_t trans_color);
+extern void RADEONSubsequentScreenToScreenCopyMMIO(struct fb_info *info,
+            int32_t xa, int32_t ya, int32_t xb, int32_t yb, int32_t w, int32_t h);   
+extern void RADEONScreenToScreenCopyMMIO(struct fb_info *info,
+            int32_t xa, int32_t ya, int32_t xb, int32_t yb, int32_t w, int32_t h, int32_t rop);
+extern void RADEONSetupForMono8x8PatternFillMMIO(struct fb_info *info,
+            int32_t patternx, int32_t patterny, int32_t fg, int32_t bg, int32_t rop, int32_t planemask);
+extern void RADEONSubsequentMono8x8PatternFillRectMMIO(struct fb_info *info,
+            int32_t patternx, int32_t patterny, int32_t x, int32_t y, int32_t w, int32_t h);
+extern void RADEONSetupForScanlineCPUToScreenColorExpandFillMMIO(struct fb_info *info, 
+            int32_t fg, int32_t bg, int32_t rop, int32_t planemask);
+extern void RADEONSubsequentScanlineCPUToScreenColorExpandFillMMIO(struct fb_info *info,
+            int32_t x, int32_t y, int32_t w, int32_t h, int32_t skipleft);
+extern void RADEONSubsequentScanlineMMIO(struct fb_info *info, uint32_t *buf);
+extern void RADEONSetupForScanlineImageWriteMMIO(struct fb_info *info,
+            int32_t rop, int32_t planemask, int32_t trans_color, int32_t bpp);
+extern void RADEONSubsequentScanlineImageWriteRectMMIO(struct fb_info *info,
+            int32_t x, int32_t y, int32_t w, int32_t h, int32_t skipleft);  
+extern void RADEONSetClippingRectangleMMIO(struct fb_info *info,
+            int32_t xa, int32_t ya, int32_t xb, int32_t yb);
+extern void RADEONDisableClippingMMIO(struct fb_info *info);
+
+#ifndef MCF5445X
+extern int32_t RADEONSetupForCPUToScreenAlphaTextureMMIO(struct fb_info *info, 
+           int32_t op, uint16_t red, uint16_t green, uint16_t blue, uint16_t alpha, uint32_t maskFormat, uint32_t dstFormat, uint8_t *alphaPtr, int32_t alphaPitch, int32_t width, int32_t height, int32_t flags);
+extern int32_t RADEONSetupForCPUToScreenTextureMMIO(struct fb_info *info,
+           int32_t op, uint32_t srcFormat, uint32_t dstFormat, uint8_t *texPtr, int32_t texPitch, int32_t width, int32_t height, int32_t flags);
+extern void RADEONSubsequentCPUToScreenTextureMMIO(struct fb_info *info,
+            int32_t dstx, int32_t dsty, int32_t srcx, int32_t srcy, int32_t width, int32_t height);
+#else
+static __inline__ int32_t RADEONSetupForCPUToScreenAlphaTextureMMIO(struct fb_info *info, 
+ int32_t op, uint16_t red, uint16_t green, uint16_t blue, uint16_t alpha, uint32_t maskFormat, uint32_t dstFormat, uint8_t *alphaPtr, int32_t alphaPitch, int32_t width, int32_t height, int32_t flags)
+{ return FALSE; }
+static __inline__ int32_t RADEONSetupForCPUToScreenTextureMMIO(struct fb_info *info,
+ int32_t op, uint32_t srcFormat, uint32_t dstFormat, uint8_t *texPtr, int32_t texPitch, int32_t width, int32_t height, int32_t flags)
+{ return FALSE; }
+static __inline__ void RADEONSubsequentCPUToScreenTextureMMIO(struct fb_info *info,
+ int32_t dstx, int32_t dsty, int32_t srcx, int32_t srcy, int32_t width, int32_t height) { }
+#endif /* MCF5445X */
+
+/* Cursor functions */
+extern void RADEONSetCursorColors(struct fb_info *info, int32_t bg, int32_t fg);
+extern void RADEONSetCursorPosition(struct fb_info *info, int32_t x, int32_t y);
+extern void RADEONLoadCursorImage(struct fb_info *info, uint16_t *mask, uint16_t *data, int32_t zoom);
+extern void RADEONHideCursor(struct fb_info *info);
+extern void RADEONShowCursor(struct fb_info *info);
+extern int32_t RADEONCursorInit(struct fb_info *info);
+
+/* Other functions */
+extern int32_t radeon_screen_blank(struct radeonfb_info *rinfo, int32_t blank, int32_t mode_switch);
+extern void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode, int32_t reg_only);
+int32_t radeonfb_setcolreg(uint32_t regno, uint32_t red, uint32_t green,
+    uint32_t blue, uint32_t transp, struct fb_info *info);
+extern int32_t radeonfb_pci_register(int32_t handle, const struct pci_device_id *ent);
+extern void radeonfb_pci_unregister(void);
+
+/* global */
+extern uint8_t monitor_layout[];
+extern int16_t default_dynclk;
+extern int16_t ignore_edid;
+extern int16_t mirror;
+extern int16_t virtual;
+extern int16_t force_measure_pll;
+extern int16_t zoom_mouse;
+
+#endif /* __RADEONFB_H__ */
--- a/include/videl.h
+++ b/include/videl.h
@@ -75,23 +75,23 @@ typedef struct {
    uint16_t vss;          /* V SS */
 } VMODE_ENTRY;

-void initialise_falcon_palette(int16_t mode);
-const VMODE_ENTRY *lookup_videl_mode(int16_t mode,int16_t monitor);
+extern void initialise_falcon_palette(int16_t mode);
+extern const VMODE_ENTRY *lookup_videl_mode(int16_t mode,int16_t monitor);

 /* Public XBIOS functions */
-int16_t vsetmode(int16_t mode);
-int16_t vmontype(void);
-int16_t vsetsync(int16_t external);
-int32_t vgetsize(int16_t mode);
-int16_t vsetrgb(int16_t index,int16_t count,int32_t *rgb);
-int16_t vgetrgb(int16_t index,int16_t count,int32_t *rgb);
+extern int16_t vsetmode(int16_t mode);
+extern int16_t vmontype(void);
+extern int16_t vsetsync(int16_t external);
+extern int32_t vgetsize(int16_t mode);
+extern int16_t vsetrgb(int16_t index,int16_t count,int32_t *rgb);
+extern int16_t vgetrgb(int16_t index,int16_t count,int32_t *rgb);

 /* misc routines */
-int16_t get_videl_mode(void);
-int16_t vfixmode(int16_t mode);
-int16_t videl_check_moderez(int16_t moderez);
-uint32_t videl_vram_size(void);
-void videl_get_current_mode_info(uint16_t *planes, uint16_t *hz_rez, uint16_t *vt_rez);
+extern int16_t get_videl_mode(void);
+extern int16_t vfixmode(int16_t mode);
+extern int16_t videl_check_moderez(int16_t moderez);
+extern uint32_t videl_vram_size(void);
+extern void videl_get_current_mode_info(uint16_t *planes, uint16_t *hz_rez, uint16_t *vt_rez);

 extern int16_t current_video_mode;

--- a/net/arp.c
+++ b/net/arp.c
@@ -9,7 +9,7 @@
 #include <stdbool.h>
 #include <stddef.h>

-#define TIMER_NETWORK 0
+#define TIMER_NETWORK 3

 static uint8_t *arp_find_pair(ARP_INFO *arptab, uint16_t protocol, uint8_t *hwa, uint8_t *pa)
 {
--- a/net/bootp.c
+++ b/net/bootp.c
@@ -11,7 +11,7 @@
 #include <stddef.h>
 #include "bas_printf.h"

-#define TIMER_NETWORK 0
+#define TIMER_NETWORK 3

 static struct bootp_connection connection;
 #define XID			0x1234		/* this is arbitrary */
--- a/net/nbuf.c
+++ b/net/nbuf.c
@@ -41,7 +41,7 @@ int nbuf_init(void)
 	}

 #ifdef DEBUG_PRINT
-	printf("Creating %d net buffers of %d bytes\n",NBUF_MAX,NBUF_SZ);
+	printf("Creating %d net buffers of %d bytes\r\n",NBUF_MAX,NBUF_SZ);
 #endif

 	for (i = 0; i < NBUF_MAX; ++i)
@@ -70,7 +70,7 @@ int nbuf_init(void)
 		queue_add(&nbuf_queue[NBUF_FREE], (QNODE *)nbuf);
 	}

-	xprintf("NBUF allocation complete\n");
+	xprintf("NBUF allocation complete\r\n");

 	return 0;
 }
--- a/net/nif.c
+++ b/net/nif.c
@@ -50,7 +50,7 @@ void nif_protocol_handler(NIF *nif, uint16_t protocol, NBUF *pNbuf)
 	}
 }

-void *nif_get_protocol_info (NIF *nif, uint16_t protocol)
+void *nif_get_protocol_info(NIF *nif, uint16_t protocol)
 {
 	/*
 	 * This function searches the list of supported protocols
@@ -67,8 +67,7 @@ void *nif_get_protocol_info (NIF *nif, uint16_t protocol)
 	return (void *)0;
 }

-int nif_bind_protocol (NIF *nif, uint16_t protocol,
-		void (*handler)(NIF *,NBUF *),
+int nif_bind_protocol(NIF *nif, uint16_t protocol, void (*handler)(NIF *,NBUF *),
 					void *info)
 {
 	/*
--- a/net/tftp.c
+++ b/net/tftp.c
@@ -18,7 +18,7 @@
 #include "net.h"
 #include "net_timer.h"

-#define TIMER_NETWORK	0
+#define TIMER_NETWORK	3

 /* The one and only TFTP connection */
 static TFTP_Connection tcxn;
--- a/net/udp.c
+++ b/net/udp.c
@@ -135,10 +135,8 @@ int udp_send(NIF *nif, uint8_t *dest, int sport, int dport, NBUF *pNbuf)
 	/* Add the length of the UDP packet to the total length of the packet */
 	pNbuf->length += 8;

-	return (ip_send(nif, dest,
-				ip_get_myip(nif_get_protocol_info(nif, ETH_FRM_IP)),
-				IP_PROTO_UDP,
-				pNbuf));
+	return (ip_send(nif, dest, ip_get_myip(nif_get_protocol_info(nif, ETH_FRM_IP)),
+				IP_PROTO_UDP, pNbuf));
 }

 void udp_handler(NIF *nif, NBUF *pNbuf)
--- a/radeon/radeon_base.c
+++ b/radeon/radeon_base.c
--- a/sys/BaS.c
+++ b/sys/BaS.c
@@ -44,6 +44,15 @@
 #include "nbuf.h"
 #include "nif.h"
 #include "fec.h"
+#include "interrupts.h"
+#include "exceptions.h"
+
+#define BAS_DEBUG
+#if defined(BAS_DEBUG)
+#define dbg(format, arg...) do { xprintf("DEBUG: " format "\r\n", ##arg); } while (0)
+#else
+#define dbg(format, arg...) do { ; } while (0)
+#endif

 /* imported routines */
 extern int mmu_init();
@@ -61,11 +70,6 @@ extern uint8_t _EMUTOS[];
 extern uint8_t _EMUTOS_SIZE[];
 #define EMUTOS_SIZE ((uint32_t)_EMUTOS_SIZE) /* size of EmuTOS, in bytes */

-NIF nif1;
-#ifdef MACHINE_M5484LITE
-NIF nif2;
-#endif
-
 /*
 * check if it is possible to transfer data to PIC
 */
@@ -126,7 +130,7 @@ void pic_init(void)

 	if (answer[0] != 'O' || answer[1] != 'K' || answer[2] != '!')
 	{
-		xprintf("PIC initialization failed. Already initialized?\r\n");
+		dbg("%s: PIC initialization failed. Already initialized?\r\n", __FUNCTION__);
 	}
 	else
 	{
@@ -236,24 +240,47 @@ void disable_coldfire_interrupts()



+NIF nif1;
+#ifdef MACHINE_M5484LITE
+NIF nif2;
+#endif
+static IP_INFO ip_info;
+static ARP_INFO	arp_info;
+
+
 void network_init(void)
 {
 	uint8_t mac[6] = {0x00, 0x04, 0x9f, 0x01, 0x01, 0x01}; /* this is a Freescale MAC address */
 	uint8_t bc[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; /* this is our broadcast MAC address */
-	IP_ADDR myip = {0, 0, 0, 0};
-	IP_ADDR gateway = {0, 0, 0, 0};
-	IP_ADDR netmask = {0, 0, 0, 0};
-	IP_INFO info;
+	IP_ADDR myip = {192, 168, 1, 100};
+	IP_ADDR gateway = {192, 168, 1, 1};
+	IP_ADDR netmask = {255, 255, 255, 0};
+	int vector;
+	int (*handler)(void *, void *);
+
+	handler = fec0_interrupt_handler;
+	vector = 103;
+
+	if (!isr_register_handler(ISR_DBUG_ISR, vector, handler, NULL, (void *) &nif1))
+	{
+		dbg("%s: unable to register handler\r\n", __FUNCTION__);
+		return;
+	}

-	fec_eth_setup(0, FEC_MODE_MII, FEC_MII_100BASE_TX, FEC_MII_FULL_DUPLEX, mac);
 	nif_init(&nif1);
 	nif1.mtu = ETH_MTU;
 	nif1.send = fec0_send;
+	fec_eth_setup(0, FEC_MODE_MII, FEC_MII_100BASE_TX, FEC_MII_FULL_DUPLEX, mac);
+	fec_eth_setup(1, FEC_MODE_MII, FEC_MII_100BASE_TX, FEC_MII_FULL_DUPLEX, mac);
 	memcpy(nif1.hwa, mac, 6);
 	memcpy(nif1.broadcast, bc, 6);

-	ip_init(&info, myip, gateway, netmask);
-	udp_init();
+	arp_init(&arp_info);
+	nif_bind_protocol(&nif1, ETH_FRM_ARP, arp_handler, (void *) &arp_info);
+
+	ip_init(&ip_info, myip, gateway, netmask);
+	nif_bind_protocol(&nif1, ETH_FRM_IP, ip_handler, (void *) &ip_info);
+
 	bootp_request(&nif1, 0);
 }

@@ -324,6 +351,7 @@ void BaS(void)

 	enable_coldfire_interrupts();

+#ifdef _NOT_USED_
 	screen_init();

 	    /* experimental */
@@ -346,6 +374,7 @@ void BaS(void)
 			}
 		}
 	}
+#endif /* _NOT_USED_ */

 #endif /* MACHINE_FIREBEE */

@@ -392,7 +421,8 @@ void BaS(void)
 	xprintf("BaS initialization finished, enable interrupts\r\n");
 	enable_coldfire_interrupts();

-	// network_init();
+	set_ipl(0);
+	network_init();

 	xprintf("call EmuTOS\r\n");
 	ROM_HEADER* os_header = (ROM_HEADER*)TOS;
--- a/sys/exceptions.S
+++ b/sys/exceptions.S
@@ -295,12 +295,19 @@ init_vec_loop:
 		lea		handler_psc3(pc),a1
 		// PSC3 interrupt source = 32
 		move.l	a1,(INT_SOURCE_PSC3 + 64) * 4(a0)
-// timer vectors (used for video page copy on the FireBee)
+// timer vectors (triggers when vbashi gets changed, used for video page copy)
 		lea		handler_gpt0(pc),a1
 		// GPT0 interrupt source = 62
 		move.l	a1,(INT_SOURCE_GPT0 + 64) * 4(a0)
 #endif /* MACHINE_FIREBEE */

+		lea		_lowlevel_isr_handler,a1
+		move.l	a1,(INT_SOURCE_GPT1 + 64) * 4(a0)
+		move.l	a1,(INT_SOURCE_GPT2 + 64) * 4(a0)
+		move.l	a1,(INT_SOURCE_GPT3 + 64) * 4(a0)
+		move.l	a1,(INT_SOURCE_FEC0 + 64) * 4(a0)
+		move.l	a1,(INT_SOURCE_FEC1 + 64) * 4(a0)
+
 		move.l	(sp)+,a2			// Restore registers
 		rts
 /*
@@ -462,7 +469,6 @@ flpoow:
 		halt
 		nop
 		nop
-
 #endif /* _NOT_USED */

 irq1:
@@ -977,10 +983,10 @@ video_chg_end:
 * low-level interrupt service routine for routines registered with
 * isr_register_handler()
 */
- 		.global	_asm_isr_handler
+ 		.global	_lowlevel_isr_handler
 		.extern	_isr_execute_handler

-_asm_isr_handler:
+_lowlevel_isr_handler:
 		link	a6,#-4*4
 		movem.l	d0-d1/a0-a1,(sp)

@@ -991,13 +997,11 @@ _asm_isr_handler:
 		jsr		_isr_execute_handler
 		lea		4(sp),sp
 		cmp.l	#1,d0
-		//beq		handled
-#ifdef _NOT_USED_
+		beq		handled
 nothandled:
 		movem.l	(sp),d0-d1/a0-a1
 		unlk	a6
-		jmp		asm_exception_handler
-#endif /* _NOT_USED_ */
+		jmp		std_exc_vec
 handled:
 		movem.l	(sp),d0-d1/a0-a1
 		unlk	a6
--- a/sys/interrupts.c
+++ b/sys/interrupts.c
@@ -34,6 +34,13 @@
 extern void (*rt_vbr[])(void);
 #define VBR	rt_vbr

+#define IRQ_DEBUG
+#if defined(IRQ_DEBUG)
+#define dbg(format, arg...) do { xprintf("DEBUG: " format "\r\n", ##arg); } while (0)
+#else
+#define dbg(format, arg...) do { ; } while (0)
+#endif
+
 /*
 * register an interrupt handler at the Coldfire interrupt controller and add the handler to
 * the interrupt vector table
@@ -113,8 +120,7 @@ void isr_init(void)
 }


-int isr_register_handler (
-		int type, int vector, 
+int isr_register_handler(int type, int vector, 
 		int (*handler)(void *, void *), void *hdev, void *harg)
 {
 	/*
@@ -131,7 +137,8 @@ int isr_register_handler (
 			((type != ISR_DBUG_ISR) && (type != ISR_USER_ISR)) ||
 			(handler == NULL))
 	{
-		return true;
+		dbg("%s: illegal type, vector or handler!\r\n", __FUNCTION__);
+		return false;
 	}

 	for (index = 0; index < UIF_MAX_ISR_ENTRY; index++)
@@ -140,7 +147,8 @@ int isr_register_handler (
 				(isrtab[index].type == type))
 		{
 			/* only one entry of each type per vector */
-			return 0;
+			dbg("%s: already set handler with this type and vector (%d, %d)\r\n", __FUNCTION__, type, vector);
+			return false;
 		}

 		if (isrtab[index].vector == 0)
@@ -150,9 +158,10 @@ int isr_register_handler (
 			isrtab[index].handler = handler;
 			isrtab[index].hdev = hdev;
 			isrtab[index].harg = harg;
-			return 1;
+			return true;
 		}
 	}
+	dbg("%s: no available slots\n\t", __FUNCTION__);
 	return false;   /* no available slots */
 }

--- a/video/video.c
+++ b/video/video.c
@@ -226,20 +226,20 @@ void screen_init(void)
 * resolution / video mode appropriately
 */
 	monitor_type = MON_COLOR;
-	xprintf("monitor_type = %d\n", monitor_type);
+	xprintf("monitor_type = %d\r\n", monitor_type);

 	/* reset VIDEL on boot-up */
 	/* first set the physbase to a safe memory */
-	setphys(0xd00000,0);
+	setphys(0xd00000, 0);

 	if (!lookup_videl_mode(boot_resolution, monitor_type)) { /* mode isn't in table */
-	    xprintf("Invalid video mode 0x%04x changed to 0x%04x\n",
+	    xprintf("Invalid video mode 0x%04x changed to 0x%04x\r\n",
 	            boot_resolution, FALCON_DEFAULT_BOOT);
 	    boot_resolution = FALCON_DEFAULT_BOOT;  /* so pick one that is */
 	}

 	if (!VALID_VDI_BPP(boot_resolution)) {      /* mustn't confuse VDI */
-	    xprintf("VDI doesn't support video mode 0x%04x, changed to 0x%04x\n",
+	    xprintf("VDI doesn't support video mode 0x%04x, changed to 0x%04x\r\n",
 	            boot_resolution, FALCON_DEFAULT_BOOT);
 	    boot_resolution = FALCON_DEFAULT_BOOT;  /* so use default */
 	}