commented everything which is not needed to debug video system/DDR controller for now
This commit is contained in:
Markus Fröschle
@@ -831,31 +831,31 @@ BEGIN
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ddrwr_d_sel1 => ddrwr_d_sel(1)
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);
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I_BLITTER: FBEE_BLITTER
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PORT MAP(
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resetn => reset_n,
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CLK_MAIN => CLK_MAIN,
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clk_ddr0 => clk_ddr(0),
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fb_adr => fb_adr,
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FB_ALE => FB_ALE,
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FB_SIZE1 => FB_SIZE(1),
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FB_SIZE0 => FB_SIZE(0),
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FB_CSn => FB_CSn,
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FB_OEn => FB_OEn,
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FB_WRn => FB_WRn,
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DATA_IN => FB_AD,
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DATA_OUT => data_out_blitter,
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DATA_EN => data_en_blitter,
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blitter_adr => blitter_adr,
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blitter_sig => blitter_sig,
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blitter_wr => blitter_wr,
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blitter_on => blitter_on,
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blitter_run => blitter_run,
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BLITTER_DIN => vd_vz,
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blitter_dout => blitter_dout,
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blitter_ta => blitter_ta,
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blitter_dack_sr => blitter_dack_sr
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);
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-- I_BLITTER: FBEE_BLITTER
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-- PORT MAP(
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-- resetn => reset_n,
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-- CLK_MAIN => CLK_MAIN,
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-- clk_ddr0 => clk_ddr(0),
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-- fb_adr => fb_adr,
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-- FB_ALE => FB_ALE,
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-- FB_SIZE1 => FB_SIZE(1),
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-- FB_SIZE0 => FB_SIZE(0),
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-- FB_CSn => FB_CSn,
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-- FB_OEn => FB_OEn,
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-- FB_WRn => FB_WRn,
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-- DATA_IN => FB_AD,
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-- DATA_OUT => data_out_blitter,
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-- DATA_EN => data_en_blitter,
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-- blitter_adr => blitter_adr,
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-- blitter_sig => blitter_sig,
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-- blitter_wr => blitter_wr,
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-- blitter_on => blitter_on,
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-- blitter_run => blitter_run,
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-- BLITTER_DIN => vd_vz,
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-- blitter_dout => blitter_dout,
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-- blitter_ta => blitter_ta,
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-- blitter_dack_sr => blitter_dack_sr
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-- );
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I_VIDEOSYSTEM: VIDEO_SYSTEM
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PORT MAP(
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@@ -912,203 +912,203 @@ BEGIN
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blitter_run => blitter_run
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);
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I_INTHANDLER: INTHANDLER
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PORT MAP(
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CLK_MAIN => CLK_MAIN,
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resetn => reset_n,
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fb_adr => fb_adr,
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FB_CSn => FB_CSn(2 DOWNTO 1),
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FB_OEn => FB_OEn,
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FB_SIZE0 => FB_SIZE(0),
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FB_SIZE1 => FB_SIZE(1),
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FB_WRn => FB_WRn,
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FB_AD_IN => FB_AD,
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FB_AD_OUT => fb_ad_out_ih,
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FB_AD_EN_31_24 => fb_ad_en_31_24_ih,
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FB_AD_EN_23_16 => fb_ad_en_23_16_ih,
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FB_AD_EN_15_8 => fb_ad_en_15_8_ih,
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FB_AD_EN_7_0 => fb_ad_en_7_0_ih,
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PIC_INT => PIC_INT,
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E0_INT => E0_INT,
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DVI_INT => DVI_INT,
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PCI_INTAn => PCI_INTAn,
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PCI_INTBn => PCI_INTBn,
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PCI_INTCn => PCI_INTCn,
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PCI_INTDn => PCI_INTDn,
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mfp_intn => mfp_int_n,
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dsp_int => dsp_int,
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VSYNC => vsync_i,
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HSYNC => hsync_i,
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drq_dma => drq_dma,
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IRQn => IRQn,
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int_handler_ta => int_handler_ta,
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fbee_conf => fbee_conf,
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TIN0 => TIN0
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);
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-- I_INTHANDLER: INTHANDLER
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-- PORT MAP(
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-- CLK_MAIN => CLK_MAIN,
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-- resetn => reset_n,
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-- fb_adr => fb_adr,
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-- FB_CSn => FB_CSn(2 DOWNTO 1),
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-- FB_OEn => FB_OEn,
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-- FB_SIZE0 => FB_SIZE(0),
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-- FB_SIZE1 => FB_SIZE(1),
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-- FB_WRn => FB_WRn,
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-- FB_AD_IN => FB_AD,
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-- FB_AD_OUT => fb_ad_out_ih,
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-- FB_AD_EN_31_24 => fb_ad_en_31_24_ih,
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-- FB_AD_EN_23_16 => fb_ad_en_23_16_ih,
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-- FB_AD_EN_15_8 => fb_ad_en_15_8_ih,
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-- FB_AD_EN_7_0 => fb_ad_en_7_0_ih,
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-- PIC_INT => PIC_INT,
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-- E0_INT => E0_INT,
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-- DVI_INT => DVI_INT,
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-- PCI_INTAn => PCI_INTAn,
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-- PCI_INTBn => PCI_INTBn,
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-- PCI_INTCn => PCI_INTCn,
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-- PCI_INTDn => PCI_INTDn,
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-- mfp_intn => mfp_int_n,
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-- dsp_int => dsp_int,
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-- VSYNC => vsync_i,
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-- HSYNC => hsync_i,
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-- drq_dma => drq_dma,
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-- IRQn => IRQn,
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-- int_handler_ta => int_handler_ta,
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-- fbee_conf => fbee_conf,
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-- TIN0 => TIN0
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-- );
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I_DMA: FBEE_DMA
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PORT MAP(
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RESET => NOT reset_n,
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CLK_MAIN => CLK_MAIN,
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clk_fdc => clk_fdc,
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-- I_DMA: FBEE_DMA
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-- PORT MAP(
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-- RESET => NOT reset_n,
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-- CLK_MAIN => CLK_MAIN,
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-- clk_fdc => clk_fdc,
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--
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-- fb_adr => fb_adr(26 DOWNTO 0),
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-- FB_ALE => FB_ALE,
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-- FB_SIZE => FB_SIZE,
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-- FB_CSn => FB_CSn(2 DOWNTO 1),
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-- FB_OEn => FB_OEn,
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-- FB_WRn => FB_WRn,
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-- FB_AD_IN => FB_AD,
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-- FB_AD_OUT => fb_ad_out_dma,
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-- FB_AD_EN_31_24 => fb_ad_en_31_24_dma,
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-- FB_AD_EN_23_16 => fb_ad_en_23_16_dma,
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-- FB_AD_EN_15_8 => fb_ad_en_15_8_dma,
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-- FB_AD_EN_7_0 => fb_ad_en_7_0_dma,
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--
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-- ACSI_DIR => ACSI_DIR,
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-- ACSI_D_IN => ACSI_D,
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-- acsi_d_out => acsi_d_out,
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-- acsi_d_en => acsi_d_en,
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-- ACSI_CSn => ACSI_CSn,
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-- ACSI_A1 => ACSI_A1,
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-- ACSI_resetn => ACSI_reset_n,
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-- ACSI_DRQn => ACSI_DRQn,
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-- ACSI_ACKn => ACSI_ACKn,
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--
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-- DATA_IN_FDC => data_out_fdc,
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-- DATA_IN_SCSI => data_out_scsi,
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-- data_out_fdc_SCSI => data_in_fdc_scsi,
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--
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-- DMA_DRQ_IN => drq_fdc,
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-- DMA_DRQ_OUT => drq_dma,
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-- DMA_DRQ11 => drq11_dma,
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--
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-- scsi_drq => scsi_drq,
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-- scsi_dackn => scsi_dack_n,
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-- scsi_int => scsi_int,
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-- scsi_csn => scsi_csn,
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-- scsi_cs => scsi_cs,
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--
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-- ca => ca,
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-- FLOPPY_HD_DD => FDD_HD_DD,
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-- wdc_bsl0 => wdc_bsl0,
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-- fdc_csn => fdc_cs_n,
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-- fdc_wrn => fdc_wr_n,
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-- fd_int => fd_int,
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-- IDE_INT => IDE_INT,
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-- dma_cs => dma_cs
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-- );
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fb_adr => fb_adr(26 DOWNTO 0),
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FB_ALE => FB_ALE,
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FB_SIZE => FB_SIZE,
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FB_CSn => FB_CSn(2 DOWNTO 1),
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FB_OEn => FB_OEn,
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FB_WRn => FB_WRn,
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FB_AD_IN => FB_AD,
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FB_AD_OUT => fb_ad_out_dma,
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FB_AD_EN_31_24 => fb_ad_en_31_24_dma,
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FB_AD_EN_23_16 => fb_ad_en_23_16_dma,
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FB_AD_EN_15_8 => fb_ad_en_15_8_dma,
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FB_AD_EN_7_0 => fb_ad_en_7_0_dma,
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-- I_IDE_CF_SD_ROM: IDE_CF_SD_ROM
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-- PORT MAP(
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-- RESET => NOT reset_n,
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-- CLK_MAIN => CLK_MAIN,
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--
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-- fb_adr => fb_adr(19 DOWNTO 5),
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-- FB_CS1n => FB_CSn(1),
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-- FB_WRn => FB_WRn,
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-- fb_b0 => fb_b0,
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-- fb_b1 => fb_b1,
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--
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-- fbee_conf => fbee_conf(31 DOWNTO 30),
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--
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-- RP_UDSn => RP_UDSn,
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-- RP_ldsn => RP_ldsn,
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--
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-- SD_CLK => SD_CLK,
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-- SD_D0 => SD_D0,
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-- SD_D1 => SD_D1,
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-- SD_D2 => SD_D2,
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-- SD_CD_D3_IN => SD_D3,
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-- sd_cd_d3_out => sd_cd_d3_out,
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-- sd_cd_d3_en => sd_cd_d3_en,
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-- SD_CMD_D1_IN => SD_CMD_D1,
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-- sd_cmd_d1_out => sd_cmd_d1_out,
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-- sd_cmd_d1_en => sd_cmd_d1_en,
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-- SD_caRD_DETECT => SD_caRD_DETECT,
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-- SD_WP => SD_WP,
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--
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-- IDE_RDY => IDE_RDY,
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-- IDE_WRn => IDE_WRn,
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-- IDE_RDn => IDE_RDn,
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-- IDE_CSn => IDE_CSn,
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-- -- IDE_DRQn =>, -- Not used.
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-- ide_cf_ta => ide_cf_ta,
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--
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-- ROM4n => ROM4n,
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-- ROM3n => ROM3n,
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--
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-- CF_WP => CF_WP,
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-- CF_CSn => CF_CSn
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-- );
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ACSI_DIR => ACSI_DIR,
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ACSI_D_IN => ACSI_D,
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acsi_d_out => acsi_d_out,
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acsi_d_en => acsi_d_en,
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ACSI_CSn => ACSI_CSn,
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ACSI_A1 => ACSI_A1,
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ACSI_resetn => ACSI_reset_n,
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ACSI_DRQn => ACSI_DRQn,
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ACSI_ACKn => ACSI_ACKn,
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-- I_DSP: DSP
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-- PORT MAP(
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-- CLK_33M => CLK_33M,
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-- CLK_MAIN => CLK_MAIN,
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-- FB_OEn => FB_OEn,
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-- FB_WRn => FB_WRn,
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-- FB_CS1n => FB_CSn(1),
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-- FB_CS2n => FB_CSn(2),
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-- FB_SIZE0 => FB_SIZE(0),
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-- FB_SIZE1 => FB_SIZE(1),
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-- FB_BURSTn => FB_BURSTn,
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-- fb_adr => fb_adr,
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-- resetn => reset_n,
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-- FB_CS3n => FB_CSn(3),
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-- SRCSn => DSP_SRCSn,
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-- SRBLEn => DSP_SRBLEn,
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-- SRBHEn => DSP_SRBHEn,
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-- SRWEn => DSP_SRWEn,
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-- SROEn => DSP_SROEn,
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-- dsp_int => dsp_int,
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-- dsp_ta => dsp_ta,
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-- FB_AD_IN => FB_AD,
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-- FB_AD_OUT => fb_ad_out_dsp,
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-- FB_AD_EN => fb_ad_en_dsp,
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-- IO_IN => DSP_IO,
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-- IO_OUT => dsp_io_out,
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-- IO_EN => dsp_io_en,
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-- SRD_IN => DSP_SRD,
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-- SRD_OUT => dsp_srd_out,
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-- SRD_EN => dsp_srd_en
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-- );
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DATA_IN_FDC => data_out_fdc,
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DATA_IN_SCSI => data_out_scsi,
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data_out_fdc_SCSI => data_in_fdc_scsi,
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DMA_DRQ_IN => drq_fdc,
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DMA_DRQ_OUT => drq_dma,
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DMA_DRQ11 => drq11_dma,
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scsi_drq => scsi_drq,
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scsi_dackn => scsi_dack_n,
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scsi_int => scsi_int,
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scsi_csn => scsi_csn,
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scsi_cs => scsi_cs,
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ca => ca,
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FLOPPY_HD_DD => FDD_HD_DD,
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wdc_bsl0 => wdc_bsl0,
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fdc_csn => fdc_cs_n,
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fdc_wrn => fdc_wr_n,
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fd_int => fd_int,
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IDE_INT => IDE_INT,
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dma_cs => dma_cs
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);
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I_IDE_CF_SD_ROM: IDE_CF_SD_ROM
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PORT MAP(
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RESET => NOT reset_n,
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CLK_MAIN => CLK_MAIN,
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fb_adr => fb_adr(19 DOWNTO 5),
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FB_CS1n => FB_CSn(1),
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FB_WRn => FB_WRn,
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fb_b0 => fb_b0,
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fb_b1 => fb_b1,
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fbee_conf => fbee_conf(31 DOWNTO 30),
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RP_UDSn => RP_UDSn,
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RP_ldsn => RP_ldsn,
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SD_CLK => SD_CLK,
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SD_D0 => SD_D0,
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SD_D1 => SD_D1,
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SD_D2 => SD_D2,
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SD_CD_D3_IN => SD_D3,
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sd_cd_d3_out => sd_cd_d3_out,
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sd_cd_d3_en => sd_cd_d3_en,
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SD_CMD_D1_IN => SD_CMD_D1,
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sd_cmd_d1_out => sd_cmd_d1_out,
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sd_cmd_d1_en => sd_cmd_d1_en,
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SD_caRD_DETECT => SD_caRD_DETECT,
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SD_WP => SD_WP,
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IDE_RDY => IDE_RDY,
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IDE_WRn => IDE_WRn,
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IDE_RDn => IDE_RDn,
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IDE_CSn => IDE_CSn,
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-- IDE_DRQn =>, -- Not used.
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ide_cf_ta => ide_cf_ta,
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ROM4n => ROM4n,
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ROM3n => ROM3n,
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CF_WP => CF_WP,
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CF_CSn => CF_CSn
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);
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I_DSP: DSP
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PORT MAP(
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CLK_33M => CLK_33M,
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CLK_MAIN => CLK_MAIN,
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FB_OEn => FB_OEn,
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FB_WRn => FB_WRn,
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FB_CS1n => FB_CSn(1),
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FB_CS2n => FB_CSn(2),
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FB_SIZE0 => FB_SIZE(0),
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FB_SIZE1 => FB_SIZE(1),
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FB_BURSTn => FB_BURSTn,
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fb_adr => fb_adr,
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resetn => reset_n,
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FB_CS3n => FB_CSn(3),
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SRCSn => DSP_SRCSn,
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SRBLEn => DSP_SRBLEn,
|
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SRBHEn => DSP_SRBHEn,
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SRWEn => DSP_SRWEn,
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SROEn => DSP_SROEn,
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dsp_int => dsp_int,
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dsp_ta => dsp_ta,
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FB_AD_IN => FB_AD,
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FB_AD_OUT => fb_ad_out_dsp,
|
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FB_AD_EN => fb_ad_en_dsp,
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IO_IN => DSP_IO,
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IO_OUT => dsp_io_out,
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IO_EN => dsp_io_en,
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SRD_IN => DSP_SRD,
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SRD_OUT => dsp_srd_out,
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SRD_EN => dsp_srd_en
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);
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I_SOUND: WF2149IP_TOP_SOC
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PORT MAP(
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SYS_CLK => CLK_MAIN,
|
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resetn => reset_n,
|
||||
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WAV_CLK => clk_2m0,
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SELn => '1',
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BDIR => sndir_i,
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BC2 => '1',
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BC1 => sndcs_i,
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A9n => '0',
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A8 => '1',
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DA_IN => FB_AD(31 DOWNTO 24),
|
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DA_OUT => da_out_x,
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IO_A_IN => x"00", -- All port pINs are dedicated OUTputs.
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IO_A_OUT(7) => ide_res_i,
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IO_A_OUT(6) => lp_dir_x,
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IO_A_OUT(5) => LP_STR,
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IO_A_OUT(4) => DTR,
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IO_A_OUT(3) => RTS,
|
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IO_A_OUT(2) => RESERVED_1,
|
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IO_A_OUT(1) => DSA_D,
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IO_A_OUT(0) => FDD_SDSELn,
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-- IO_A_EN => TOUT0n, -- Not required.
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IO_B_IN => LP_D,
|
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IO_B_OUT => lp_d_x,
|
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-- IO_B_EN => -- Not used.
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OUT_A => YM_QA,
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OUT_B => YM_QB,
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OUT_C => YM_QC
|
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);
|
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-- I_SOUND: WF2149IP_TOP_SOC
|
||||
-- PORT MAP(
|
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-- SYS_CLK => CLK_MAIN,
|
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-- resetn => reset_n,
|
||||
--
|
||||
-- WAV_CLK => clk_2m0,
|
||||
-- SELn => '1',
|
||||
--
|
||||
-- BDIR => sndir_i,
|
||||
-- BC2 => '1',
|
||||
-- BC1 => sndcs_i,
|
||||
--
|
||||
-- A9n => '0',
|
||||
-- A8 => '1',
|
||||
-- DA_IN => FB_AD(31 DOWNTO 24),
|
||||
-- DA_OUT => da_out_x,
|
||||
--
|
||||
-- IO_A_IN => x"00", -- All port pINs are dedicated OUTputs.
|
||||
-- IO_A_OUT(7) => ide_res_i,
|
||||
-- IO_A_OUT(6) => lp_dir_x,
|
||||
-- IO_A_OUT(5) => LP_STR,
|
||||
-- IO_A_OUT(4) => DTR,
|
||||
-- IO_A_OUT(3) => RTS,
|
||||
-- IO_A_OUT(2) => RESERVED_1,
|
||||
-- IO_A_OUT(1) => DSA_D,
|
||||
-- IO_A_OUT(0) => FDD_SDSELn,
|
||||
-- -- IO_A_EN => TOUT0n, -- Not required.
|
||||
-- IO_B_IN => LP_D,
|
||||
-- IO_B_OUT => lp_d_x,
|
||||
-- -- IO_B_EN => -- Not used.
|
||||
--
|
||||
-- OUT_A => YM_QA,
|
||||
-- OUT_B => YM_QB,
|
||||
-- OUT_C => YM_QC
|
||||
-- );
|
||||
|
||||
I_MFP: WF68901IP_TOP_SOC
|
||||
PORT MAP(
|
||||
@@ -1159,32 +1159,32 @@ BEGIN
|
||||
-- TRn => -- Not used.
|
||||
);
|
||||
|
||||
I_ACIA_MIDI: WF6850IP_TOP_SOC
|
||||
PORT MAP(
|
||||
CLK => CLK_MAIN,
|
||||
resetn => reset_n,
|
||||
|
||||
CS2n => '0',
|
||||
CS1 => fb_adr(2),
|
||||
CS0 => acia_cs,
|
||||
E => acia_cs,
|
||||
RWn => FB_WRN,
|
||||
RS => fb_adr(1),
|
||||
|
||||
DATA_IN => FB_AD(31 DOWNTO 24),
|
||||
DATA_OUT => data_out_acia_iI,
|
||||
-- DATA_EN => -- Not used.
|
||||
|
||||
TXCLK => clk_500k,
|
||||
RXCLK => clk_500k,
|
||||
RXDATA => MIDI_IN,
|
||||
CTSn => '0',
|
||||
DCDn => '0',
|
||||
|
||||
IRQn => irq_midi_n,
|
||||
TXDATA => midi_out
|
||||
--RTSn => -- Not used.
|
||||
);
|
||||
-- I_ACIA_MIDI: WF6850IP_TOP_SOC
|
||||
-- PORT MAP(
|
||||
-- CLK => CLK_MAIN,
|
||||
-- resetn => reset_n,
|
||||
--
|
||||
-- CS2n => '0',
|
||||
-- CS1 => fb_adr(2),
|
||||
-- CS0 => acia_cs,
|
||||
-- E => acia_cs,
|
||||
-- RWn => FB_WRN,
|
||||
-- RS => fb_adr(1),
|
||||
--
|
||||
-- DATA_IN => FB_AD(31 DOWNTO 24),
|
||||
-- DATA_OUT => data_out_acia_iI,
|
||||
-- -- DATA_EN => -- Not used.
|
||||
--
|
||||
-- TXCLK => clk_500k,
|
||||
-- RXCLK => clk_500k,
|
||||
-- RXDATA => MIDI_IN,
|
||||
-- CTSn => '0',
|
||||
-- DCDn => '0',
|
||||
--
|
||||
-- IRQn => irq_midi_n,
|
||||
-- TXDATA => midi_out
|
||||
-- --RTSn => -- Not used.
|
||||
-- );
|
||||
|
||||
I_ACIA_KEYBOARD: WF6850IP_TOP_SOC
|
||||
PORT MAP(
|
||||
@@ -1214,98 +1214,98 @@ BEGIN
|
||||
--RTSn => -- Not used.
|
||||
);
|
||||
|
||||
I_SCSI: WF5380_TOP_SOC
|
||||
PORT MAP(
|
||||
CLK => clk_fdc,
|
||||
resetn => reset_n,
|
||||
ADR => ca,
|
||||
DATA_IN => data_in_fdc_scsi,
|
||||
DATA_OUT => data_out_scsi,
|
||||
--DATA_EN =>,
|
||||
-- Bus and DMA controls:
|
||||
CSn => scsi_csn,
|
||||
RDn => NOT fdc_wr_n OR NOT scsi_cs,
|
||||
WRn => fdc_wr_n OR NOT scsi_cs,
|
||||
EOPn => '1',
|
||||
DACKn => scsi_dack_n,
|
||||
DRQ => scsi_drq,
|
||||
INT => scsi_int,
|
||||
-- READY =>,
|
||||
-- SCSI bus:
|
||||
DB_INn => SCSI_D,
|
||||
DB_OUTn => scsi_d_out_n,
|
||||
DB_EN => scsi_d_en,
|
||||
DBP_INn => SCSI_PAR,
|
||||
DBP_OUTn => scsi_dbp_out_n,
|
||||
DBP_EN => scsi_dbp_en, -- wenn 1 dann OUTput
|
||||
RST_INn => SCSI_RSTn,
|
||||
RST_OUTn => scsi_rst_out_n,
|
||||
RST_EN => scsi_rst_en,
|
||||
BSY_INn => SCSI_BUSYn,
|
||||
BSY_OUTn => scsi_bsy_out_n,
|
||||
BSY_EN => scsi_bsy_en,
|
||||
SEL_INn => SCSI_SELn,
|
||||
SEL_OUTn => SCSI_SEL_OUTn,
|
||||
SEL_EN => scsi_sel_en,
|
||||
ACK_INn => '1',
|
||||
ACK_OUTn => SCSI_ACKn,
|
||||
-- ACK_EN => ACK_EN,
|
||||
ATN_INn => '1',
|
||||
ATN_OUTn => SCSI_ATNn,
|
||||
-- ATN_EN => ATN_EN,
|
||||
REQ_INn => scsi_drqn,
|
||||
-- REQ_OUTn => REQ_OUTn,
|
||||
-- REQ_EN => REQ_EN,
|
||||
IOn_IN => SCSI_IOn,
|
||||
-- IOn_OUT => IOn_OUT,
|
||||
-- IO_EN => IO_EN,
|
||||
CDn_IN => SCSI_CDn,
|
||||
-- CDn_OUT => CDn_OUT,
|
||||
-- CD_EN => CD_EN,
|
||||
MSG_INn => SCSI_MSGn
|
||||
-- MSG_OUTn => MSG_OUTn,
|
||||
-- MSG_EN => MSG_EN
|
||||
);
|
||||
-- I_SCSI: WF5380_TOP_SOC
|
||||
-- PORT MAP(
|
||||
-- CLK => clk_fdc,
|
||||
-- resetn => reset_n,
|
||||
-- ADR => ca,
|
||||
-- DATA_IN => data_in_fdc_scsi,
|
||||
-- DATA_OUT => data_out_scsi,
|
||||
-- --DATA_EN =>,
|
||||
-- -- Bus and DMA controls:
|
||||
-- CSn => scsi_csn,
|
||||
-- RDn => NOT fdc_wr_n OR NOT scsi_cs,
|
||||
-- WRn => fdc_wr_n OR NOT scsi_cs,
|
||||
-- EOPn => '1',
|
||||
-- DACKn => scsi_dack_n,
|
||||
-- DRQ => scsi_drq,
|
||||
-- INT => scsi_int,
|
||||
-- -- READY =>,
|
||||
-- -- SCSI bus:
|
||||
-- DB_INn => SCSI_D,
|
||||
-- DB_OUTn => scsi_d_out_n,
|
||||
-- DB_EN => scsi_d_en,
|
||||
-- DBP_INn => SCSI_PAR,
|
||||
-- DBP_OUTn => scsi_dbp_out_n,
|
||||
-- DBP_EN => scsi_dbp_en, -- wenn 1 dann OUTput
|
||||
-- RST_INn => SCSI_RSTn,
|
||||
-- RST_OUTn => scsi_rst_out_n,
|
||||
-- RST_EN => scsi_rst_en,
|
||||
-- BSY_INn => SCSI_BUSYn,
|
||||
-- BSY_OUTn => scsi_bsy_out_n,
|
||||
-- BSY_EN => scsi_bsy_en,
|
||||
-- SEL_INn => SCSI_SELn,
|
||||
-- SEL_OUTn => SCSI_SEL_OUTn,
|
||||
-- SEL_EN => scsi_sel_en,
|
||||
-- ACK_INn => '1',
|
||||
-- ACK_OUTn => SCSI_ACKn,
|
||||
-- -- ACK_EN => ACK_EN,
|
||||
-- ATN_INn => '1',
|
||||
-- ATN_OUTn => SCSI_ATNn,
|
||||
-- -- ATN_EN => ATN_EN,
|
||||
-- REQ_INn => scsi_drqn,
|
||||
-- -- REQ_OUTn => REQ_OUTn,
|
||||
-- -- REQ_EN => REQ_EN,
|
||||
-- IOn_IN => SCSI_IOn,
|
||||
-- -- IOn_OUT => IOn_OUT,
|
||||
-- -- IO_EN => IO_EN,
|
||||
-- CDn_IN => SCSI_CDn,
|
||||
-- -- CDn_OUT => CDn_OUT,
|
||||
-- -- CD_EN => CD_EN,
|
||||
-- MSG_INn => SCSI_MSGn
|
||||
-- -- MSG_OUTn => MSG_OUTn,
|
||||
-- -- MSG_EN => MSG_EN
|
||||
-- );
|
||||
--
|
||||
-- I_FDC: WF1772IP_TOP_SOC
|
||||
-- PORT MAP(
|
||||
-- CLK => clk_fdc,
|
||||
-- resetn => reset_n,
|
||||
-- CSn => fdc_cs_n,
|
||||
-- RWn => fdc_wr_n,
|
||||
-- A1 => ca(2),
|
||||
-- A0 => ca(1),
|
||||
-- DATA_IN => data_in_fdc_scsi,
|
||||
-- DATA_OUT => data_out_fdc,
|
||||
-- -- DATA_EN => CD_EN_FDC,
|
||||
-- RDn => FDD_RDn,
|
||||
-- TR00n => FDD_TRACK00,
|
||||
-- IPn => FDD_INDEXn,
|
||||
-- WPRTn => FDD_WPn,
|
||||
-- DDEn => '0', -- Fixed to MFM.
|
||||
-- HDTYPE => hd_dd_out,
|
||||
-- MO => FDD_MOT_ON,
|
||||
-- WG => FDD_WR_GATE,
|
||||
-- WD => FDD_WDn,
|
||||
-- STEP => FDD_STEP,
|
||||
-- DIRC => FDD_STEP_DIR,
|
||||
-- DRQ => drq_fdc,
|
||||
-- INTRQ => fd_int
|
||||
-- );
|
||||
|
||||
I_FDC: WF1772IP_TOP_SOC
|
||||
PORT MAP(
|
||||
CLK => clk_fdc,
|
||||
resetn => reset_n,
|
||||
CSn => fdc_cs_n,
|
||||
RWn => fdc_wr_n,
|
||||
A1 => ca(2),
|
||||
A0 => ca(1),
|
||||
DATA_IN => data_in_fdc_scsi,
|
||||
DATA_OUT => data_out_fdc,
|
||||
-- DATA_EN => CD_EN_FDC,
|
||||
RDn => FDD_RDn,
|
||||
TR00n => FDD_TRACK00,
|
||||
IPn => FDD_INDEXn,
|
||||
WPRTn => FDD_WPn,
|
||||
DDEn => '0', -- Fixed to MFM.
|
||||
HDTYPE => hd_dd_out,
|
||||
MO => FDD_MOT_ON,
|
||||
WG => FDD_WR_GATE,
|
||||
WD => FDD_WDn,
|
||||
STEP => FDD_STEP,
|
||||
DIRC => FDD_STEP_DIR,
|
||||
DRQ => drq_fdc,
|
||||
INTRQ => fd_int
|
||||
);
|
||||
|
||||
I_RTC: RTC
|
||||
PORT MAP(
|
||||
CLK_MAIN => CLK_MAIN,
|
||||
fb_adr => fb_adr(19 DOWNTO 0),
|
||||
FB_CS1n => FB_CSn(1),
|
||||
FB_SIZE0 => FB_SIZE(0),
|
||||
FB_SIZE1 => FB_SIZE(1),
|
||||
FB_WRn => FB_WRn,
|
||||
FB_OEn => FB_OEn,
|
||||
FB_AD_IN => FB_AD(23 DOWNTO 16),
|
||||
FB_AD_OUT => fb_ad_out_rtc,
|
||||
FB_AD_EN_23_16 => fb_ad_en_rtc,
|
||||
PIC_INT => PIC_INT
|
||||
);
|
||||
-- I_RTC: RTC
|
||||
-- PORT MAP(
|
||||
-- CLK_MAIN => CLK_MAIN,
|
||||
-- fb_adr => fb_adr(19 DOWNTO 0),
|
||||
-- FB_CS1n => FB_CSn(1),
|
||||
-- FB_SIZE0 => FB_SIZE(0),
|
||||
-- FB_SIZE1 => FB_SIZE(1),
|
||||
-- FB_WRn => FB_WRn,
|
||||
-- FB_OEn => FB_OEn,
|
||||
-- FB_AD_IN => FB_AD(23 DOWNTO 16),
|
||||
-- FB_AD_OUT => fb_ad_out_rtc,
|
||||
-- FB_AD_EN_23_16 => fb_ad_en_rtc,
|
||||
-- PIC_INT => PIC_INT
|
||||
-- );
|
||||
END ARCHITECTURE;
|
||||
|
||||
|
||||
Reference in New Issue
Block a user