From 0c26287af7b273a9b3d8c53ccb382b326c6f1f41 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Fri, 26 Dec 2014 19:47:22 +0000 Subject: [PATCH] moved logic into process --- vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd | 67 +++++++++++++++++++--------------- 1 file changed, 38 insertions(+), 29 deletions(-) diff --git a/vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd b/vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd index 15b9020..4858569 100644 --- a/vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd +++ b/vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd @@ -183,41 +183,50 @@ ARCHITECTURE BEHAVIOUR of DDR_CTRL IS SIGNAL va_p : unsigned(12 DOWNTO 0); SIGNAL ba_s : unsigned(1 DOWNTO 0) ; SIGNAL ba_p : unsigned(1 DOWNTO 0); -BEGIN - access_width <= long_access WHEN fb_size1 = '0' AND fb_size0 = '0' ELSE - word_access WHEN fb_size1 = '1' AND fb_size0 = '0' ELSE - byte_access WHEN fb_size1 = '0' AND fb_size0 = '1' ELSE - line_access; - - -- Byte selectors: - byte_sel(0) <= '1' WHEN fb_adr(1 DOWNTO 0) = "00" OR - access_width = line_access OR - access_width = long_access - ELSE '0'; - - byte_sel(1) <= '1' WHEN fb_adr(1 DOWNTO 0) = "01" OR - (access_width = word_access AND fb_adr(1) = '0') OR - access_width = line_access OR - access_width = long_access - ELSE '0'; - - byte_sel(2) <= '1' WHEN fb_adr(1 DOWNTO 0) = "10" OR - access_width = line_access OR - access_width = long_access - ELSE '0'; - - byte_sel(3) <= '1' WHEN fb_adr(1 DOWNTO 0) = "11" OR - (access_width = word_access AND fb_adr(1) = '1') OR - access_width = line_access OR - access_width = long_access - ELSE '0'; - +BEGIN --------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------------------------------ ddr_access_cpu READ (REG DDR => ddr_access_cpu) AND WRITE (ddr_access_cpu => REG DDR) --------------------------------------------------------------------- fbctrl_reg : PROCESS + VARIABLE aw : access_width_t; + BEGIN WAIT UNTIL rising_edge(clk_main); + + -- determine access type + CASE std_logic_vector'(fb_size1 & fb_size0) IS + WHEN "00" => aw := long_access; + WHEN "01" => aw := byte_access; + WHEN "10" => aw := word_access; + WHEN OTHERS => aw := line_access; + END CASE; + + -- determine byte selectors + IF fb_adr(1 DOWNTO 0) = "00" OR aw = line_access OR aw = long_access THEN + byte_sel(0) <= '1'; + ELSE + byte_sel(0) <= '0'; + END IF; + + IF fb_adr(1 DOWNTO 0) = "01" OR (aw = word_access AND fb_adr(1) = '0') OR aw = line_access OR aw = long_access THEN + byte_sel(1) <= '1'; + ELSE + byte_sel(1) <= '0'; + END IF; + + IF fb_adr(1 DOWNTO 0) = "10" OR aw = line_access OR aw = long_access THEN + byte_sel(2) <= '1'; + ELSE + byte_sel(2) <= '0'; + END IF; + + IF fb_adr(1 DOWNTO 0) = "11" OR (aw = word_access AND fb_adr(1) = '1') OR aw = line_access OR aw = long_access THEN + byte_sel(3) <= '1'; + ELSE + byte_sel(3) <= '0'; + END IF; + fb_regddr <= fb_regddr_next; + access_width <= aw; END PROCESS FBCTRL_REG; fbctrl_dec : PROCESS(fb_regddr, bus_cyc, ddr_sel, access_width, fb_wr_n, ddr_cs)