From 0801adb0c0b2f047700c61dad765fe9b59d39a4b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Wed, 17 Sep 2014 05:28:16 +0000 Subject: [PATCH] fixed a few MMU quirks --- BaS_gcc/dma/dma.c | 2 +- BaS_gcc/sys/cache.c | 154 +++++++------- BaS_gcc/sys/exceptions.S | 20 +- BaS_gcc/sys/init_fpga.c | 2 +- BaS_gcc/sys/interrupts.c | 442 +++++++++++++++++++-------------------- BaS_gcc/sys/mmu.c | 4 +- 6 files changed, 316 insertions(+), 308 deletions(-) diff --git a/BaS_gcc/dma/dma.c b/BaS_gcc/dma/dma.c index 1f1f62e..9dbbb4c 100644 --- a/BaS_gcc/dma/dma.c +++ b/BaS_gcc/dma/dma.c @@ -39,7 +39,7 @@ #error "unknown machine!" #endif /* MACHINE_FIREBEE */ -#define DBG_DMA +//#define DBG_DMA #ifdef DBG_DMA #define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0) #else diff --git a/BaS_gcc/sys/cache.c b/BaS_gcc/sys/cache.c index fb30a53..673d090 100644 --- a/BaS_gcc/sys/cache.c +++ b/BaS_gcc/sys/cache.c @@ -32,7 +32,7 @@ void cacr_set(uint32_t value) __asm__ __volatile__("movec %0, cacr\n\t" : /* output */ : "r" (rt_cacr) - : /* clobbers */); + : "memory" /* clobbers */); } uint32_t cacr_get(void) @@ -44,35 +44,41 @@ uint32_t cacr_get(void) void disable_data_cache(void) { - flush_and_invalidate_caches(); - cacr_set(cacr_get() | CF_CACR_DCINVA); + flush_and_invalidate_caches(); + cacr_set((cacr_get() | CF_CACR_DCINVA) & ~CF_CACR_DEC); +} + +void disable_instruction_cache(void) +{ + flush_and_invalidate_caches(); + cacr_set((cacr_get() | CF_CACR_ICINVA) & ~CF_CACR_IEC); } void enable_data_cache(void) { - cacr_set(cacr_get() & ~CF_CACR_DCINVA); + cacr_set(cacr_get() & ~CF_CACR_DCINVA); } void flush_and_invalidate_caches(void) { - __asm__ __volatile__( - " clr.l d0 \n\t" - " clr.l d1 \n\t" - " move.l d0,a0 \n\t" - "cfa_setloop: \n\t" - " cpushl bc,(a0) | flush\n\t" - " lea 0x10(a0),a0 | index+1\n\t" - " addq.l #1,d1 | index+1\n\t" - " cmpi.w #512,d1 | all sets?\n\t" - " bne.s cfa_setloop | no->\n\t" - " clr.l d1 \n\t" - " addq.l #1,d0 \n\t" - " move.l d0,a0 \n\t" - " cmpi.w #4,d0 | all ways?\n\t" - " bne.s cfa_setloop | no->\n\t" - /* input */ : - /* output */ : - /* clobber */ : "cc", "d0", "d1", "a0" + __asm__ __volatile__( + " clr.l d0 \n\t" + " clr.l d1 \n\t" + " move.l d0,a0 \n\t" + "cfa_setloop: \n\t" + " cpushl bc,(a0) | flush\n\t" + " lea 0x10(a0),a0 | index+1\n\t" + " addq.l #1,d1 | index+1\n\t" + " cmpi.w #512,d1 | all sets?\n\t" + " bne.s cfa_setloop | no->\n\t" + " clr.l d1 \n\t" + " addq.l #1,d0 \n\t" + " move.l d0,a0 \n\t" + " cmpi.w #4,d0 | all ways?\n\t" + " bne.s cfa_setloop | no->\n\t" + /* input */ : + /* output */ : + /* clobber */ : "cc", "d0", "d1", "a0" ); } @@ -92,35 +98,35 @@ void flush_icache_range(void *address, size_t size) if (start_set > end_set) { /* from the begining to the lowest address */ for (set = 0; set <= end_set; set += (0x10 - 3)) { - __asm__ __volatile__( - " cpushl ic,(%[set]) \n\t" - " addq.l #1,%[set] \n\t" - " cpushl ic,(%[set]) \n\t" - " addq.l #1,%[set] \n\t" - " cpushl ic,(%[set]) \n\t" - " addq.l #1,%[set] \n\t" - " cpushl ic,(%[set]) \n\t" - : /* output parameters */ - : [set] "a" (set) /* input parameters */ - : "cc" /* clobbered registers */ - ); + __asm__ __volatile__( + " cpushl ic,(%[set]) \n\t" + " addq.l #1,%[set] \n\t" + " cpushl ic,(%[set]) \n\t" + " addq.l #1,%[set] \n\t" + " cpushl ic,(%[set]) \n\t" + " addq.l #1,%[set] \n\t" + " cpushl ic,(%[set]) \n\t" + : /* output parameters */ + : [set] "a" (set) /* input parameters */ + : "cc" /* clobbered registers */ + ); } /* next loop will finish the cache ie pass the hole */ end_set = LAST_ICACHE_ADDR; } for (set = start_set; set <= end_set; set += (0x10 - 3)) { - __asm__ __volatile__( - " cpushl ic,(%[set]) \n\t" - " addq.l #1,%[set] \n\t" - " cpushl ic,(%[set]) \n\t" - " addq.l #1,%[set] \n\t" - " cpushl ic,(%[set]) \n\t" - " addq.l #1,%[set] \n\t" - " cpushl ic,(%[set])" - : /* output parameters */ - : [set] "a" (set) - : "cc" - ); + __asm__ __volatile__( + " cpushl ic,(%[set]) \n\t" + " addq.l #1,%[set] \n\t" + " cpushl ic,(%[set]) \n\t" + " addq.l #1,%[set] \n\t" + " cpushl ic,(%[set]) \n\t" + " addq.l #1,%[set] \n\t" + " cpushl ic,(%[set])" + : /* output parameters */ + : [set] "a" (set) + : "cc" + ); } } @@ -142,37 +148,37 @@ void flush_dcache_range(void *address, size_t size) if (start_set > end_set) { /* from the begining to the lowest address */ - for (set = 0; set <= end_set; set += (0x10 - 3)) - { - __asm__ __volatile__( - " cpushl dc,(%[set]) \n\t" - " addq.l #1,%[set] \n\t" - " cpushl dc,(%[set]) \n\t" - " addq.l #1,%[set] \n\t" - " cpushl dc,(%[set]) \n\t" - " addq.l #1,%[set] \n\t" - " cpushl dc,(%[set]) \n\t" - : /* output parameters */ - : [set] "a" (set) - : "cc" /* clobbered registers */ - ); + for (set = 0; set <= end_set; set += (0x10 - 3)) + { + __asm__ __volatile__( + " cpushl dc,(%[set]) \n\t" + " addq.l #1,%[set] \n\t" + " cpushl dc,(%[set]) \n\t" + " addq.l #1,%[set] \n\t" + " cpushl dc,(%[set]) \n\t" + " addq.l #1,%[set] \n\t" + " cpushl dc,(%[set]) \n\t" + : /* output parameters */ + : [set] "a" (set) + : "cc" /* clobbered registers */ + ); } /* next loop will finish the cache ie pass the hole */ end_set = LAST_DCACHE_ADDR; } - for (set = start_set; set <= end_set; set += (0x10 - 3)) - { - __asm__ __volatile__( - " cpushl dc,(%[set]) \n\t" - " addq.l #1,%[set] \n\t" - " cpushl dc,(%[set]) \n\t" - " addq%.l #1,%[set] \n\t" - " cpushl dc,(%[set]) \n\t" - " addq.l #1,%[set] \n\t" - " cpushl dc,(%[set]) \n\t" - : /* output parameters */ - : [set] "a" (set) - : "cc" /* clobbered registers */ - ); + for (set = start_set; set <= end_set; set += (0x10 - 3)) + { + __asm__ __volatile__( + " cpushl dc,(%[set]) \n\t" + " addq.l #1,%[set] \n\t" + " cpushl dc,(%[set]) \n\t" + " addq%.l #1,%[set] \n\t" + " cpushl dc,(%[set]) \n\t" + " addq.l #1,%[set] \n\t" + " cpushl dc,(%[set]) \n\t" + : /* output parameters */ + : [set] "a" (set) + : "cc" /* clobbered registers */ + ); } } diff --git a/BaS_gcc/sys/exceptions.S b/BaS_gcc/sys/exceptions.S index f7df27c..95e3e33 100644 --- a/BaS_gcc/sys/exceptions.S +++ b/BaS_gcc/sys/exceptions.S @@ -758,15 +758,17 @@ irq7: /* - * general purpose timer 0 (GPT0): video change, later also others. GPT0 is used as - * input trigger. It is connected to the TIN0 signal of the FPGA and triggers everytime - * vbasehi is written to, i.e. when the video base address gets changed + * general purpose timer 0 (GPT0): video change, later also others. + * + * GPT0 is used as input trigger. It is connected to the TIN0 signal of + * the FPGA and triggers everytime vbasehi is written to, i.e. + * when the video base address gets changed */ handler_gpt0: move #0x2700,sr // disable interrupts - lea -28(a7),a7 // save registers - movem.l d0-d4/a0-a1,(a7) + lea -7 * 4(sp),sp // save registers + movem.l d0-d4/a0-a1,(sp) mvz.b vbasehi,d0 // screen base address high cmp.w #2,d0 // screen base lower than 0x20000? @@ -779,7 +781,7 @@ handler_gpt0: move.l (a0),_video_sbt // save time // FIXME: don't we need to get out here? - bra video_chg_end + // bra video_chg_end sca_other: lsl.l #8,d0 // build new screen start address from Atari register contents @@ -840,7 +842,7 @@ video_chg_2page: mvz.w 0xffff82a8,d1 // VDB: vertical display begin sub.l d1,d2 // number of lines mulu d2,d4 // times number of words per line - add.l d4,d0 // video gr�sse + add.l d4,d0 // video memory end address cmp.l #__STRAM_END,d0 // start address > end of STRAM? bge video_chg_end // yes - we're finished @@ -853,8 +855,8 @@ video_chg_2page: jsr _flush_and_invalidate_caches video_chg_end: - lea MCF_GPT0_GMS,a0 // clear interrupt - bclr.b #0,3(a0) + lea MCF_GPT0_GMS,a0 // disable and reenable timer + bclr.b #0,3(a0) // input capture nop bset.b #0,3(a0) diff --git a/BaS_gcc/sys/init_fpga.c b/BaS_gcc/sys/init_fpga.c index 0216ffb..b7c785b 100644 --- a/BaS_gcc/sys/init_fpga.c +++ b/BaS_gcc/sys/init_fpga.c @@ -27,7 +27,7 @@ #include "bas_printf.h" #include "wait.h" -#define FPGA_DEBUG +// #define FPGA_DEBUG #if defined(FPGA_DEBUG) #define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0) #else diff --git a/BaS_gcc/sys/interrupts.c b/BaS_gcc/sys/interrupts.c index 0d502d8..dbfe1b3 100644 --- a/BaS_gcc/sys/interrupts.c +++ b/BaS_gcc/sys/interrupts.c @@ -38,7 +38,7 @@ extern void (*rt_vbr[])(void); #define VBR rt_vbr -#define IRQ_DEBUG +//#define IRQ_DEBUG #if defined(IRQ_DEBUG) #define dbg(format, arg...) do { xprintf("DEBUG %s(): " format, __FUNCTION__, ##arg); } while (0) #else @@ -51,45 +51,45 @@ extern void (*rt_vbr[])(void); */ int register_interrupt_handler(uint8_t source, uint8_t level, uint8_t priority, uint8_t intr, void (*handler)(void)) { - int ipl; - int i; - volatile uint8_t *ICR = &MCF_INTC_ICR01 - 1; - uint8_t lp; + int ipl; + int i; + volatile uint8_t *ICR = &MCF_INTC_ICR01 - 1; + uint8_t lp; - source &= 63; - priority &= 7; + source &= 63; + priority &= 7; - if (source < 1 || source > 63) - { - dbg("interrupt source %d not defined\r\n", source); - return -1; - } + if (source < 1 || source > 63) + { + dbg("interrupt source %d not defined\r\n", source); + return -1; + } - lp = MCF_INTC_ICR_IL(level) | MCF_INTC_ICR_IP(priority); + lp = MCF_INTC_ICR_IL(level) | MCF_INTC_ICR_IP(priority); - /* check if this combination is already set somewhere */ - for (i = 1; i < 64; i++) - { - if (ICR[i] == lp) - { - dbg("level %d and priority %d already used for interrupt source %d!\r\n", - level, priority, i); - return -1; - } - } + /* check if this combination is already set somewhere */ + for (i = 1; i < 64; i++) + { + if (ICR[i] == lp) + { + dbg("level %d and priority %d already used for interrupt source %d!\r\n", + level, priority, i); + return -1; + } + } - /* disable interrupts */ - ipl = set_ipl(7); + /* disable interrupts */ + ipl = set_ipl(7); - VBR[64 + source] = handler; /* first 64 vectors are system exceptions */ + VBR[64 + source] = handler; /* first 64 vectors are system exceptions */ - /* set level and priority in interrupt controller */ - ICR[source] = lp; + /* set level and priority in interrupt controller */ + ICR[source] = lp; - /* set interrupt mask to where it was before */ - set_ipl(ipl); + /* set interrupt mask to where it was before */ + set_ipl(ipl); - return 0; + return 0; } #ifndef MAX_ISR_ENTRY @@ -99,10 +99,10 @@ int register_interrupt_handler(uint8_t source, uint8_t level, uint8_t priority, struct isrentry { - int vector; - int (*handler)(void *, void *); - void *hdev; - void *harg; + int vector; + int (*handler)(void *, void *); + void *hdev; + void *harg; }; static struct isrentry isrtab[MAX_ISR_ENTRY]; /* list of interrupt service routines */ @@ -112,7 +112,7 @@ static struct isrentry isrtab[MAX_ISR_ENTRY]; /* list of interrupt service */ void isr_init(void) { - memset(isrtab, 0, sizeof(isrtab)); + memset(isrtab, 0, sizeof(isrtab)); } /* @@ -125,56 +125,56 @@ void isr_init(void) */ int isr_register_handler(int vector, int (*handler)(void *, void *), void *hdev, void *harg) { - int index; + int index; - if ((vector == 0) || (handler == NULL)) - { - dbg("illegal vector or handler!\r\n"); - return false; - } + if ((vector == 0) || (handler == NULL)) + { + dbg("illegal vector or handler!\r\n"); + return false; + } - for (index = 0; index < MAX_ISR_ENTRY; index++) - { - if (isrtab[index].vector == vector) - { - /* one cross each, only! */ - dbg("already set handler with this vector (%d, %d)\r\n", vector); - return false; - } + for (index = 0; index < MAX_ISR_ENTRY; index++) + { + if (isrtab[index].vector == vector) + { + /* one cross each, only! */ + dbg("already set handler with this vector (%d, %d)\r\n", vector); + return false; + } - if (isrtab[index].vector == 0) - { - isrtab[index].vector = vector; - isrtab[index].handler = handler; - isrtab[index].hdev = hdev; - isrtab[index].harg = harg; + if (isrtab[index].vector == 0) + { + isrtab[index].vector = vector; + isrtab[index].handler = handler; + isrtab[index].hdev = hdev; + isrtab[index].harg = harg; - return true; - } - } - dbg("no available slots to register handler for vector %d\n\r", vector); + return true; + } + } + dbg("no available slots to register handler for vector %d\n\r", vector); - return false; /* no available slots */ + return false; /* no available slots */ } void isr_remove_handler(int (*handler)(void *, void *)) { - /* - * This routine removes from the ISR table all - * entries that matches 'handler'. - */ - int index; + /* + * This routine removes from the ISR table all + * entries that matches 'handler'. + */ + int index; - for (index = 0; index < MAX_ISR_ENTRY; index++) - { - if (isrtab[index].handler == handler) - { - memset(&isrtab[index], 0, sizeof(struct isrentry)); + for (index = 0; index < MAX_ISR_ENTRY; index++) + { + if (isrtab[index].handler == handler) + { + memset(&isrtab[index], 0, sizeof(struct isrentry)); - return; - } - } - dbg("no such handler registered (handler=%p\r\n", handler); + return; + } + } + dbg("no such handler registered (handler=%p\r\n", handler); } /* @@ -183,27 +183,27 @@ void isr_remove_handler(int (*handler)(void *, void *)) */ bool isr_execute_handler(int vector) { - int index; - bool retval = false; + int index; + bool retval = false; - /* - * locate a BaS Interrupt Service Routine handler. - */ - for (index = 0; index < MAX_ISR_ENTRY; index++) - { - if (isrtab[index].vector == vector) - { - retval = true; + /* + * locate a BaS Interrupt Service Routine handler. + */ + for (index = 0; index < MAX_ISR_ENTRY; index++) + { + if (isrtab[index].vector == vector) + { + retval = true; - if (isrtab[index].handler(isrtab[index].hdev, isrtab[index].harg)) - { - return retval; - } - } - } - dbg("no BaS isr handler for vector %d found\r\n", vector); + if (isrtab[index].handler(isrtab[index].hdev, isrtab[index].harg)) + { + return retval; + } + } + } + dbg("no BaS isr handler for vector %d found\r\n", vector); - return retval; + return retval; } /* @@ -211,24 +211,24 @@ bool isr_execute_handler(int vector) */ int pic_interrupt_handler(void *arg1, void *arg2) { - uint8_t rcv_byte; + uint8_t rcv_byte; - rcv_byte = MCF_PSC3_PSCRB_8BIT; - if (rcv_byte == 2) // PIC requests RTC data - { - uint8_t *rtc_reg = (uint8_t *) 0xffff8961; - uint8_t *rtc_data = (uint8_t *) 0xffff8963; - int index = 0; + rcv_byte = MCF_PSC3_PSCRB_8BIT; + if (rcv_byte == 2) // PIC requests RTC data + { + uint8_t *rtc_reg = (uint8_t *) 0xffff8961; + uint8_t *rtc_data = (uint8_t *) 0xffff8963; + int index = 0; - xprintf("PIC interrupt requesting RTC data\r\n"); + xprintf("PIC interrupt requesting RTC data\r\n"); - MCF_PSC3_PSCTB_8BIT = 0x82; // header byte to PIC - do - { - *rtc_reg = 0; - MCF_PSC3_PSCTB_8BIT = *rtc_data; - } while (index++ < 64); - } + MCF_PSC3_PSCTB_8BIT = 0x82; // header byte to PIC + do + { + *rtc_reg = 0; + MCF_PSC3_PSCTB_8BIT = *rtc_data; + } while (index++ < 64); + } return 1; } @@ -237,93 +237,93 @@ extern int32_t video_tlb; void video_addr_timeout(void) { - uint32_t addr = 0x0L; - uint32_t *src; - uint32_t *dst; - uint32_t asid; + uint32_t addr = 0x0L; + uint32_t *src; + uint32_t *dst; + uint32_t asid; - dbg("video address timeout\r\n"); - flush_and_invalidate_caches(); + dbg("video address timeout\r\n"); + flush_and_invalidate_caches(); - do - { - uint32_t tlb; - uint32_t page_attr; + do + { + uint32_t tlb; + uint32_t page_attr; - /* - * search tlb entry id for addr (if not available, the MMU - * will provide a new one based on its LRU algorithm) - */ - MCF_MMU_MMUAR = addr; - MCF_MMU_MMUOR = - MCF_MMU_MMUOR_STLB | - MCF_MMU_MMUOR_RW | - MCF_MMU_MMUOR_ACC; - NOP(); - tlb = (MCF_MMU_MMUOR >> 16) & 0xffff; + /* + * search tlb entry id for addr (if not available, the MMU + * will provide a new one based on its LRU algorithm) + */ + MCF_MMU_MMUAR = addr; + MCF_MMU_MMUOR = + MCF_MMU_MMUOR_STLB | + MCF_MMU_MMUOR_RW | + MCF_MMU_MMUOR_ACC; + NOP(); + tlb = (MCF_MMU_MMUOR >> 16) & 0xffff; - /* - * retrieve tlb entry with the found TLB entry id - */ - MCF_MMU_MMUAR = tlb; - MCF_MMU_MMUOR = - MCF_MMU_MMUOR_STLB | - MCF_MMU_MMUOR_ADR | - MCF_MMU_MMUOR_RW | - MCF_MMU_MMUOR_ACC; - NOP(); + /* + * retrieve tlb entry with the found TLB entry id + */ + MCF_MMU_MMUAR = tlb; + MCF_MMU_MMUOR = + MCF_MMU_MMUOR_STLB | + MCF_MMU_MMUOR_ADR | + MCF_MMU_MMUOR_RW | + MCF_MMU_MMUOR_ACC; + NOP(); - asid = (MCF_MMU_MMUTR >> 2) & 0x1fff; /* fetch ASID of page */; - if (asid != sca_page_ID) /* check if screen area */ - { - addr += 0x100000; - continue; /* next page */ - } + asid = (MCF_MMU_MMUTR >> 2) & 0x1fff; /* fetch ASID of page */; + if (asid != sca_page_ID) /* check if screen area */ + { + addr += 0x100000; + continue; /* next page */ + } - /* modify found TLB entry */ - if (addr == 0x0) - { - page_attr = - MCF_MMU_MMUDR_LK | - MCF_MMU_MMUDR_SZ(0) | - MCF_MMU_MMUDR_CM(0) | - MCF_MMU_MMUDR_R | - MCF_MMU_MMUDR_W | - MCF_MMU_MMUDR_X; - } - else - { - page_attr = - MCF_MMU_MMUTR_SG | - MCF_MMU_MMUTR_V; - } + /* modify found TLB entry */ + if (addr == 0x0) + { + page_attr = + MCF_MMU_MMUDR_LK | + MCF_MMU_MMUDR_SZ(0) | + MCF_MMU_MMUDR_CM(0) | + MCF_MMU_MMUDR_R | + MCF_MMU_MMUDR_W | + MCF_MMU_MMUDR_X; + } + else + { + page_attr = + MCF_MMU_MMUTR_SG | + MCF_MMU_MMUTR_V; + } - MCF_MMU_MMUTR = addr; - MCF_MMU_MMUDR = page_attr; - MCF_MMU_MMUOR = - MCF_MMU_MMUOR_STLB | - MCF_MMU_MMUOR_ADR | - MCF_MMU_MMUOR_ACC | - MCF_MMU_MMUOR_UAA; - NOP(); + MCF_MMU_MMUTR = addr; + MCF_MMU_MMUDR = page_attr; + MCF_MMU_MMUOR = + MCF_MMU_MMUOR_STLB | + MCF_MMU_MMUOR_ADR | + MCF_MMU_MMUOR_ACC | + MCF_MMU_MMUOR_UAA; + NOP(); - dst = (uint32_t *) 0x60000000 + addr; - src = (uint32_t *) addr; - while (dst < (uint32_t *) 0x60000000 + addr + 0x10000) - { - *dst++ = *src++; - *dst++ = *src++; - *dst++ = *src++; - *dst++ = *src++; - } + dst = (uint32_t *) 0x60000000 + addr; + src = (uint32_t *) addr; + while (dst < (uint32_t *) 0x60000000 + addr + 0x10000) + { + *dst++ = *src++; + *dst++ = *src++; + *dst++ = *src++; + *dst++ = *src++; + } - addr += 0x100000; - } while (addr < 0xd00000); - video_tlb = 0x2000; - video_sbt = 0; + addr += 0x100000; + } while (addr < 0xd00000); + video_tlb = 0x2000; + video_sbt = 0; } @@ -332,16 +332,16 @@ void video_addr_timeout(void) */ void blink_led(void) { - static uint16_t blinker = 0; + static uint16_t blinker = 0; - if ((blinker++ & 0x80) > 0) - { - MCF_GPIO_PODR_FEC1L |= (1 << 4); /* LED off */ - } - else - { - MCF_GPIO_PODR_FEC1L &= ~(1 << 4); /* LED on */ - } + if ((blinker++ & 0x80) > 0) + { + MCF_GPIO_PODR_FEC1L |= (1 << 4); /* LED off */ + } + else + { + MCF_GPIO_PODR_FEC1L &= ~(1 << 4); /* LED on */ + } } /* @@ -359,45 +359,45 @@ void blink_led(void) bool irq6_acsi_dma_interrupt(void) { - dbg("ACSI DMA interrupt\r\n"); + dbg("ACSI DMA interrupt\r\n"); - /* - * TODO: implement handler - */ + /* + * TODO: implement handler + */ - return false; + return false; } bool irq6_interrupt_handler(uint32_t sf1, uint32_t sf2) { - bool handled = false; + bool handled = false; - MCF_EPORT_EPFR |= (1 << 6); /* clear int6 from edge port */ + MCF_EPORT_EPFR |= (1 << 6); /* clear int6 from edge port */ - if (video_sbt != 0 && (video_sbt - 0x70000000) > MCF_SLT0_SCNT) - { - video_addr_timeout(); - handled = true; - } + if (video_sbt != 0 && (video_sbt - 0x70000000) > MCF_SLT0_SCNT) + { + video_addr_timeout(); + handled = true; + } - /* - * check if ACSI DMA interrupt - */ + /* + * check if ACSI DMA interrupt + */ - if (FALCON_MFP_IERA & (1 << 7)) - { - /* ACSI interrupt is enabled */ - if (FALCON_MFP_IPRA & (1 << 7)) - { - irq6_acsi_dma_interrupt(); - handled = true; - } - } + if (FALCON_MFP_IERA & (1 << 7)) + { + /* ACSI interrupt is enabled */ + if (FALCON_MFP_IPRA & (1 << 7)) + { + irq6_acsi_dma_interrupt(); + handled = true; + } + } - if (FALCON_MFP_IPRA || FALCON_MFP_IPRB) - { - blink_led(); - } + if (FALCON_MFP_IPRA || FALCON_MFP_IPRB) + { + blink_led(); + } - return handled; + return handled; } diff --git a/BaS_gcc/sys/mmu.c b/BaS_gcc/sys/mmu.c index 8ef1305..6a96c9b 100644 --- a/BaS_gcc/sys/mmu.c +++ b/BaS_gcc/sys/mmu.c @@ -62,7 +62,7 @@ #error "unknown machine!" #endif /* MACHINE_FIREBEE */ -#define DEBUG_MMU +// #define DEBUG_MMU #ifdef DEBUG_MMU #define dbg(format, arg...) do { xprintf("DEBUG (%s()): " format, __FUNCTION__, ##arg);} while(0) #else @@ -377,7 +377,7 @@ void mmu_init(void) * Map (locked) the second last MB of physical SDRAM (this is where BaS .data and .bss reside) to the same * virtual address. This is also used (completely) when BaS is in RAM */ - flags.cache_mode = CACHE_WRITETHROUGH; + flags.cache_mode = CACHE_COPYBACK; flags.access = ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE; mmu_map_page(SDRAM_START + SDRAM_SIZE - 0X00200000, SDRAM_START + SDRAM_SIZE - 0X00200000, MMU_PAGE_SIZE_1M, &flags);