got rid of BIT signal types

vhdl/rtl/vhdl/WF_FDC1772_IP/wf1772ip_crc_logic.vhd

@@ -96,8 +96,8 @@ entity WF1772IP_CRC_LOGIC is
 		-- Preset controls:
 		DDEn		: in std_logic;
 		ID_AM		: in std_logic;
-		DATA_AM		: in Bit;
-		DDATA_AM	: in Bit;
+		DATA_AM		: in STD_LOGIC;
+		DDATA_AM	: in STD_LOGIC;
 		
 		-- CRC unit:
 		SD			: in std_logic; -- Serial data input.

vhdl/rtl/vhdl/WF_FDC1772_IP/wf1772ip_top_soc.vhd

@@ -311,8 +311,8 @@ begin
 			DDEn			=> DDEn,
 			HDTYPE 			=> HDTYPE,
 			ID_AM			=> ID_AM_I,
-			DATA_AM			=> DATA_AM_I,
-			DDATA_AM		=> DDATA_AM_I,
+			DATA_AM			=> STD_LOGIC(DATA_AM_I),
+			DDATA_AM		=> STD_LOGIC(DDATA_AM_I),
 			SHFT_LOAD_SD	=> SHFT_LOAD_SD_I,
 			DR				=> DR_I,
 			PRECOMP_EN		=> PRECOMP_EN_I,

vhdl/rtl/vhdl/WF_FDC1772_IP/wf1772ip_transceiver.vhd

@@ -77,8 +77,8 @@ entity WF1772IP_TRANSCEIVER is
 		HDTYPE			: in std_logic; -- Floppy type HD or DD.
 		DDEn			: in std_logic; -- Double density select (FM or MFM).
 		ID_AM			: in std_logic; -- ID addressmark strobe.
-		DATA_AM			: in Bit; -- Data addressmark strobe.
-		DDATA_AM		: in Bit; -- Deleted data addressmark strobe.
+		DATA_AM			: in STD_LOGIC; -- Data addressmark strobe.
+		DDATA_AM		: in STD_LOGIC; -- Deleted data addressmark strobe.
 		SHFT_LOAD_SD	: in std_logic; -- Indication for shift register load time.
 		DR				: in std_logic_vector(7 downto 0); -- Content of the data register.