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got rid of BIT signal types

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This commit is contained in:
Markus Fröschle
2014-12-24 17:07:51 +00:00
parent 5a923ddada
commit 06688a9a02
3 changed files with 6 additions and 6 deletions
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4
vhdl/rtl/vhdl/WF_FDC1772_IP/wf1772ip_crc_logic.vhd
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@@ -96,8 +96,8 @@ entity WF1772IP_CRC_LOGIC is
-- Preset controls: -- Preset controls:
DDEn : in std_logic; DDEn : in std_logic;
ID_AM : in std_logic; ID_AM : in std_logic;
DATA_AM : in Bit; DATA_AM : in STD_LOGIC;
DDATA_AM : in Bit; DDATA_AM : in STD_LOGIC;
-- CRC unit: -- CRC unit:
SD : in std_logic; -- Serial data input. SD : in std_logic; -- Serial data input.

4
vhdl/rtl/vhdl/WF_FDC1772_IP/wf1772ip_top_soc.vhd
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@@ -311,8 +311,8 @@ begin
DDEn => DDEn, DDEn => DDEn,
HDTYPE => HDTYPE, HDTYPE => HDTYPE,
ID_AM => ID_AM_I, ID_AM => ID_AM_I,
DATA_AM => DATA_AM_I, DATA_AM => STD_LOGIC(DATA_AM_I),
DDATA_AM => DDATA_AM_I, DDATA_AM => STD_LOGIC(DDATA_AM_I),
SHFT_LOAD_SD => SHFT_LOAD_SD_I, SHFT_LOAD_SD => SHFT_LOAD_SD_I,
DR => DR_I, DR => DR_I,
PRECOMP_EN => PRECOMP_EN_I, PRECOMP_EN => PRECOMP_EN_I,

4
vhdl/rtl/vhdl/WF_FDC1772_IP/wf1772ip_transceiver.vhd
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@@ -77,8 +77,8 @@ entity WF1772IP_TRANSCEIVER is
HDTYPE : in std_logic; -- Floppy type HD or DD. HDTYPE : in std_logic; -- Floppy type HD or DD.
DDEn : in std_logic; -- Double density select (FM or MFM). DDEn : in std_logic; -- Double density select (FM or MFM).
ID_AM : in std_logic; -- ID addressmark strobe. ID_AM : in std_logic; -- ID addressmark strobe.
DATA_AM : in Bit; -- Data addressmark strobe. DATA_AM : in STD_LOGIC; -- Data addressmark strobe.
DDATA_AM : in Bit; -- Deleted data addressmark strobe. DDATA_AM : in STD_LOGIC; -- Deleted data addressmark strobe.
SHFT_LOAD_SD : in std_logic; -- Indication for shift register load time. SHFT_LOAD_SD : in std_logic; -- Indication for shift register load time.
DR : in std_logic_vector(7 downto 0); -- Content of the data register. DR : in std_logic_vector(7 downto 0); -- Content of the data register.