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improved timing, added timing constraints, got rid of CLK_33M

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Design compiles and runs, but still has issues with different screen resolutions and video clocks
This commit is contained in:
Markus Fröschle
2015-09-23 09:49:05 +00:00
parent ca251a2cf1
commit 03a110f03b
19 changed files with 1631 additions and 1519 deletions
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200
altpll1.bsf
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@@ -1,100 +1,100 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 328 216)
(text "altpll1" (rect 144 1 191 20)(font "Arial" (font_size 10)))
(text "inst" (rect 8 197 31 212)(font "Arial" ))
(port
(pt 0 72)
(input)
(text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8)))
(text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 48 72)(line_width 1))
)
(port
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(text "inclk0 frequency: 33.000 MHz" (rect 58 67 201 81)(font "Arial" ))
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(text "Ratio" (rect 90 111 114 125)(font "Arial" ))
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2014 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
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(text "altpll1" (rect 119 0 160 16)(font "Arial" (font_size 10)))
(text "inst" (rect 8 161 26 172)(font "Arial" ))
(port
(pt 0 64)
(input)
(text "inclk0" (rect 0 0 34 13)(font "Arial" (font_size 8)))
(text "inclk0" (rect 4 51 31 63)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 40 64))
)
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)
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(output)
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)
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(text "Operation Mode: Src Sync Comp" (rect 50 72 239 154)(font "Arial" ))
(text "Clk " (rect 51 91 117 192)(font "Arial" ))
(text "Ratio" (rect 82 91 187 192)(font "Arial" ))
(text "Ph (dg)" (rect 119 91 269 192)(font "Arial" ))
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