787 lines
30 KiB
Plaintext
787 lines
30 KiB
Plaintext
TITLE "VIDEO MODUSE UND CLUT CONTROL";
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-- CREATED BY FREDI ASCHWANDEN
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INCLUDE "lpm_bustri_WORD.inc";
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INCLUDE "lpm_bustri_BYT.inc";
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-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
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-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
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SUBDESIGN video_mod_mux_clutctr
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(
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-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
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nRSTO : INPUT;
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MAIN_CLK : INPUT;
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nFB_CS1 : INPUT;
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nFB_CS2 : INPUT;
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nFB_CS3 : INPUT;
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nFB_WR : INPUT;
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nFB_OE : INPUT;
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FB_SIZE0 : INPUT;
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FB_SIZE1 : INPUT;
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nFB_BURST : INPUT;
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FB_ADR[31..0] : INPUT;
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CLK33M : INPUT;
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CLK25M : INPUT;
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BLITTER_RUN : INPUT;
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CLK_VIDEO : INPUT;
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VR_D[8..0] : INPUT;
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VR_BUSY : INPUT;
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COLOR8 : OUTPUT;
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ACP_CLUT_RD : OUTPUT;
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COLOR1 : OUTPUT;
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FALCON_CLUT_RDH : OUTPUT;
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FALCON_CLUT_RDL : OUTPUT;
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FALCON_CLUT_WR[3..0] : OUTPUT;
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ST_CLUT_RD : OUTPUT;
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ST_CLUT_WR[1..0] : OUTPUT;
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CLUT_MUX_ADR[3..0] : OUTPUT;
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HSYNC : OUTPUT;
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VSYNC : OUTPUT;
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nBLANK : OUTPUT;
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nSYNC : OUTPUT;
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nPD_VGA : OUTPUT;
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FIFO_RDE : OUTPUT;
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COLOR2 : OUTPUT;
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COLOR4 : OUTPUT;
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PIXEL_CLK : OUTPUT;
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CLUT_OFF[3..0] : OUTPUT;
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BLITTER_ON : OUTPUT;
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VIDEO_RAM_CTR[15..0] : OUTPUT;
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VIDEO_MOD_TA : OUTPUT;
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BORDER_COLOR[23..0] : OUTPUT;
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CCSEL[2..0] : OUTPUT;
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ACP_CLUT_WR[3..0] : OUTPUT;
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INTER_ZEI : OUTPUT;
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DOP_FIFO_CLR : OUTPUT;
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VIDEO_RECONFIG : OUTPUT;
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VR_WR : OUTPUT;
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VR_RD : OUTPUT;
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CLR_FIFO : OUTPUT;
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FB_AD[31..0] : BIDIR;
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-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
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)
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VARIABLE
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CLK17M :DFF;
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CLK13M :DFF;
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ACP_CLUT_CS :NODE;
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ACP_CLUT :NODE;
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VIDEO_PLL_CONFIG_CS :NODE;
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VR_WR :DFF;
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VR_DOUT[8..0] :DFFE;
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VR_FRQ[7..0] :DFFE;
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VIDEO_PLL_RECONFIG_CS :NODE;
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VIDEO_RECONFIG :DFF;
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FALCON_CLUT_CS :NODE;
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FALCON_CLUT :NODE;
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ST_CLUT_CS :NODE;
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ST_CLUT :NODE;
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FB_B[3..0] :NODE;
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FB_16B[1..0] :NODE;
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ST_SHIFT_MODE[1..0] :DFFE;
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ST_SHIFT_MODE_CS :NODE;
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FALCON_SHIFT_MODE[10..0] :DFFE;
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FALCON_SHIFT_MODE_CS :NODE;
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CLUT_MUX_ADR[3..0] :DFF;
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CLUT_MUX_AV[1..0][3..0] :DFF;
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ACP_VCTR_CS :NODE;
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ACP_VCTR[31..0] :DFFE;
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BORDER_COLOR_CS :NODE;
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BORDER_COLOR[23..0] :DFFE;
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ACP_VIDEO_ON :NODE;
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SYS_CTR[6..0] :DFFE;
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SYS_CTR_CS :NODE;
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LOF[15..0] :DFFE;
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LOF_CS :NODE;
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LWD[15..0] :DFFE;
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LWD_CS :NODE;
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-- DIV. CONTROL REGISTER
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CLUT_TA :DFF; -- BRAUCHT EIN WAITSTAT
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HSYNC :DFF;
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HSYNC_I[7..0] :DFF;
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HSY_LEN[7..0] :DFF; -- LÄNGE HSYNC PULS IN PIXEL_CLK
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HSYNC_START :DFF;
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LAST :DFF; -- LETZTES PIXEL EINER ZEILE ERREICHT
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VSYNC :DFF;
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VSYNC_START :DFFE;
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VSYNC_I[2..0] :DFFE;
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nBLANK :DFF;
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DISP_ON :DFF;
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DPO_ZL :DFFE;
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DPO_ON :DFF;
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DPO_OFF :DFF;
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VDTRON :DFF;
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VCO_ZL :DFFE;
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VCO_ON :DFF;
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VCO_OFF :DFF;
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VHCNT[11..0] :DFF;
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SUB_PIXEL_CNT[6..0] :DFFE;
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VVCNT[10..0] :DFFE;
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VERZ[2..0][9..0] :DFF;
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RAND[6..0] :DFF;
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RAND_ON :NODE;
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FIFO_RDE :DFF;
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CLR_FIFO :DFFE;
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START_ZEILE :DFFE;
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SYNC_PIX :DFF;
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SYNC_PIX1 :DFF;
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SYNC_PIX2 :DFF;
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CCSEL[2..0] :DFF;
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COLOR16 :NODE;
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COLOR24 :NODE;
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-- ATARI RESOLUTION
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ATARI_SYNC :NODE;
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ATARI_HH[31..0] :DFFE; -- HORIZONTAL TIMING 640x480
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ATARI_HH_CS :NODE;
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ATARI_VH[31..0] :DFFE; -- VERTIKAL TIMING 640x480
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ATARI_VH_CS :NODE;
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ATARI_HL[31..0] :DFFE; -- HORIZONTAL TIMING 320x240
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ATARI_HL_CS :NODE;
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ATARI_VL[31..0] :DFFE; -- VERTIKAL TIMING 320x240
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ATARI_VL_CS :NODE;
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-- HORIZONTAL
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RAND_LINKS[11..0] :NODE;
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HDIS_START[11..0] :NODE;
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HDIS_END[11..0] :NODE;
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RAND_RECHTS[11..0] :NODE;
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HS_START[11..0] :NODE;
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H_TOTAL[11..0] :NODE;
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HDIS_LEN[11..0] :NODE;
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MULF[5..0] :NODE;
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HHT[11..0] :DFFE;
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HHT_CS :NODE;
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HBE[11..0] :DFFE;
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HBE_CS :NODE;
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HDB[11..0] :DFFE;
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HDB_CS :NODE;
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HDE[11..0] :DFFE;
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HDE_CS :NODE;
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HBB[11..0] :DFFE;
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HBB_CS :NODE;
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HSS[11..0] :DFFE;
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HSS_CS :NODE;
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-- VERTIKAL
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RAND_OBEN[10..0] :NODE;
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VDIS_START[10..0] :NODE;
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VDIS_END[10..0] :NODE;
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RAND_UNTEN[10..0] :NODE;
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VS_START[10..0] :NODE;
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V_TOTAL[10..0] :NODE;
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FALCON_VIDEO :NODE;
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ST_VIDEO :NODE;
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INTER_ZEI :DFF;
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DOP_ZEI :DFF;
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DOP_FIFO_CLR :DFF;
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VBE[10..0] :DFFE;
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VBE_CS :NODE;
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VDB[10..0] :DFFE;
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VDB_CS :NODE;
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VDE[10..0] :DFFE;
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VDE_CS :NODE;
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VBB[10..0] :DFFE;
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VBB_CS :NODE;
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VSS[10..0] :DFFE;
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VSS_CS :NODE;
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VFT[10..0] :DFFE;
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VFT_CS :NODE;
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VCO[8..0] :DFFE;
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VCO_CS :NODE;
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VCNTRL[3..0] :DFFE;
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VCNTRL_CS :NODE;
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BEGIN
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-- BYT SELECT 32 BIT
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FB_B0 = FB_ADR[1..0] == 0; -- ADR==0
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FB_B1 = FB_ADR[1..0] == 1 -- ADR==1
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# FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HIGH WORD
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# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
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FB_B2 = FB_ADR[1..0] == 2 -- ADR==2
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# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
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FB_B3 = FB_ADR[1..0] == 3 -- ADR==3
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# FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD
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# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
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-- BYT SELECT 16 BIT
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FB_16B0 = FB_ADR[0] == 0; -- ADR==0
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FB_16B1 = FB_ADR[0] == 1 -- ADR==1
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# !(!FB_SIZE1 & FB_SIZE0); -- NOT BYT
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-- ACP CLUT --
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ACP_CLUT_CS = !nFB_CS2 & FB_ADR[27..10] == H"0"; -- 0-3FF/1024
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ACP_CLUT_RD = ACP_CLUT_CS & !nFB_OE;
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ACP_CLUT_WR[] = FB_B[] & ACP_CLUT_CS & !nFB_WR;
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CLUT_TA.CLK = MAIN_CLK;
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CLUT_TA = (ACP_CLUT_CS # FALCON_CLUT_CS # ST_CLUT_CS) & !VIDEO_MOD_TA;
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--FALCON CLUT --
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FALCON_CLUT_CS = !nFB_CS1 & FB_ADR[19..10] == H"3E6"; -- $F9800/$400
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FALCON_CLUT_RDH = FALCON_CLUT_CS & !nFB_OE & !FB_ADR1; -- HIGH WORD
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FALCON_CLUT_RDL = FALCON_CLUT_CS & !nFB_OE & FB_ADR1; -- LOW WORD
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FALCON_CLUT_WR[1..0] = FB_16B[] & !FB_ADR1 & FALCON_CLUT_CS & !nFB_WR;
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FALCON_CLUT_WR[3..2] = FB_16B[] & FB_ADR1 & FALCON_CLUT_CS & !nFB_WR;
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-- ST CLUT --
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ST_CLUT_CS = !nFB_CS1 & FB_ADR[19..5] == H"7C12"; -- $F8240/$20
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ST_CLUT_RD = ST_CLUT_CS & !nFB_OE;
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ST_CLUT_WR[] = FB_16B[] & ST_CLUT_CS & !nFB_WR;
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-- ST SHIFT MODE
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ST_SHIFT_MODE[].CLK = MAIN_CLK;
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ST_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C130"; -- $F8260/2
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ST_SHIFT_MODE[] = FB_AD[25..24];
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ST_SHIFT_MODE[].ENA = ST_SHIFT_MODE_CS & !nFB_WR & FB_B0;
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COLOR1 = ST_SHIFT_MODE[] == B"10" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- MONO
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COLOR2 = ST_SHIFT_MODE[] == B"01" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 4 FARBEN
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COLOR4 = ST_SHIFT_MODE[] == B"00" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 16 FARBEN
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-- FALCON SHIFT MODE
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FALCON_SHIFT_MODE[].CLK = MAIN_CLK;
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FALCON_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C133"; -- $F8266/2
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FALCON_SHIFT_MODE[] = FB_AD[26..16];
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FALCON_SHIFT_MODE[10..8].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B2;
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FALCON_SHIFT_MODE[7..0].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B3;
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CLUT_OFF[3..0] = FALCON_SHIFT_MODE[3..0] & COLOR4;
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COLOR1 = FALCON_SHIFT_MODE10 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON;
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COLOR8 = FALCON_SHIFT_MODE4 & !COLOR16 & FALCON_VIDEO & !ACP_VIDEO_ON;
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COLOR16 = FALCON_SHIFT_MODE8 & FALCON_VIDEO & !ACP_VIDEO_ON;
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COLOR4 = !COLOR1 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON;
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-- ACP VIDEO CONTROL
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-- BIT 0 = ACP VIDEO ON
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-- BIT 1 = POWER ON VIDEO DAC
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-- BIT 2 = ACP 24BIT
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-- BIT 3 = ACP 16BIT
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-- BIT 4 = ACP 8BIT
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-- BIT 5 = ACP 1BIT
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-- BIT 6 = FALCON SHIFT MODE
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-- BIT 7 = ST SHIFT MODE
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-- BIT 9..8 = VCLK FREQUENZ
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-- BIT 15 =-SYNC ALLOWED
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-- BIT 31..16 = VIDEO_RAM_CTR
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-- BIT 25 = RANDFARBE EINSCHALTEN
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-- BIT 26 = STANDARD ATARI SYNCS
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ACP_VCTR[].CLK = MAIN_CLK;
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ACP_VCTR_CS = !nFB_CS2 & FB_ADR[27..2] == H"100"; -- $400/4
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ACP_VCTR[31..8] = FB_AD[31..8];
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ACP_VCTR[5..0] = FB_AD[5..0];
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ACP_VCTR[31..24].ENA = ACP_VCTR_CS & FB_B0 & !nFB_WR;
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ACP_VCTR[23..16].ENA = ACP_VCTR_CS & FB_B1 & !nFB_WR;
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ACP_VCTR[15..8].ENA = ACP_VCTR_CS & FB_B2 & !nFB_WR;
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ACP_VCTR[5..0].ENA = ACP_VCTR_CS & FB_B3 & !nFB_WR;
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ACP_VIDEO_ON = ACP_VCTR0;
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nPD_VGA = ACP_VCTR1;
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-- ATARI MODUS
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ATARI_SYNC = ACP_VCTR26; -- WENN 1 AUTOMATISCHE AUFLÖSUNG
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-- HORIZONTAL TIMING 640x480
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ATARI_HH[].CLK = MAIN_CLK;
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ATARI_HH_CS = !nFB_CS2 & FB_ADR[27..2] == H"104"; -- $410/4
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ATARI_HH[] = FB_AD[];
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ATARI_HH[31..24].ENA = ATARI_HH_CS & FB_B0 & !nFB_WR;
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ATARI_HH[23..16].ENA = ATARI_HH_CS & FB_B1 & !nFB_WR;
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ATARI_HH[15..8].ENA = ATARI_HH_CS & FB_B2 & !nFB_WR;
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ATARI_HH[7..0].ENA = ATARI_HH_CS & FB_B3 & !nFB_WR;
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-- VERTIKAL TIMING 640x480
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ATARI_VH[].CLK = MAIN_CLK;
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ATARI_VH_CS = !nFB_CS2 & FB_ADR[27..2] == H"105"; -- $414/4
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ATARI_VH[] = FB_AD[];
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ATARI_VH[31..24].ENA = ATARI_VH_CS & FB_B0 & !nFB_WR;
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ATARI_VH[23..16].ENA = ATARI_VH_CS & FB_B1 & !nFB_WR;
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ATARI_VH[15..8].ENA = ATARI_VH_CS & FB_B2 & !nFB_WR;
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ATARI_VH[7..0].ENA = ATARI_VH_CS & FB_B3 & !nFB_WR;
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-- HORIZONTAL TIMING 320x240
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ATARI_HL[].CLK = MAIN_CLK;
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ATARI_HL_CS = !nFB_CS2 & FB_ADR[27..2] == H"106"; -- $418/4
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ATARI_HL[] = FB_AD[];
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ATARI_HL[31..24].ENA = ATARI_HL_CS & FB_B0 & !nFB_WR;
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ATARI_HL[23..16].ENA = ATARI_HL_CS & FB_B1 & !nFB_WR;
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ATARI_HL[15..8].ENA = ATARI_HL_CS & FB_B2 & !nFB_WR;
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ATARI_HL[7..0].ENA = ATARI_HL_CS & FB_B3 & !nFB_WR;
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-- VERTIKAL TIMING 320x240
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ATARI_VL[].CLK = MAIN_CLK;
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ATARI_VL_CS = !nFB_CS2 & FB_ADR[27..2] == H"107"; -- $41C/4
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ATARI_VL[] = FB_AD[];
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ATARI_VL[31..24].ENA = ATARI_VL_CS & FB_B0 & !nFB_WR;
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ATARI_VL[23..16].ENA = ATARI_VL_CS & FB_B1 & !nFB_WR;
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ATARI_VL[15..8].ENA = ATARI_VL_CS & FB_B2 & !nFB_WR;
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ATARI_VL[7..0].ENA = ATARI_VL_CS & FB_B3 & !nFB_WR;
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-- VIDEO PLL CONFIG
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VIDEO_PLL_CONFIG_CS = !nFB_CS2 & FB_ADR[27..9] == H"3" & FB_B0 & FB_B1; -- $(F)000'0600-7FF ->6/2 WORD RESP LONG ONLY
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VR_WR.CLK = MAIN_CLK;
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VR_WR = VIDEO_PLL_CONFIG_CS & !nFB_WR & !VR_BUSY & !VR_WR;
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VR_RD = VIDEO_PLL_CONFIG_CS & nFB_WR & !VR_BUSY;
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VR_DOUT[].CLK = MAIN_CLK;
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VR_DOUT[].ENA = !VR_BUSY;
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VR_DOUT[] = VR_D[];
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VR_FRQ[].CLK = MAIN_CLK;
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VR_FRQ[].ENA = VR_WR & FB_ADR[8..0] == H"04";
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VR_FRQ[] = FB_AD[23..16];
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-- VIDEO PLL RECONFIG
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VIDEO_PLL_RECONFIG_CS = !nFB_CS2 & FB_ADR[27..0] == H"800" & FB_B0; -- $(F)000'0800
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VIDEO_RECONFIG.CLK = MAIN_CLK;
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VIDEO_RECONFIG = VIDEO_PLL_RECONFIG_CS & !nFB_WR & !VR_BUSY & !VIDEO_RECONFIG;
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------------------------------------------------------------------------------------------------------------------------
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VIDEO_RAM_CTR[] = ACP_VCTR[31..16];
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-------------- COLOR MODE IM ACP SETZEN
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COLOR1 = ACP_VCTR5 & !ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
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COLOR8 = ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
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COLOR16 = ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
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COLOR24 = ACP_VCTR2 & ACP_VIDEO_ON;
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ACP_CLUT = ACP_VIDEO_ON & (COLOR1 # COLOR8) # ST_VIDEO & COLOR1;
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-- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER
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ACP_VCTR7 = FALCON_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON;
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ACP_VCTR6 = ST_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON;
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ACP_VCTR[7..6].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR # ST_SHIFT_MODE_CS & !nFB_WR # ACP_VCTR_CS & FB_B3 & !nFB_WR & FB_AD0;
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FALCON_VIDEO = ACP_VCTR7;
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FALCON_CLUT = FALCON_VIDEO & !ACP_VIDEO_ON & !COLOR16;
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ST_VIDEO = ACP_VCTR6;
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ST_CLUT = ST_VIDEO & !ACP_VIDEO_ON & !FALCON_CLUT & !COLOR1;
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CCSEL[].CLK = PIXEL_CLK;
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CCSEL[] = B"000" & ST_CLUT -- ONLY FOR INFORMATION
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# B"001" & FALCON_CLUT
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# B"100" & ACP_CLUT
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# B"101" & COLOR16
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# B"110" & COLOR24
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# B"111" & RAND_ON;
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-- DIVERSE (VIDEO)-REGISTER ----------------------------
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-- RANDFARBE
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BORDER_COLOR[].CLK = MAIN_CLK;
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BORDER_COLOR_CS = !nFB_CS2 & FB_ADR[27..2]==H"101"; -- $404/4
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BORDER_COLOR[] = FB_AD[23..0];
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BORDER_COLOR[23..16].ENA = BORDER_COLOR_CS & FB_B1 & !nFB_WR;
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|
BORDER_COLOR[15..8].ENA = BORDER_COLOR_CS & FB_B2 & !nFB_WR;
|
|
BORDER_COLOR[7..0].ENA = BORDER_COLOR_CS & FB_B3 & !nFB_WR;
|
|
|
|
-- System Config Register
|
|
-- $FFFF8006 [R/W] B 76543210 Monitor-Type Hi
|
|
-- ||||||||
|
|
-- |||||||+- RAM Wait Status
|
|
-- ||||||| 0 = 1 Wait (default)
|
|
-- ||||||| 1 = 0 Wait
|
|
-- ||||||+-- Video Bus Width
|
|
-- |||||| 0 = 16 Bit
|
|
-- |||||| 1 = 32 Bit (default)
|
|
-- ||||++--- ROM Wait Status
|
|
-- |||| 00 = reserved
|
|
-- |||| 01 = 2 Wait (default)
|
|
-- |||| 10 = 1 Wait
|
|
-- |||| 11 = 0 Wait
|
|
-- ||++----- Main Memory Size
|
|
-- || 01 = 4 MB
|
|
-- || 10 = 16 MB
|
|
-- ++------- Monitor Type
|
|
-- 00 Monochrome
|
|
-- 01 RGB
|
|
-- 10 VGA
|
|
-- 11 TV
|
|
|
|
SYS_CTR_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C003"; -- $8006/2
|
|
SYS_CTR[].CLK = MAIN_CLK;
|
|
SYS_CTR[6..0] = FB_AD[22..16];
|
|
SYS_CTR[6..0].ENA = SYS_CTR_CS & !nFB_WR & FB_B3;
|
|
BLITTER_ON = !SYS_CTR3;
|
|
|
|
-- LOF
|
|
LOF_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C107"; -- $820E/2
|
|
LOF[].CLK = MAIN_CLK;
|
|
LOF[] = FB_AD[31..16];
|
|
LOF[15..8].ENA = LOF_CS & !nFB_WR & FB_B2;
|
|
LOF[7..0].ENA = LOF_CS & !nFB_WR & FB_B3;
|
|
|
|
-- LWD
|
|
LWD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C108"; -- $8210/2
|
|
LWD[].CLK = MAIN_CLK;
|
|
LWD[] = FB_AD[31..16];
|
|
LWD[15..8].ENA = LWD_CS & !nFB_WR & FB_B0;
|
|
LWD[7..0].ENA = LWD_CS & !nFB_WR & FB_B1;
|
|
|
|
-- HORIZONTAL
|
|
-- HHT
|
|
HHT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C141"; -- $8282/2
|
|
HHT[].CLK = MAIN_CLK;
|
|
HHT[] = FB_AD[27..16];
|
|
HHT[11..8].ENA = HHT_CS & !nFB_WR & FB_B2;
|
|
HHT[7..0].ENA = HHT_CS & !nFB_WR & FB_B3;
|
|
|
|
-- HBE
|
|
HBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C143"; -- $8286/2
|
|
HBE[].CLK = MAIN_CLK;
|
|
HBE[] = FB_AD[27..16];
|
|
HBE[11..8].ENA = HBE_CS & !nFB_WR & FB_B2;
|
|
HBE[7..0].ENA = HBE_CS & !nFB_WR & FB_B3;
|
|
|
|
-- HDB
|
|
HDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C144"; -- $8288/2
|
|
HDB[].CLK = MAIN_CLK;
|
|
HDB[] = FB_AD[27..16];
|
|
HDB[11..8].ENA = HDB_CS & !nFB_WR & FB_B0;
|
|
HDB[7..0].ENA = HDB_CS & !nFB_WR & FB_B1;
|
|
-- HDE
|
|
HDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C145"; -- $828A/2
|
|
HDE[].CLK = MAIN_CLK;
|
|
HDE[] = FB_AD[27..16];
|
|
HDE[11..8].ENA = HDE_CS & !nFB_WR & FB_B2;
|
|
HDE[7..0].ENA = HDE_CS & !nFB_WR & FB_B3;
|
|
|
|
-- HBB
|
|
HBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C142"; -- $8284/2
|
|
HBB[].CLK = MAIN_CLK;
|
|
HBB[] = FB_AD[27..16];
|
|
HBB[11..8].ENA = HBB_CS & !nFB_WR & FB_B0;
|
|
HBB[7..0].ENA = HBB_CS & !nFB_WR & FB_B1;
|
|
|
|
-- HSS
|
|
HSS_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C146"; -- Videl HSYNC start register $828C / 2
|
|
HSS[].CLK = MAIN_CLK;
|
|
HSS[] = FB_AD[27..16];
|
|
HSS[11..8].ENA = HSS_CS & !nFB_WR & FB_B0;
|
|
HSS[7..0].ENA = HSS_CS & !nFB_WR & FB_B1;
|
|
|
|
-- VERTIKAL
|
|
-- VBE
|
|
VBE_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C153"; -- $82A6/2
|
|
VBE[].CLK = MAIN_CLK;
|
|
VBE[] = FB_AD[26..16];
|
|
VBE[10..8].ENA = VBE_CS & !nFB_WR & FB_B2;
|
|
VBE[7..0].ENA = VBE_CS & !nFB_WR & FB_B3;
|
|
|
|
-- VDB
|
|
VDB_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C154"; -- $82A8/2
|
|
VDB[].CLK = MAIN_CLK;
|
|
VDB[] = FB_AD[26..16];
|
|
VDB[10..8].ENA = VDB_CS & !nFB_WR & FB_B0;
|
|
VDB[7..0].ENA = VDB_CS & !nFB_WR & FB_B1;
|
|
|
|
-- VDE
|
|
VDE_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C155"; -- $82AA/2
|
|
VDE[].CLK = MAIN_CLK;
|
|
VDE[] = FB_AD[26..16];
|
|
VDE[10..8].ENA = VDE_CS & !nFB_WR & FB_B2;
|
|
VDE[7..0].ENA = VDE_CS & !nFB_WR & FB_B3;
|
|
-- VBB
|
|
VBB_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C152"; -- $82A4/2
|
|
VBB[].CLK = MAIN_CLK;
|
|
VBB[] = FB_AD[26..16];
|
|
VBB[10..8].ENA = VBB_CS & !nFB_WR & FB_B0;
|
|
VBB[7..0].ENA = VBB_CS & !nFB_WR & FB_B1;
|
|
|
|
-- VSS
|
|
VSS_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C156"; -- $82AC/2
|
|
VSS[].CLK = MAIN_CLK;
|
|
VSS[] = FB_AD[26..16];
|
|
VSS[10..8].ENA = VSS_CS & !nFB_WR & FB_B0;
|
|
VSS[7..0].ENA = VSS_CS & !nFB_WR & FB_B1;
|
|
|
|
-- VFT
|
|
VFT_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C151"; -- $82A2/2
|
|
VFT[].CLK = MAIN_CLK;
|
|
VFT[] = FB_AD[26..16];
|
|
VFT[10..8].ENA = VFT_CS & !nFB_WR & FB_B2;
|
|
VFT[7..0].ENA = VFT_CS & !nFB_WR & FB_B3;
|
|
|
|
-- VCO
|
|
VCO_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C160"; -- $82C0 / 2 Falcon clock control register VCO
|
|
VCO[].CLK = MAIN_CLK;
|
|
VCO[] = FB_AD[24..16];
|
|
VCO[8].ENA = VCO_CS & !nFB_WR & FB_B0;
|
|
VCO[7..0].ENA = VCO_CS & !nFB_WR & FB_B1;
|
|
|
|
-- VCNTRL
|
|
VCNTRL_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C161"; -- $82C2 / 2 Falcon resolution control register VCNTRL
|
|
VCNTRL[].CLK = MAIN_CLK;
|
|
VCNTRL[] = FB_AD[19..16];
|
|
VCNTRL[3..0].ENA = VCNTRL_CS & !nFB_WR & FB_B3;
|
|
|
|
--- REGISTER OUT
|
|
-- low word register access
|
|
FB_AD[31..16] = lpm_bustri_WORD(
|
|
ST_SHIFT_MODE_CS & (0, ST_SHIFT_MODE[],B"00000000")
|
|
# FALCON_SHIFT_MODE_CS & (0, FALCON_SHIFT_MODE[])
|
|
# SYS_CTR_CS & (B"100000000", SYS_CTR[6..4], !BLITTER_RUN, SYS_CTR[2..0])
|
|
# LOF_CS & LOF[]
|
|
# LWD_CS & LWD[]
|
|
# HBE_CS & (0, HBE[])
|
|
# HDB_CS & (0, HDB[])
|
|
# HDE_CS & (0, HDE[])
|
|
# HBB_CS & (0, HBB[])
|
|
# HSS_CS & (0, HSS[])
|
|
# HHT_CS & (0, HHT[])
|
|
# VBE_CS & (0, VBE[])
|
|
# VDB_CS & (0, VDB[])
|
|
# VDE_CS & (0, VDE[])
|
|
# VBB_CS & (0, VBB[])
|
|
# VSS_CS & (0, VSS[])
|
|
# VFT_CS & (0, VFT[])
|
|
# VCO_CS & (0, VCO[])
|
|
# VCNTRL_CS & (0, VCNTRL[])
|
|
# ACP_VCTR_CS & ACP_VCTR[31..16]
|
|
# ATARI_HH_CS & ATARI_HH[31..16]
|
|
# ATARI_VH_CS & ATARI_VH[31..16]
|
|
# ATARI_HL_CS & ATARI_HL[31..16]
|
|
# ATARI_VL_CS & ATARI_VL[31..16]
|
|
# BORDER_COLOR_CS & (0, BORDER_COLOR[23..16])
|
|
# VIDEO_PLL_CONFIG_CS & (0,VR_DOUT[])
|
|
# VIDEO_PLL_RECONFIG_CS & (VR_BUSY, B"0000", VR_WR, VR_RD, VIDEO_RECONFIG, H"FA")
|
|
,(ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # BORDER_COLOR_CS # SYS_CTR_CS # LOF_CS # LWD_CS
|
|
# HBE_CS # HDB_CS # HDE_CS # HBB_CS # HSS_CS # HHT_CS
|
|
# ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS # VIDEO_PLL_CONFIG_CS # VIDEO_PLL_RECONFIG_CS
|
|
# VBE_CS # VDB_CS # VDE_CS # VBB_CS # VSS_CS # VFT_CS # VCO_CS # VCNTRL_CS) & !nFB_OE);
|
|
|
|
-- high word register access
|
|
FB_AD[15..0] = lpm_bustri_WORD(
|
|
ACP_VCTR_CS & ACP_VCTR[15..0]
|
|
# ATARI_HH_CS & ATARI_HH[15..0]
|
|
# ATARI_VH_CS & ATARI_VH[15..0]
|
|
# ATARI_HL_CS & ATARI_HL[15..0]
|
|
# ATARI_VL_CS & ATARI_VL[15..0]
|
|
# BORDER_COLOR_CS & BORDER_COLOR[15..0],
|
|
(ACP_VCTR_CS # BORDER_COLOR_CS # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS ) & !nFB_OE);
|
|
|
|
VIDEO_MOD_TA = CLUT_TA # ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # SYS_CTR_CS # LOF_CS # LWD_CS
|
|
# HBE_CS # HDB_CS # HDE_CS # HBB_CS # HSS_CS # HHT_CS
|
|
# ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS
|
|
# VBE_CS # VDB_CS # VDE_CS # VBB_CS # VSS_CS # VFT_CS # VCO_CS # VCNTRL_CS;
|
|
|
|
-- VIDEO AUSGABE SETZEN
|
|
CLK17M.CLK = CLK33M;
|
|
CLK17M = !CLK17M;
|
|
|
|
CLK13M.CLK = CLK25M;
|
|
CLK13M = !CLK13M;
|
|
|
|
PIXEL_CLK = CLK13M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & (VCNTRL2 & VCO2 # VCO0) -- 320 pixels, 32 MHz,
|
|
# CLK17M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & (VCNTRL2 & !VCO2 # VCO0) -- 320 pixels, 25.175 MHz,
|
|
# CLK25M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VCNTRL2 & VCO2 & !VCO0 -- 640 pixels, 32 MHz, VGA monitor
|
|
# CLK33M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VCNTRL2 & !VCO2 & !VCO0 -- 640 pixels, 25.175 MHz, VGA monitor
|
|
# CLK25M & ACP_VIDEO_ON & ACP_VCTR[9..8] == B"00"
|
|
# CLK33M & ACP_VIDEO_ON & ACP_VCTR[9..8] == B"01"
|
|
# CLK_VIDEO & ACP_VIDEO_ON & ACP_VCTR[9];
|
|
|
|
--------------------------------------------------------------
|
|
-- HORIZONTALE SYNC LÄNGE in PIXEL_CLK
|
|
----------------------------------------------------------------
|
|
-- HSY_LEN[].CLK = MAIN_CLK;
|
|
HSY_LEN[].CLK = PIXEL_CLK; -- check if this is better (mfro)
|
|
HSY_LEN[] = 14 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & (VCNTRL2 & VCO2 # VCO0) -- 320 pixels, 32 MHz, RGB
|
|
# 16 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & (VCNTRL2 & !VCO2 # VCO0) -- 320 pixels, 25.175 MHz, VGA
|
|
# 28 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VCNTRL2 & VCO2 & !VCO0 -- 640 pixels, 32 MHz, RGB
|
|
# 32 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VCNTRL2 & !VCO2 & !VCO0 -- 640 pixels, 25.175 MHz, VGA
|
|
# 28 & ACP_VIDEO_ON & ACP_VCTR[9..8] == B"00"
|
|
# 32 & ACP_VIDEO_ON & ACP_VCTR[9..8] == B"01"
|
|
# 16 + (0, VR_FRQ[7..1]) & ACP_VIDEO_ON & ACP_VCTR[9]; -- hsync pulse length in pixeln = frequenz / = 500ns
|
|
|
|
MULF[] = 2 & !ST_VIDEO & VCNTRL2 -- MULTIPLIKATIONS FAKTOR
|
|
# 4 & !ST_VIDEO & !VCNTRL2
|
|
# 16 & ST_VIDEO & VCNTRL2
|
|
# 32 & ST_VIDEO & !VCNTRL2;
|
|
|
|
|
|
HDIS_LEN[] = 320 & VCNTRL2 -- BREITE IN PIXELN
|
|
# 640 & !VCNTRL2;
|
|
|
|
-- DOPPELZEILENMODUS
|
|
DOP_ZEI.CLK = MAIN_CLK;
|
|
DOP_ZEI = VCNTRL0 & (FALCON_VIDEO # ST_VIDEO); -- ZEILENVERDOPPELUNG EIN AUS
|
|
|
|
INTER_ZEI.CLK = PIXEL_CLK;
|
|
INTER_ZEI = DOP_ZEI & VVCNT0 != VDIS_START0 & VVCNT[] != 0 & VHCNT[] < (HDIS_END[] - 1) -- EINSCHIEBEZEILE AUF "DOPPEL" ZEILEN UND ZEILE NULL WEGEN SYNC
|
|
# DOP_ZEI & VVCNT0 == VDIS_START0 & VVCNT[] != 0 & VHCNT[] > (HDIS_END[] - 2); -- EINSCHIEBEZEILE AUF "NORMAL" ZEILEN UND ZEILE NULL WEGEN SYNC
|
|
|
|
DOP_FIFO_CLR.CLK = PIXEL_CLK;
|
|
DOP_FIFO_CLR = INTER_ZEI & HSYNC_START # SYNC_PIX; -- DOPPELZEILENFIFO LÖSCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START
|
|
|
|
RAND_LINKS[] = HBE[] & ACP_VIDEO_ON
|
|
# 21 & !ACP_VIDEO_ON & ATARI_SYNC & VCNTRL2
|
|
# 42 & !ACP_VIDEO_ON & ATARI_SYNC & !VCNTRL2
|
|
# HBE[] * (0, MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; --
|
|
|
|
HDIS_START[] = HDB[] & ACP_VIDEO_ON
|
|
# RAND_LINKS[] + 1 & !ACP_VIDEO_ON; --
|
|
|
|
HDIS_END[] = HDE[] & ACP_VIDEO_ON
|
|
# RAND_LINKS[] + HDIS_LEN[] & !ACP_VIDEO_ON; --
|
|
|
|
RAND_RECHTS[] = HBB[] & ACP_VIDEO_ON
|
|
# HDIS_END[] + 1 & !ACP_VIDEO_ON; --
|
|
|
|
HS_START[] = HSS[] & ACP_VIDEO_ON
|
|
# ATARI_HL[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & VCNTRL2
|
|
# ATARI_HH[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & !VCNTRL2
|
|
# (HHT[] + 1 + HSS[]) * (0, MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; --
|
|
|
|
H_TOTAL[] = HHT[] & ACP_VIDEO_ON
|
|
# ATARI_HL[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & VCNTRL2
|
|
# ATARI_HH[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VCNTRL2
|
|
# (HHT[] + 2) * (0, MULF[]) & !ACP_VIDEO_ON & !ATARI_SYNC; --
|
|
|
|
RAND_OBEN[] = VBE[] & ACP_VIDEO_ON
|
|
# 31 & !ACP_VIDEO_ON & ATARI_SYNC
|
|
# (0, VBE[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC;
|
|
|
|
VDIS_START[] = VDB[] & ACP_VIDEO_ON
|
|
# 32 & !ACP_VIDEO_ON & ATARI_SYNC
|
|
# (0, VDB[10..1])+1 & !ACP_VIDEO_ON & !ATARI_SYNC;
|
|
|
|
VDIS_END[] = VDE[] & ACP_VIDEO_ON
|
|
# 431 & !ACP_VIDEO_ON & ATARI_SYNC & ST_VIDEO
|
|
# 511 & !ACP_VIDEO_ON & ATARI_SYNC & !ST_VIDEO
|
|
# (0, VDE[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC;
|
|
|
|
RAND_UNTEN[] = VBB[] & ACP_VIDEO_ON
|
|
# VDIS_END[] + 1 & !ACP_VIDEO_ON & ATARI_SYNC
|
|
# (0, VBB[10..1])+1 & !ACP_VIDEO_ON & !ATARI_SYNC;
|
|
|
|
VS_START[] = VSS[] & ACP_VIDEO_ON
|
|
# ATARI_VL[10..0] & !ACP_VIDEO_ON & ATARI_SYNC & VCNTRL2
|
|
# ATARI_VH[10..0] & !ACP_VIDEO_ON & ATARI_SYNC & !VCNTRL2
|
|
# (0, VSS[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC;
|
|
|
|
V_TOTAL[] = VFT[] & ACP_VIDEO_ON
|
|
# ATARI_VL[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & VCNTRL2
|
|
# ATARI_VH[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VCNTRL2
|
|
# (0, VFT[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC;
|
|
-- ZÄHLER
|
|
LAST.CLK = PIXEL_CLK;
|
|
LAST = VHCNT[] == (H_TOTAL[] - 2);
|
|
|
|
VHCNT[].CLK = PIXEL_CLK;
|
|
VHCNT[] = (VHCNT[] + 1) & !LAST;
|
|
|
|
VVCNT[].CLK = PIXEL_CLK;
|
|
VVCNT[].ENA = LAST;
|
|
VVCNT[] = (VVCNT[] + 1) & (VVCNT[] != V_TOTAL[] - 1);
|
|
|
|
-- DISPLAY ON OFF
|
|
DPO_ZL.CLK = PIXEL_CLK;
|
|
DPO_ZL = (VVCNT[] > RAND_OBEN[] - 1) & (VVCNT[] < RAND_UNTEN[] - 1); -- 1 ZEILE DAVOR ON OFF
|
|
DPO_ZL.ENA = LAST; -- AM ZEILENENDE ÜBERNEHMEN
|
|
|
|
DPO_ON.CLK = PIXEL_CLK;
|
|
DPO_ON = VHCNT[] == RAND_LINKS[]; -- BESSER EINZELN WEGEN TIMING
|
|
|
|
DPO_OFF.CLK = PIXEL_CLK;
|
|
DPO_OFF = VHCNT[] == (RAND_RECHTS[] - 1);
|
|
|
|
DISP_ON.CLK = PIXEL_CLK;
|
|
DISP_ON = DISP_ON & !DPO_OFF
|
|
# DPO_ON & DPO_ZL;
|
|
|
|
-- DATENTRANSFER ON OFF
|
|
VCO_ON.CLK = PIXEL_CLK;
|
|
VCO_ON = VHCNT[] == (HDIS_START[] - 1); -- BESSER EINZELN WEGEN TIMING
|
|
|
|
VCO_OFF.CLK = PIXEL_CLK;
|
|
VCO_OFF = VHCNT[] == HDIS_END[];
|
|
|
|
VCO_ZL.CLK = PIXEL_CLK;
|
|
VCO_ZL.ENA = LAST; -- AM ZEILENENDE ÜBERNEHMEN
|
|
VCO_ZL = (VVCNT[] >= (VDIS_START[] - 1)) & (VVCNT[] < VDIS_END[]); -- 1 ZEILE DAVOR ON OFF
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VDTRON.CLK = PIXEL_CLK;
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VDTRON = VDTRON & !VCO_OFF
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# VCO_ON & VCO_ZL;
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-- VERZÖGERUNG UND SYNC
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HSYNC_START.CLK = PIXEL_CLK;
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HSYNC_START = VHCNT[] == HS_START[] - 3;
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HSYNC_I[].CLK = PIXEL_CLK;
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HSYNC_I[] = HSY_LEN[] & HSYNC_START
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# (HSYNC_I[] - 1) & !HSYNC_START & HSYNC_I[] != 0;
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VSYNC_START.CLK = PIXEL_CLK;
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VSYNC_START.ENA = LAST;
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VSYNC_START = VVCNT[] == (VS_START[] - 3); -- start am ende der Zeile vor dem vsync
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VSYNC_I[].CLK = PIXEL_CLK;
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VSYNC_I[].ENA = LAST; -- start am ende der Zeile vor dem vsync
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VSYNC_I[] = 3 & VSYNC_START -- 3 zeilen vsync length
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# (VSYNC_I[]-1) & !VSYNC_START & VSYNC_I[] != 0; -- runterzählen bis 0
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VERZ[][].CLK = PIXEL_CLK;
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VERZ[][1] = VERZ[][0];
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VERZ[][2] = VERZ[][1];
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VERZ[][3] = VERZ[][2];
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VERZ[][4] = VERZ[][3];
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VERZ[][5] = VERZ[][4];
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VERZ[][6] = VERZ[][5];
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VERZ[][7] = VERZ[][6];
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VERZ[][8] = VERZ[][7];
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VERZ[][9] = VERZ[][8];
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VERZ[0][0] = DISP_ON;
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-- VERZ[1][0] = HSYNC_I[] != 0;
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VERZ[1][0] = (!ACP_VCTR15 # !VCO6) & HSYNC_I[] != 0
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# ACP_VCTR15 & VCO6 & HSYNC_I[] == 0; -- NUR MÖGLICH WENN BEIDE
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VERZ[2][0] = (!ACP_VCTR15 # !VCO5) & VSYNC_I[] != 0
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# ACP_VCTR15 & VCO5 & VSYNC_I[] == 0; -- NUR MÖGLICH WENN BEIDE
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nBLANK.CLK = PIXEL_CLK;
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-- nBLANK = VERZ[0][8];
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nBLANK = DISP_ON;
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HSYNC.CLK = PIXEL_CLK;
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-- HSYNC = VERZ[1][9];
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HSYNC = (!ACP_VCTR15 # !VCO6) & HSYNC_I[] != 0
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# ACP_VCTR15 & VCO6 & HSYNC_I[] == 0; -- NUR MÖGLICH WENN BEIDE
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VSYNC.CLK = PIXEL_CLK;
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-- VSYNC = VERZ[2][9];
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VSYNC = (!ACP_VCTR15 # !VCO5) & VSYNC_I[] != 0
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# ACP_VCTR15 & VCO5 & VSYNC_I[] == 0; -- NUR MÖGLICH WENN BEIDE
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nSYNC = GND;
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-- RANDFARBE MACHEN ------------------------------------
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RAND[].CLK = PIXEL_CLK;
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RAND[0] = DISP_ON & !VDTRON & ACP_VCTR25;
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RAND[1] = RAND[0];
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RAND[2] = RAND[1];
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RAND[3] = RAND[2];
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RAND[4] = RAND[3];
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RAND[5] = RAND[4];
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RAND[6] = RAND[5];
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-- RAND_ON = RAND[6];
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RAND_ON = DISP_ON & !VDTRON & ACP_VCTR25;
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----------------------------------------------------------
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CLR_FIFO.CLK = PIXEL_CLK;
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CLR_FIFO.ENA = LAST;
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CLR_FIFO = VVCNT[] == V_TOTAL[] - 2; -- IN LETZTER ZEILE LÖSCHEN
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START_ZEILE.CLK = PIXEL_CLK;
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START_ZEILE.ENA = LAST;
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START_ZEILE = VVCNT[] == 0; -- ZEILE 1
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SYNC_PIX.CLK = PIXEL_CLK;
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SYNC_PIX = VHCNT[] == 3 & START_ZEILE; -- SUB PIXEL ZÄHLER SYNCHRONISIEREN
|
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SYNC_PIX1.CLK = PIXEL_CLK;
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SYNC_PIX1 = VHCNT[] == 5 & START_ZEILE; -- SUB PIXEL ZÄHLER SYNCHRONISIEREN
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SYNC_PIX2.CLK = PIXEL_CLK;
|
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SYNC_PIX2 = VHCNT[] == 7 & START_ZEILE; -- SUB PIXEL ZÄHLER SYNCHRONISIEREN
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|
SUB_PIXEL_CNT[].CLK = PIXEL_CLK;
|
|
SUB_PIXEL_CNT[].ENA = VDTRON # SYNC_PIX;
|
|
SUB_PIXEL_CNT[] = (SUB_PIXEL_CNT[] + 1) & !SYNC_PIX; --count up if display on sonst clear bei sync pix
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|
|
FIFO_RDE.CLK = PIXEL_CLK;
|
|
FIFO_RDE = (SUB_PIXEL_CNT[6..0] == 1 & COLOR1
|
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# SUB_PIXEL_CNT[5..0] == 1 & COLOR2
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# SUB_PIXEL_CNT[4..0] == 1 & COLOR4
|
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# SUB_PIXEL_CNT[3..0] == 1 & COLOR8
|
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# SUB_PIXEL_CNT[2..0] == 1 & COLOR16
|
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# SUB_PIXEL_CNT[1..0] == 1 & COLOR24) & VDTRON
|
|
# SYNC_PIX # SYNC_PIX1 # SYNC_PIX2; -- 3 CLOCK ZUSÄTZLICH FÜR FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION
|
|
|
|
CLUT_MUX_ADR[].CLK = PIXEL_CLK;
|
|
|
|
CLUT_MUX_AV[][].CLK = PIXEL_CLK;
|
|
CLUT_MUX_AV[0][] = SUB_PIXEL_CNT[3..0];
|
|
CLUT_MUX_AV[1][] = CLUT_MUX_AV[0][];
|
|
CLUT_MUX_ADR[] = CLUT_MUX_AV[1][];
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|
END;
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