31 lines
1.1 KiB
Verilog
31 lines
1.1 KiB
Verilog
// Copyright (C) 1991-2009 Altera Corporation
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// Your use of Altera Corporation's design tools, logic functions
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// and other software and tools, and its AMPP partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License
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// Subscription Agreement, Altera MegaCore Function License
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// Agreement, or other applicable license agreement, including,
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// without limitation, that your use is for the sole purpose of
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// programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the
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// applicable agreement for further details.
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// PROGRAM "Quartus II 64-Bit"
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// VERSION "Version 9.1 Build 222 10/21/2009 SJ Full Version"
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// CREATED "Sat Mar 01 09:20:01 2014"
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module mux41_0(S0,S1,D0,INH,D1,Q);
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input S0;
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input S1;
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input D0;
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input INH;
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input D1;
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output Q;
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mux41 lpm_instance(.S0(S0),.S1(S1),.D0(D0),.INH(INH),.D1(D1),.Q(Q));
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endmodule
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