222 lines
10 KiB
Plaintext
222 lines
10 KiB
Plaintext
-- megafunction wizard: %ALTSYNCRAM%
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-- GENERATION: STANDARD
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-- VERSION: WM1.0
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-- MODULE: altsyncram
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-- ============================================================
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-- File Name: altsyncram0.tdf
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-- Megafunction Name(s):
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-- altsyncram
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--
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-- Simulation Library Files(s):
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-- altera_mf
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-- ============================================================
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-- ************************************************************
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-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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--
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-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
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-- ************************************************************
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--Copyright (C) 1991-2010 Altera Corporation
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--Your use of Altera Corporation's design tools, logic functions
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--and other software and tools, and its AMPP partner logic
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--functions, and any output files from any of the foregoing
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--(including device programming or simulation files), and any
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--associated documentation or information are expressly subject
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--to the terms and conditions of the Altera Program License
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--Subscription Agreement, Altera MegaCore Function License
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--Agreement, or other applicable license agreement, including,
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--without limitation, that your use is for the sole purpose of
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--programming logic devices manufactured by Altera and sold by
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--Altera or its authorized distributors. Please refer to the
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--applicable agreement for further details.
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INCLUDE "altsyncram.inc";
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SUBDESIGN altsyncram0
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(
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address_a[3..0] : INPUT;
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address_b[3..0] : INPUT;
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byteena_a[1..0] : INPUT = VCC;
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clock_a : INPUT = VCC;
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clock_b : INPUT;
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data_a[15..0] : INPUT;
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data_b[15..0] : INPUT;
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wren_a : INPUT = GND;
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wren_b : INPUT = GND;
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q_a[15..0] : OUTPUT;
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q_b[15..0] : OUTPUT;
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)
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VARIABLE
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altsyncram_component : altsyncram WITH (
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ADDRESS_REG_B = "CLOCK1",
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BYTE_SIZE = 8,
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CLOCK_ENABLE_INPUT_A = "BYPASS",
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CLOCK_ENABLE_INPUT_B = "BYPASS",
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CLOCK_ENABLE_OUTPUT_A = "BYPASS",
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CLOCK_ENABLE_OUTPUT_B = "BYPASS",
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INDATA_REG_B = "CLOCK1",
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INTENDED_DEVICE_FAMILY = "Cyclone III",
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LPM_TYPE = "altsyncram",
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NUMWORDS_A = 16,
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NUMWORDS_B = 16,
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OPERATION_MODE = "BIDIR_DUAL_PORT",
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OUTDATA_ACLR_A = "NONE",
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OUTDATA_ACLR_B = "NONE",
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OUTDATA_REG_A = "UNREGISTERED",
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OUTDATA_REG_B = "UNREGISTERED",
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POWER_UP_UNINITIALIZED = "FALSE",
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READ_DURING_WRITE_MODE_PORT_A = "NEW_DATA_WITH_NBE_READ",
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READ_DURING_WRITE_MODE_PORT_B = "NEW_DATA_WITH_NBE_READ",
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WIDTHAD_A = 4,
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WIDTHAD_B = 4,
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WIDTH_A = 16,
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WIDTH_B = 16,
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WIDTH_BYTEENA_A = 2,
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WIDTH_BYTEENA_B = 1,
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WRCONTROL_WRADDRESS_REG_B = "CLOCK1"
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);
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BEGIN
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q_a[15..0] = altsyncram_component.q_a[15..0];
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q_b[15..0] = altsyncram_component.q_b[15..0];
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altsyncram_component.wren_a = wren_a;
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altsyncram_component.clock0 = clock_a;
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altsyncram_component.wren_b = wren_b;
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altsyncram_component.clock1 = clock_b;
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altsyncram_component.byteena_a[1..0] = byteena_a[1..0];
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altsyncram_component.address_a[3..0] = address_a[3..0];
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altsyncram_component.address_b[3..0] = address_b[3..0];
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altsyncram_component.data_a[15..0] = data_a[15..0];
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altsyncram_component.data_b[15..0] = data_b[15..0];
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END;
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-- ============================================================
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-- CNX file retrieval info
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-- ============================================================
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-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
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-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
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-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
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-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
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-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "1"
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-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
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-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
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-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
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-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
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-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
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-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
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-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
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-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
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-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
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-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
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-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
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-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
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-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
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-- Retrieval info: PRIVATE: Clock NUMERIC "5"
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-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
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-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
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-- Retrieval info: PRIVATE: ECC NUMERIC "0"
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-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
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-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
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-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
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-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
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-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
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-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
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-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
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-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
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-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
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-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "256"
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-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
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-- Retrieval info: PRIVATE: MIFfilename STRING ""
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-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
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-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
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-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
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-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
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-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
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-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "4"
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-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "4"
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-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
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-- Retrieval info: PRIVATE: REGq NUMERIC "0"
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-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
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-- Retrieval info: PRIVATE: REGrren NUMERIC "0"
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-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
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-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
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-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
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-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
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-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
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-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
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-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
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-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
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-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
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-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
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-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
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-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
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-- Retrieval info: PRIVATE: enable NUMERIC "0"
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-- Retrieval info: PRIVATE: rden NUMERIC "0"
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-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
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-- Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
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-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
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-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
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-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
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-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
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-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
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-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
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-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
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-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16"
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-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16"
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-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
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-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
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-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
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-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
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-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
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-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
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-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_WITH_NBE_READ"
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-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_WITH_NBE_READ"
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-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "4"
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-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "4"
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-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
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-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
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-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "2"
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-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
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-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
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-- Retrieval info: USED_PORT: address_a 0 0 4 0 INPUT NODEFVAL address_a[3..0]
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-- Retrieval info: USED_PORT: address_b 0 0 4 0 INPUT NODEFVAL address_b[3..0]
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-- Retrieval info: USED_PORT: byteena_a 0 0 2 0 INPUT VCC byteena_a[1..0]
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-- Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC clock_a
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-- Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL clock_b
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-- Retrieval info: USED_PORT: data_a 0 0 16 0 INPUT NODEFVAL data_a[15..0]
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-- Retrieval info: USED_PORT: data_b 0 0 16 0 INPUT NODEFVAL data_b[15..0]
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-- Retrieval info: USED_PORT: q_a 0 0 16 0 OUTPUT NODEFVAL q_a[15..0]
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-- Retrieval info: USED_PORT: q_b 0 0 16 0 OUTPUT NODEFVAL q_b[15..0]
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-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND wren_a
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-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND wren_b
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-- Retrieval info: CONNECT: @data_a 0 0 16 0 data_a 0 0 16 0
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-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
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-- Retrieval info: CONNECT: q_a 0 0 16 0 @q_a 0 0 16 0
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-- Retrieval info: CONNECT: q_b 0 0 16 0 @q_b 0 0 16 0
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-- Retrieval info: CONNECT: @address_a 0 0 4 0 address_a 0 0 4 0
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-- Retrieval info: CONNECT: @data_b 0 0 16 0 data_b 0 0 16 0
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-- Retrieval info: CONNECT: @address_b 0 0 4 0 address_b 0 0 4 0
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-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
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-- Retrieval info: CONNECT: @byteena_a 0 0 2 0 byteena_a 0 0 2 0
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-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
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-- Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
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-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0.tdf TRUE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0.inc TRUE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0.cmp FALSE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0.bsf FALSE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0_inst.tdf FALSE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0_waveforms.html FALSE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0_wave*.jpg FALSE
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-- Retrieval info: LIB_FILE: altera_mf
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