Files
FPGA_Config/FPGA_Quartus_13.1/altpll4.qip
Markus Fröschle 7e2181fbc9 improved timing, added timing constraints, got rid of CLK_33M
Design compiles and runs, but still has issues with different screen resolutions and video clocks
2015-09-23 09:49:05 +00:00

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set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.tdf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.inc"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.cmp"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.ppf"]