Files
FPGA_Config/FPGA_by_Gregory_Estrade/altpll2.ppf
2018-04-06 19:07:30 +02:00

14 lines
640 B
XML

<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE pinplan>
<pinplan intended_family="Cyclone III" variation_name="altpll2" megafunction_name="ALTPLL" specifies="all_ports">
<global>
<pin name="inclk0" direction="input" scope="external" source="clock" />
<pin name="c0" direction="output" scope="external" source="clock" />
<pin name="c1" direction="output" scope="external" source="clock" />
<pin name="c2" direction="output" scope="external" source="clock" />
<pin name="c3" direction="output" scope="external" source="clock" />
<pin name="c4" direction="output" scope="external" source="clock" />
</global>
</pinplan>