Files
FPGA_Config/FPGA_by_Gregory_Estrade/Video/altddio_bidir0.ppf
2018-04-06 19:07:30 +02:00

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840 B
XML

<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE pinplan>
<pinplan intended_family="Cyclone III" variation_name="altddio_bidir0" megafunction_name="ALTDDIO_BIDIR" specifies="all_ports">
<global>
<pin name="datain_h[31..0]" direction="input" scope="external" />
<pin name="datain_l[31..0]" direction="input" scope="external" />
<pin name="inclock" direction="input" scope="external" source="clock" />
<pin name="oe" direction="input" scope="external" />
<pin name="outclock" direction="input" scope="external" source="clock" />
<pin name="combout[31..0]" direction="output" scope="external" />
<pin name="dataout_h[31..0]" direction="output" scope="external" />
<pin name="dataout_l[31..0]" direction="output" scope="external" />
<pin name="padio[31..0]" direction="bidir" scope="external" />
</global>
</pinplan>