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FPGA_Config/FPGA_by_Fredi
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David Gálvez 38144f937c Create README.md
2018-04-09 17:33:13 +02:00
..
.sopc_builder
Sync with Fredi's source tree 15/04/2017
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DSP
Sync with Fredi's source 22/06/2017
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FalconIO_SDCard_IDE_CF
Sync with Fredi's source 22/06/2017
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Interrupt_Handler
Sync with Fredi's source 22/06/2017
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Video
Sync with Fredi's source 22/06/2017
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altddio_out0.cmp
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altddio_out0.inc
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altddio_out0.ppf
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altddio_out0.qip
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altddio_out0.vhd
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altddio_out3.bsf
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altddio_out3.cmp
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altddio_out3.inc
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altddio_out3.ppf
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altddio_out3.qip
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altddio_out3.vhd
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altiobuf_bidir0_iobuf_bidir_quo.tdf
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altiobuf_bidir0.bsf
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altiobuf_bidir0.cmp
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altiobuf_bidir0.inc
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altiobuf_bidir0.qip
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altiobuf_bidir0.tdf
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altpll0.bsf
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altpll0.cmp
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altpll0.inc
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altpll0.ppf
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altpll0.qip
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altpll0.vhd
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altpll1.bsf
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altpll1.cmp
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altpll1.inc
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altpll1.ppf
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altpll1.qip
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altpll1.vhd
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altpll2.bsf
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altpll2.cmp
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altpll2.inc
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altpll2.ppf
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altpll2.qip
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altpll2.vhd
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altpll3.bsf
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altpll3.cmp
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altpll3.inc
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altpll3.ppf
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altpll3.qip
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altpll3.vhd
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altpll4.bsf
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altpll4.cmp
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altpll4.inc
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altpll4.mif
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altpll4.ppf
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altpll4.qip
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altpll4.tdf
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altpll_reconfig0.bsf
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altpll_reconfig0.qip
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altpll_reconfig1_pllrcfg_bju.tdf
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altpll_reconfig1_pllrcfg_t4q.tdf
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altpll_reconfig1.bsf
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altpll_reconfig1.cmp
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altpll_reconfig1.inc
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altpll_reconfig1.qip
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altpll_reconfig1.tdf
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blitter.tdf
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blitter.tdf.bak
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Coldari1.qsf
Initial commit
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firebee1_assignment_defaults.qdf
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firebee1.bdf
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firebee1.done
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firebee1.dpf
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firebee1.fit.summary
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firebee1.map.summary
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firebee1.pin
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firebee1.qsf
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firebee1.qws
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firebee1.sof
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firebee1.tan.summary
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firebeei1.qpf
Initial commit
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FPGA_DATE_lpm_constant_e19.tdf
Sync with Fredi's source 22/06/2017
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FPGA_DATE_lpm_constant_f19.tdf
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FPGA_DATE_lpm_constant_g19.tdf
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FPGA_DATE.bsf
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FPGA_DATE.inc
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FPGA_DATE.qip
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FPGA_DATE.tdf
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lpm_bustri_BYT.bsf
Initial commit
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lpm_bustri_BYT.cmp
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lpm_bustri_BYT.inc
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lpm_bustri_BYT.qip
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lpm_bustri_BYT.vhd
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lpm_bustri_LONG.bsf
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lpm_bustri_LONG.cmp
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lpm_bustri_LONG.inc
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lpm_bustri_LONG.qip
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lpm_bustri_LONG.vhd
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lpm_bustri_WORD.bsf
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lpm_bustri_WORD.cmp
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lpm_bustri_WORD.inc
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lpm_bustri_WORD.qip
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lpm_bustri_WORD.vhd
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lpm_counter0.bsf
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lpm_counter0.cmp
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lpm_counter0.qip
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lpm_counter0.vhd
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lpm_counter1.bsf
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lpm_counter1.cmp
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lpm_counter1.inc
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lpm_counter1.qip
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lpm_counter1.tdf
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lpm_latch0.bsf
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lpm_latch0.cmp
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lpm_latch0.qip
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lpm_latch0.vhd
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lpm_mux0.bsf
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lpm_mux0.cmp
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lpm_mux0.inc
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lpm_mux0.qip
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lpm_mux0.tdf
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lpm_mux1.bsf
Sync with Fredi's source tree 15/04/2017
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lpm_mux1.cmp
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lpm_mux1.inc
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lpm_mux1.qip
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lpm_mux1.tdf
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lpm_shiftreg0.bsf
Sync with Fredi's source tree 13/06/2015
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lpm_shiftreg0.cmp
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lpm_shiftreg0.inc
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lpm_shiftreg0.qip
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lpm_shiftreg0.tdf
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README.md
Create README.md
2018-04-09 17:33:13 +02:00

README.md

These FPGA's sources can be built with Quartus 9.1.

This repository should be only used to sync(like a kind of mirror) with Fredi's source tree.

Please for further development create a new repository and merge from here.