51 lines
1.8 KiB
VHDL
51 lines
1.8 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity flexbus_register is
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generic
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(
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reg_width : integer := 11;
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match_address : std_logic_vector(31 downto 0) := (others => '0');
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match_mask : std_logic_vector(31 downto 0) := (others => '1');
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match_fbcs : integer := 0
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);
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port
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(
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clk : in std_logic;
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fb_addr : in std_logic_vector(31 downto 0);
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fb_data : inout std_logic_vector(31 downto 0);
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fb_cs : in std_logic_vector(5 downto 1);
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fb_wr_n : in std_logic;
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fb_ta_n : out std_logic;
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reg_value : inout std_logic_vector(reg_width - 1 downto 0);
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cs : out std_logic := '0'
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);
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end entity flexbus_register;
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architecture rtl of flexbus_register is
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signal fbcs_match : std_logic;
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signal address_match : std_logic;
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begin
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fbcs_match <= '1' when fb_cs(match_fbcs) = '1' else '0';
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address_match <= '1' when (fb_addr and match_mask) = (match_address and match_mask) else '0';
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p_register_access : process(all)
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begin
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if rising_edge(clk) then
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if fbcs_match = '1' and address_match = '1' then
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cs <= '1';
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if fb_wr_n = '0' then -- write access
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reg_value <= fb_data(reg_width - 1 downto 0);
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else -- read access
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fb_data(reg_width - 1 downto 0) <= reg_value;
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fb_ta_n <= '0';
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end if;
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else
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fb_data <= (others => 'Z');
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fb_ta_n <= 'Z';
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cs <= '0';
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end if;
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end if;
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end process p_register_access;
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end architecture rtl; |