75 lines
2.1 KiB
Verilog
75 lines
2.1 KiB
Verilog
// Copyright (C) 1991-2009 Altera Corporation
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// Your use of Altera Corporation's design tools, logic functions
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// and other software and tools, and its AMPP partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License
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// Subscription Agreement, Altera MegaCore Function License
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// Agreement, or other applicable license agreement, including,
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// without limitation, that your use is for the sole purpose of
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// programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the
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// applicable agreement for further details.
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// PROGRAM "Quartus II 64-Bit"
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// VERSION "Version 9.1 Build 222 10/21/2009 SJ Full Version"
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// CREATED "Sat Mar 01 09:17:14 2014"
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module mux41(
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S0,
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D2,
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INH,
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D0,
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D1,
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D3,
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S1,
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Q
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);
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input S0;
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input D2;
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input INH;
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input D0;
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input D1;
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input D3;
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input S1;
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output Q;
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wire SYNTHESIZED_WIRE_18;
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wire SYNTHESIZED_WIRE_19;
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wire SYNTHESIZED_WIRE_20;
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wire SYNTHESIZED_WIRE_21;
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wire SYNTHESIZED_WIRE_22;
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wire SYNTHESIZED_WIRE_13;
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wire SYNTHESIZED_WIRE_14;
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wire SYNTHESIZED_WIRE_15;
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wire SYNTHESIZED_WIRE_16;
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assign SYNTHESIZED_WIRE_18 = ~S0;
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assign SYNTHESIZED_WIRE_21 = ~SYNTHESIZED_WIRE_18;
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assign SYNTHESIZED_WIRE_13 = SYNTHESIZED_WIRE_19 & SYNTHESIZED_WIRE_20 & SYNTHESIZED_WIRE_18 & D0;
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assign SYNTHESIZED_WIRE_14 = SYNTHESIZED_WIRE_19 & SYNTHESIZED_WIRE_20 & SYNTHESIZED_WIRE_21 & D1;
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assign SYNTHESIZED_WIRE_15 = SYNTHESIZED_WIRE_19 & SYNTHESIZED_WIRE_22 & SYNTHESIZED_WIRE_18 & D2;
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assign SYNTHESIZED_WIRE_16 = SYNTHESIZED_WIRE_19 & SYNTHESIZED_WIRE_22 & SYNTHESIZED_WIRE_21 & D3;
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assign Q = SYNTHESIZED_WIRE_13 | SYNTHESIZED_WIRE_14 | SYNTHESIZED_WIRE_15 | SYNTHESIZED_WIRE_16;
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assign SYNTHESIZED_WIRE_19 = ~INH;
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assign SYNTHESIZED_WIRE_20 = ~S1;
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assign SYNTHESIZED_WIRE_22 = ~SYNTHESIZED_WIRE_20;
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endmodule
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