111 lines
3.5 KiB
VHDL
111 lines
3.5 KiB
VHDL
-- megafunction wizard: %LPM_LATCH%
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-- GENERATION: STANDARD
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-- VERSION: WM1.0
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-- MODULE: lpm_latch
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-- ============================================================
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-- File Name: lpm_latch0.vhd
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-- Megafunction Name(s):
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-- lpm_latch
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--
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-- Simulation Library Files(s):
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-- lpm
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-- ============================================================
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-- ************************************************************
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-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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--
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-- 8.1 Build 163 10/28/2008 SJ Web Edition
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-- ************************************************************
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--Copyright (C) 1991-2008 Altera Corporation
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--Your use of Altera Corporation's design tools, logic functions
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--and other software and tools, and its AMPP partner logic
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--functions, and any output files from any of the foregoing
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--(including device programming or simulation files), and any
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--associated documentation or information are expressly subject
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--to the terms and conditions of the Altera Program License
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--Subscription Agreement, Altera MegaCore Function License
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--Agreement, or other applicable license agreement, including,
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--without limitation, that your use is for the sole purpose of
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--programming logic devices manufactured by Altera and sold by
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--Altera or its authorized distributors. Please refer to the
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--applicable agreement for further details.
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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LIBRARY lpm;
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USE lpm.all;
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ENTITY lpm_latch0 IS
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PORT
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(
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data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
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gate : IN STD_LOGIC ;
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q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
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);
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END lpm_latch0;
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ARCHITECTURE SYN OF lpm_latch0 IS
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SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
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COMPONENT lpm_latch
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GENERIC (
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lpm_type : STRING;
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lpm_width : NATURAL
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);
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PORT (
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q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
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data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
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gate : IN STD_LOGIC
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);
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END COMPONENT;
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BEGIN
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q <= sub_wire0(31 DOWNTO 0);
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lpm_latch_component : lpm_latch
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GENERIC MAP (
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lpm_type => "LPM_LATCH",
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lpm_width => 32
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)
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PORT MAP (
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data => data,
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gate => gate,
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q => sub_wire0
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);
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END SYN;
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-- ============================================================
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-- CNX file retrieval info
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-- ============================================================
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-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
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-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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-- Retrieval info: PRIVATE: aclr NUMERIC "0"
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-- Retrieval info: PRIVATE: aset NUMERIC "0"
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-- Retrieval info: PRIVATE: nBit NUMERIC "32"
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-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_LATCH"
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-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
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-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
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-- Retrieval info: USED_PORT: gate 0 0 0 0 INPUT NODEFVAL gate
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-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
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-- Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
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-- Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
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-- Retrieval info: CONNECT: @gate 0 0 0 0 gate 0 0 0 0
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-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
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-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_latch0.vhd TRUE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_latch0.inc FALSE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_latch0.cmp TRUE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_latch0.bsf TRUE FALSE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_latch0_inst.vhd FALSE
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-- Retrieval info: LIB_FILE: lpm
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