Files
FPGA_Config/FPGA_by_Fredi/.sopc_builder/preferences.xml
David Gálvez b2d17efff1 Sync with Fredi's source tree 15/04/2017
IDE and Blitter work.
2018-04-09 17:21:35 +02:00

19 lines
439 B
XML

<?xml version="1.0" encoding="UTF-8"?>
<preferences>
<systemtable>
<columns>
<connections preferredWidth="30" />
<export visible="0" />
<irq preferredWidth="34" />
</columns>
</systemtable>
<clocktable>
<columns>
<clockname preferredWidth="138" />
<clocksource preferredWidth="138" />
<frequency preferredWidth="119" />
</columns>
</clocktable>
<window width="900" height="600" x="0" y="0" />
</preferences>