53 lines
1.7 KiB
VHDL
53 lines
1.7 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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-- Entity Declaration
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entity dsp is
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port
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(
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CLK33M : in std_logic;
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MAIN_CLK : in std_logic;
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nFB_OE : in std_logic;
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nFB_WR : in std_logic;
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nFB_CS1 : in std_logic;
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nFB_CS2 : in std_logic;
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FB_SIZE0 : in std_logic;
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FB_SIZE1 : in std_logic;
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nFB_BURST : in std_logic;
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FB_ADR : in std_logic_vector(31 downto 0);
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nRSTO : in std_logic;
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nFB_CS3 : in std_logic;
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nSRCS : inout std_logic;
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nSRBLE : out std_logic;
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nSRBHE : out std_logic;
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nSRWE : out std_logic;
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nSROE : out std_logic;
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DSP_INT : out std_logic;
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DSP_TA : out std_logic;
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fb_ad_in : in std_logic_vector(31 downto 0);
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fb_ad_out : out std_logic_vector(31 downto 0);
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IO : inout std_logic_vector(17 downto 0);
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SRD : inout std_logic_vector(15 downto 0)
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);
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end dsp;
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-- Architecture Body
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architecture rtl of dsp is
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begin
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nSRCS <= '0' when nFB_CS2 = '0' and FB_ADR(27 downto 24) = x"4" else '1'; --nFB_CS3;
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nSRBHE <= '0' when FB_ADR(0 downto 0) = "0" else '1';
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nSRBLE <= '1' when FB_ADR(0 downto 0) = "0" and FB_SIZE1 = '0' and FB_SIZE0 = '1' else '0';
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nSRWE <= '0' when nFB_WR = '0' and nSRCS = '0' and MAIN_CLK = '0' else '1';
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nSROE <= '0' when nFB_OE = '0' and nSRCS = '0' else '1';
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DSP_INT <= '0';
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DSP_TA <= '0';
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IO(17 downto 0) <= FB_ADR(18 downto 1);
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SRD(15 downto 0) <= fb_ad_in(31 downto 16) when nFB_WR = '0' and nSRCS = '0' else (others => 'Z');
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-- fb_ad_out(31 downto 16) <= srd(15 DOWNTO 0 )when nFB_OE = '0' AND nSRCS = '0' ELSE (others => 'Z');
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fb_ad_out(31 downto 0) <= (others => 'Z'); -- otherwise we get a constant driver error
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end rtl;
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