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FPGA_Config/FPGA_30_11_2018/Video/lpm_fifo_dc0.inc
2025-09-02 14:32:05 +02:00

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--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
FUNCTION lpm_fifo_dc0
(
aclr,
data[127..0],
rdclk,
rdreq,
wrclk,
wrreq
)
RETURNS (
q[127..0],
wrusedw[10..0]
);