-- WARNING: Do NOT edit the input and output ports in this file in a text -- editor if you plan to continue editing the block that represents it in -- the Block Editor! File corruption is VERY likely to occur. -- Copyright (C) 1991-2010 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any output files from any of the foregoing -- (including device programming or simulation files), and any -- associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License -- Subscription Agreement, Altera MegaCore Function License -- Agreement, or other applicable license agreement, including, -- without limitation, that your use is for the sole purpose of -- programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the -- applicable agreement for further details. -- Generated by Quartus II Version 9.1 (Build Build 350 03/24/2010) -- Created on Sat Jan 15 11:06:17 2011 INCLUDE "lpm_bustri_WORD.inc"; INCLUDE "VIDEO/BLITTER/lpm_clshift384.INC"; INCLUDE "VIDEO/BLITTER/altsyncram0.INC"; INCLUDE "VIDEO/BLITTER/lpm_clshift144.inc"; --CONSTANT BL_SKEW_LF = 255; -- Title Statement (optional) TITLE "Blitter"; -- Parameters Statement (optional) -- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE! -- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE! -- Subdesign Section SUBDESIGN BLITTER ( -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! nRSTO : INPUT; MAIN_CLK : INPUT; FB_ALE : INPUT; nFB_WR : INPUT; nFB_OE : INPUT; FB_SIZE0 : INPUT; FB_SIZE1 : INPUT; VIDEO_RAM_CTR[15..0] : INPUT; BLITTER_ON : INPUT; FB_ADR[31..0] : INPUT; nFB_CS1 : INPUT; nFB_CS2 : INPUT; nFB_CS3 : INPUT; DDRCLK0 : INPUT; VDP_IN[63..0] : INPUT; BLITTER_DACK[4..0] : INPUT; SR_BLITTER_DACK : INPUT; BLITTER_RUN : OUTPUT; BLITTER_INT : OUTPUT; BLITTER_DOUT[127..0] : OUTPUT; BLITTER_ADR[31..0] : OUTPUT; BLITTER_SIG : OUTPUT; BLITTER_WR : OUTPUT; BLITTER_TA : OUTPUT; FB_AD[31..0] : BIDIR; -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! ) VARIABLE BYT :NODE; LONGLINE :NODE; W_ADR[18..0] :NODE; FB_16B[1..0] :NODE; W_A1 :DFFE; BLITTER_CS :NODE; BL_HRAM_CS :NODE; BL_HRAM_BE[1..0] :NODE; BL_HRAM_OUT[15..0] :NODE; BL_DPRAM_OUT[15..0] :NODE; BL_SRC_X_INC_CS :NODE; BL_SRC_X_INC[15..0] :DFFE; SRC_XINC_NODE[31..0] :NODE; BL_SRC_Y_INC_CS :NODE; BL_SRC_Y_INC[15..0] :DFFE; SRC_YINC_NODE[31..0] :NODE; BL_ENDMASK1_CS :NODE; BL_ENDMASK1[15..0] :DFFE; BL_ENDMASK2_CS :NODE; BL_ENDMASK2[15..0] :DFFE; BL_ENDMASK3_CS :NODE; BL_ENDMASK3[15..0] :DFFE; BL_SRC_ADRH_CS :NODE; BL_SRC_ADRL_CS :NODE; BL_SRC_ADR[31..0] :DFFE; SRC_IADRH_CS :NODE; SRC_IADRL_CS :NODE; SRC_IADR[31..0] :DFF; SRC_IADR_CLR :NODE; SIINC :NODE; SRC_ADR_NODE[31..0] :NODE; BL_DST_X_INC_CS :NODE; BL_DST_X_INC[15..0] :DFFE; DST_XINC_NODE[31..0] :NODE; BL_DST_Y_INC_CS :NODE; BL_DST_Y_INC[15..0] :DFFE; DST_YINC_NODE[31..0] :NODE; BL_DST_ADRH_CS :NODE; BL_DST_ADRL_CS :NODE; BL_DST_ADR[31..0] :DFFE; DST_IADRH_CS :NODE; DST_IADRL_CS :NODE; DST_IADR[31..0] :DFF; DST_IADR_CLR :NODE; DST_ADR_NODE[31..0] :NODE; DIINC :NODE; BL_X_CNT_CS :NODE; BL_X_CNT[15..0] :DFFE; X_CNT_NODE[15..0] :NODE; BL_Y_CNT_CS :NODE; BL_Y_CNT[15..0] :DFFE; BL_HOP_CS :NODE; BL_HOP[7..0] :DFFE; BL_OP[7..0] :DFFE; BL_LN_CS :NODE; LN7CLR :NODE; BL_LN[7..0] :DFFE; BL_SKEW[7..0] :DFFE; -- barell shifter DIST_RIGHT[8..0] :NODE; BL_BS_SKEW[7..0] :NODE; BL_BSIN[383..0] :NODE; BL_BSOUT[383..0] :NODE; SHIFT_DIR :NODE; BL_SRC_BUF1[127..0] :DFFE; BL_SRC_BUF2[127..0] :DFFE; BL_SRC_BUF3[127..0] :DFFE; BL_DST_BUFRD[127..0] :DFFE; BL_READ_DST :NODE; -- LATCH SIGNAL DST BUF RD BL_READ_SRC :NODE; -- LATCH SIGNAL SRC BUF SRC_READ :NODE; -- FREIGABE LATCH SIGNAL NOT_DST_READ :NODE; WREN_B :NODE; -- WR ENA HALFTONE RAM X_INDEX_CS :NODE; X_INDEX[15..0] :DFF; -- LAUFZEIGER X COUNT X_INDEX_CLR :NODE; Y_INDEX_CS :NODE; Y_INDEX[15..0] :DFF; -- LAUFZEIGER Y COUNT Y_INDEX_CLR :NODE; LINE_NR[3..0] :NODE; XIINC :NODE; -- INC INDEX SPALTE YIINC :NODE; -- INC INDEX ZEILE ZIINC :NODE; -- INC ADRESSEN ZEILENUMBRUCH ZYINC :NODE; -- KORREKTUR ADRESSEN WENN FERTIG HOP_OUT[127..0] :NODE; OP_OUT[127..0] :NODE; ENDMASK1_SHIFT[7..0] :NODE; ENDMASK2_SHIFT[7..0] :NODE; ENDMASK12_IN[143..0] :NODE; ENDMASK12_OUT[143..0] :NODE; ENDMASK23_IN[143..0] :NODE; ENDMASK23_OUT[143..0] :NODE; ENDMASK123[127..0] :NODE; ENDMASKEND[15..0] :NODE; SRC_DDR_ADR[31..0] :NODE; DST_DDR_ADR[31..0] :NODE; BLITTER_REQ :DFF; -- MAIN STATE MACHINE BL_SM :MACHINE WITH STATES(START,NEW_LINE,NEW_LINEW,RDSRC0,RDSRC1,RDSRC2,RDDST,WRDSTW1,WRDST,TESTZEILENENDE,TESTFERTIG,FERTIG); BEGIN -- BYT UND WORD SELECT 16 BIT BYT = !FB_SIZE1 & FB_SIZE0; LONGLINE = !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG OR LINE W_A1.CLK = MAIN_CLK; W_A1.ENA = FB_ALE # BLITTER_TA & LONGLINE; W_A1 = FB_ADR[1] & FB_ALE # BLITTER_TA & LONGLINE; -- A1 HOCHZÄHLEN BEI LONG UND LINE WEGEN BURST W_ADR[18..1] = FB_ADR[19..2]; W_ADR0 = W_A1; FB_16B0 = FB_ADR[0]==0; -- wenn ADR==0 FB_16B1 = FB_ADR[0]==1 # !BYT; -- wenn ADR==1 or NOT BYT -- BLITTER CS BLITTER_CS = !nFB_CS1 & FB_ADR[19..7]==H"1F14"; -- FFFF8A00-7F BLITTER_TA = BLITTER_CS; -- REGISTER -- HALFTON RAM BL_HRAM_CS = !nFB_CS1 & FB_ADR[19..5]==H"7C50"; -- $F8A00-1F.w BL_HRAM_BE1 = BL_HRAM_CS & FB_16B0; BL_HRAM_BE0 = BL_HRAM_CS & FB_16B1; WREN_B = B"0"; LINE_NR[] = ((Y_INDEX[3..0] & !BL_DST_Y_INC15) # (!Y_INDEX[3..0] & BL_DST_Y_INC15)); (BL_DPRAM_OUT[],BL_HRAM_OUT[]) = altsyncram0(W_ADR[3..0],LINE_NR[],BL_HRAM_BE[],MAIN_CLK,DDRCLK0,FB_AD[31..16],FB_AD[31..16],BL_HRAM_CS & !nFB_WR,WREN_B); -- SRC X INC BL_SRC_X_INC[].CLK = MAIN_CLK; BL_SRC_X_INC[] = FB_AD[31..16]; BL_SRC_X_INC_CS = !nFB_CS1 & W_ADR[]==H"7C510"; -- $F8A20.w BL_SRC_X_INC[15..8].ENA = BL_SRC_X_INC_CS & !nFB_WR & FB_16B0; BL_SRC_X_INC[7..0].ENA = BL_SRC_X_INC_CS & !nFB_WR & FB_16B1; SRC_XINC_NODE[] = (H"FFFF0000" & BL_SRC_X_INC15) # (H"0000",BL_SRC_X_INC[]); -- ERWEITERN AUF 32 BIT -- SRC Y INC BL_SRC_Y_INC[].CLK = MAIN_CLK; BL_SRC_Y_INC[] = FB_AD[31..16]; BL_SRC_Y_INC_CS = !nFB_CS1 & W_ADR[]==H"7C511"; -- $F8A22.w BL_SRC_Y_INC[15..8].ENA = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B0; BL_SRC_Y_INC[7..0].ENA = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B1; SRC_YINC_NODE[] = (H"FFFF0000" & BL_SRC_Y_INC15) # (H"0000",BL_SRC_Y_INC[]); -- ERWEITERN AUF 32 BIT -- SRC ADR HIGH BL_SRC_ADR[].CLK = MAIN_CLK; BL_SRC_ADR[31..16] = FB_AD[31..16]; BL_SRC_ADRH_CS = !nFB_CS1 & W_ADR[]==H"7C512"; -- $F8A24.w BL_SRC_ADR[31..24].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B0; BL_SRC_ADR[23..16].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B1; -- SRC ADR LOW BL_SRC_ADR[].CLK = MAIN_CLK; BL_SRC_ADR[15..0] = FB_AD[31..16]; BL_SRC_ADRL_CS = !nFB_CS1 & W_ADR[]==H"7C513"; -- $F8A26.w BL_SRC_ADR[15..8].ENA = BL_SRC_ADRL_CS & !nFB_WR & FB_16B0; BL_SRC_ADR[7..0].ENA = BL_SRC_ADRL_CS & !nFB_WR & FB_16B1; SRC_IADR[].CLK = DDRCLK0; SRC_IADRH_CS = !nFB_CS1 & W_ADR[]==H"7C520"; -- $F8A40.w SRC_IADRL_CS = !nFB_CS1 & W_ADR[]==H"7C521"; -- $F8A42.w SRC_IADR_CLR = (BL_SRC_ADRL_CS # BL_SRC_ADRH_CS) & !nFB_WR; -- LÖSCHEN BEI WRITE SRC_IADR[] = (SRC_IADR[] + (((8 * SRC_XINC_NODE[]) & SIINC) + (SRC_YINC_NODE[] & ZYINC) + ((((0,BL_X_CNT[]) - (0,X_INDEX[]) - 8) * SRC_XINC_NODE[]) & ZIINC)) & SRC_READ) & !SRC_IADR_CLR; SRC_ADR_NODE[] = BL_SRC_ADR[] + SRC_IADR[]; -- ZUGRIFFSADRESSE THEORETISCH -- ENDMASK 1 BL_ENDMASK1[].CLK = MAIN_CLK; BL_ENDMASK1[] = FB_AD[31..16]; BL_ENDMASK1_CS = !nFB_CS1 & W_ADR[]==H"7C514"; -- $F8A28.w BL_ENDMASK1[15..8].ENA = BL_ENDMASK1_CS & !nFB_WR & FB_16B0; BL_ENDMASK1[7..0].ENA = BL_ENDMASK1_CS & !nFB_WR & FB_16B1; -- ENDMASK 2 BL_ENDMASK2[].CLK = MAIN_CLK; BL_ENDMASK2[] = FB_AD[31..16]; BL_ENDMASK2_CS = !nFB_CS1 & W_ADR[]==H"7C515"; -- $F8A2A.w BL_ENDMASK2[15..8].ENA = BL_ENDMASK2_CS & !nFB_WR & FB_16B0; BL_ENDMASK2[7..0].ENA = BL_ENDMASK2_CS & !nFB_WR & FB_16B1; -- ENDMASK 3 BL_ENDMASK3[].CLK = MAIN_CLK; BL_ENDMASK3[] = FB_AD[31..16]; BL_ENDMASK3_CS = !nFB_CS1 & W_ADR[]==H"7C516"; -- $F8A2C.w BL_ENDMASK3[15..8].ENA = BL_ENDMASK3_CS & !nFB_WR & FB_16B0; BL_ENDMASK3[7..0].ENA = BL_ENDMASK3_CS & !nFB_WR & FB_16B1; -- DST X INC BL_DST_X_INC[].CLK = MAIN_CLK; BL_DST_X_INC[] = FB_AD[31..16]; BL_DST_X_INC_CS = !nFB_CS1 & W_ADR[]==H"7C517"; -- $F8A2E.w BL_DST_X_INC[15..8].ENA = BL_DST_X_INC_CS & !nFB_WR & FB_16B0; BL_DST_X_INC[7..0].ENA = BL_DST_X_INC_CS & !nFB_WR & FB_16B1; DST_XINC_NODE[] = (H"FFFF0000" & BL_DST_X_INC15) # (H"0000",BL_DST_X_INC[]); -- ERWEITERN AUF 32 BIT -- DST Y INC BL_DST_Y_INC[].CLK = MAIN_CLK; BL_DST_Y_INC[] = FB_AD[31..16]; BL_DST_Y_INC_CS = !nFB_CS1 & W_ADR[]==H"7C518"; -- $F8A30.w BL_DST_Y_INC[15..8].ENA = BL_DST_Y_INC_CS & !nFB_WR & FB_16B0; BL_DST_Y_INC[7..0].ENA = BL_DST_Y_INC_CS & !nFB_WR & FB_16B1; DST_YINC_NODE[] = (H"FFFF0000" & BL_DST_Y_INC15) # (H"0000",BL_DST_Y_INC[]); -- ERWEITERN AUF 32 BIT -- DST ADR HIGH BL_DST_ADR[].CLK = MAIN_CLK; BL_DST_ADR[31..16] = FB_AD[31..16]; BL_DST_ADRH_CS = !nFB_CS1 & W_ADR[]==H"7C519"; -- $F8A32.w BL_DST_ADR[31..24].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B0; BL_DST_ADR[23..16].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B1; -- DST ADR LOW BL_DST_ADR[].CLK = MAIN_CLK; BL_DST_ADR[15..0] = FB_AD[31..16]; BL_DST_ADRL_CS = !nFB_CS1 & W_ADR[]==H"7C51A"; -- $F8A34.w BL_DST_ADR[15..8].ENA = BL_DST_ADRL_CS & !nFB_WR & FB_16B0; BL_DST_ADR[7..0].ENA = BL_DST_ADRL_CS & !nFB_WR & FB_16B1; DST_IADR[].CLK = DDRCLK0; DST_IADRH_CS = !nFB_CS1 & W_ADR[]==H"7C522"; -- $F8A44.w DST_IADRL_CS = !nFB_CS1 & W_ADR[]==H"7C523"; -- $F8A46.w DST_IADR_CLR = (BL_DST_ADRL_CS # BL_DST_ADRH_CS) & !nFB_WR; -- LÖSCHEN BEI WRITE DST_IADR[] = (DST_IADR[] + ((8 * DST_XINC_NODE[]) & DIINC) + (DST_YINC_NODE[] & ZYINC) + ((((0,BL_X_CNT[]) - (0,X_INDEX[])) * DST_XINC_NODE[]) & ZIINC)) & !DST_IADR_CLR; DST_ADR_NODE[] = BL_DST_ADR[] + DST_IADR[]; -- ZUGRIFFSADRESSE THEORETISCH -- X COUNT BL_X_CNT[].CLK = MAIN_CLK; BL_X_CNT[] = FB_AD[31..16]; BL_X_CNT_CS = !nFB_CS1 & W_ADR[]==H"7C51B"; -- $F8A36.w BL_X_CNT[15..8].ENA = BL_X_CNT_CS & !nFB_WR & FB_16B0; BL_X_CNT[7..0].ENA = BL_X_CNT_CS & !nFB_WR & FB_16B1; X_INDEX[].CLK = DDRCLK0; X_INDEX_CS = !nFB_CS1 & W_ADR[]==H"7C524"; -- $F8A48.w X_INDEX_CLR = BL_X_CNT_CS & !nFB_WR; -- LÖSCHEN BEI WRITE X_INDEX[] = (X_INDEX[] + (8 & XIINC) + ((BL_X_CNT[] - X_INDEX[]) & ZIINC)) & !X_INDEX_CLR; X_CNT_NODE[] = X_INDEX[] - ((0,DST_ADR_NODE[3..1]) & (X_INDEX[]!=0));-- EFFEKTIV GELESENE -- Y COUNT BL_Y_CNT[].CLK = MAIN_CLK; BL_Y_CNT[] = FB_AD[31..16]; BL_Y_CNT_CS = !nFB_CS1 & W_ADR[]==H"7C51C"; -- $F8A38.w BL_Y_CNT[15..8].ENA = BL_Y_CNT_CS & !nFB_WR & FB_16B0; BL_Y_CNT[7..0].ENA = BL_Y_CNT_CS & !nFB_WR & FB_16B1; Y_INDEX[].CLK = DDRCLK0; Y_INDEX_CS = !nFB_CS1 & W_ADR[]==H"7C525"; -- $F8A4A.w Y_INDEX_CLR = BL_Y_CNT_CS & !nFB_WR; -- LÖSCHEN BEI WRITE Y_INDEX[] = (Y_INDEX[] + (1 & YIINC)) & !Y_INDEX_CLR; -- HOP LOGIC BL_HOP[].CLK = MAIN_CLK; BL_HOP[] = FB_AD[31..24]; BL_HOP_CS = !nFB_CS1 & W_ADR[]==H"7C51D"; -- $F8A3A.w BL_HOP[7..0].ENA = BL_HOP_CS & !nFB_WR & FB_16B0; -- $F8A3A -- OP LOGIC BL_OP[].CLK = MAIN_CLK; BL_OP[] = FB_AD[23..16]; BL_OP[7..0].ENA = BL_HOP_CS & !nFB_WR & FB_16B1; -- $F8A3B -- LINE NUMBER BYT BL_LN[].CLK = MAIN_CLK; BL_LN[6..0] = FB_AD[30..24]; BL_LN7 = FB_AD31 & !LN7CLR; -- BUSY HOG UND SMUDGE BL_LN_CS = !nFB_CS1 & W_ADR[]==H"7C51E"; -- $F8A3C.w BL_LN[].ENA = BL_LN_CS & !nFB_WR & FB_16B0; -- $F8A3C BL_LN7.ENA = LN7CLR; -- SKEW BYT BL_SKEW[].CLK = MAIN_CLK; BL_SKEW[] = FB_AD[23..16]; BL_SKEW[].ENA = BL_LN_CS & !nFB_WR & FB_16B1; -- $F8A3D --- REGISTER OUT FB_AD[31..16] = lpm_bustri_WORD( BL_HRAM_CS & BL_DPRAM_OUT[] # BL_SRC_X_INC_CS & BL_SRC_X_INC[] # BL_SRC_Y_INC_CS & BL_SRC_Y_INC[] # BL_SRC_ADRH_CS & SRC_ADR_NODE[31..16] # BL_SRC_ADRL_CS & SRC_ADR_NODE[15..0] # BL_ENDMASK1_CS & BL_ENDMASK1[] # BL_ENDMASK2_CS & BL_ENDMASK2[] # BL_ENDMASK3_CS & BL_ENDMASK3[] # BL_DST_X_INC_CS & BL_DST_X_INC[] # BL_DST_Y_INC_CS & BL_DST_Y_INC[] # BL_DST_ADRH_CS & DST_ADR_NODE[31..16] # BL_DST_ADRL_CS & DST_ADR_NODE[15..0] # BL_X_CNT_CS & (BL_X_CNT[]-X_INDEX[]) # BL_Y_CNT_CS & (BL_Y_CNT[]-Y_INDEX[]) # BL_HOP_CS & (BL_HOP[],BL_OP[]) # BL_LN_CS & (BL_LN[7..4],Y_INDEX[3..0],BL_SKEW[]) # SRC_IADRH_CS & SRC_IADR[31..16] # SRC_IADRL_CS & SRC_IADR[15..0] # DST_IADRH_CS & DST_IADR[31..16] # DST_IADRL_CS & DST_IADR[15..0] # X_INDEX_CS & X_INDEX[] # Y_INDEX_CS & Y_INDEX[] ,BLITTER_CS & !nFB_OE); -- FFFF8A00-7F -------------------------------------------------------------------------------------- -- SRC BUFFER LADEN BL_SRC_BUF1[].CLK = DDRCLK0; BL_SRC_BUF1[127..64].ENA = BLITTER_DACK1 & BL_READ_SRC; BL_SRC_BUF1[63..0].ENA = BLITTER_DACK0 & BL_READ_SRC; BL_SRC_BUF1[] = (VDP_IN[],VDP_IN[]); BL_SRC_BUF2[].CLK = DDRCLK0; BL_SRC_BUF2[127..64].ENA = BLITTER_DACK1 & BL_READ_SRC; BL_SRC_BUF2[63..0].ENA = BLITTER_DACK0 & BL_READ_SRC; BL_SRC_BUF2[] = BL_SRC_BUF1[]; BL_SRC_BUF3[].CLK = DDRCLK0; BL_SRC_BUF3[127..64].ENA = BLITTER_DACK1 & BL_READ_SRC; BL_SRC_BUF3[63..0].ENA = BLITTER_DACK0 & BL_READ_SRC; BL_SRC_BUF3[] = BL_SRC_BUF2[]; -- ZUORDNUNG --------- IF BL_SRC_X_INC15 THEN -- WENN NEGATIV -> REIHENFOLGE KEHREN CASE BL_HOP[7..4] IS -- SPIEGELN? WHEN H"0" => -- LINE WEISE BL_BSIN[127..0] = BL_SRC_BUF3[]; BL_BSIN[255..128] = BL_SRC_BUF2[]; BL_BSIN[383..256] = BL_SRC_BUF1[]; WHEN H"1" => --- BIT WEISE BL_BSIN[0..127] = BL_SRC_BUF3[]; BL_BSIN[128..255] = BL_SRC_BUF2[]; BL_BSIN[256..383] = BL_SRC_BUF1[]; WHEN H"2" => -- BYT WEISE BL_BSIN[127..0] = (BL_SRC_BUF3[7..0],BL_SRC_BUF3[15..8],BL_SRC_BUF3[23..16],BL_SRC_BUF3[31..24],BL_SRC_BUF3[39..32],BL_SRC_BUF3[47..40],BL_SRC_BUF3[55..48],BL_SRC_BUF3[63..56],BL_SRC_BUF3[71..64],BL_SRC_BUF3[79..72],BL_SRC_BUF3[87..80],BL_SRC_BUF3[95..88],BL_SRC_BUF3[103..96],BL_SRC_BUF3[111..104],BL_SRC_BUF3[119..112],BL_SRC_BUF3[127..120]); BL_BSIN[255..128] = (BL_SRC_BUF2[7..0],BL_SRC_BUF2[15..8],BL_SRC_BUF2[23..16],BL_SRC_BUF2[31..24],BL_SRC_BUF2[39..32],BL_SRC_BUF2[47..40],BL_SRC_BUF2[55..48],BL_SRC_BUF2[63..56],BL_SRC_BUF2[71..64],BL_SRC_BUF2[79..72],BL_SRC_BUF2[87..80],BL_SRC_BUF2[95..88],BL_SRC_BUF2[103..96],BL_SRC_BUF2[111..104],BL_SRC_BUF2[119..112],BL_SRC_BUF2[127..120]); BL_BSIN[383..256] = (BL_SRC_BUF1[7..0],BL_SRC_BUF1[15..8],BL_SRC_BUF1[23..16],BL_SRC_BUF1[31..24],BL_SRC_BUF1[39..32],BL_SRC_BUF1[47..40],BL_SRC_BUF1[55..48],BL_SRC_BUF1[63..56],BL_SRC_BUF1[71..64],BL_SRC_BUF1[79..72],BL_SRC_BUF1[87..80],BL_SRC_BUF1[95..88],BL_SRC_BUF1[103..96],BL_SRC_BUF1[111..104],BL_SRC_BUF1[119..112],BL_SRC_BUF1[127..120]); WHEN H"3" => -- WORD WEISE BL_BSIN[127..0] = (BL_SRC_BUF3[15..0],BL_SRC_BUF3[31..16],BL_SRC_BUF3[47..32],BL_SRC_BUF3[63..48],BL_SRC_BUF3[79..64],BL_SRC_BUF3[95..80],BL_SRC_BUF3[111..96],BL_SRC_BUF3[127..112]); BL_BSIN[255..128] = (BL_SRC_BUF2[15..0],BL_SRC_BUF2[31..16],BL_SRC_BUF2[47..32],BL_SRC_BUF2[63..48],BL_SRC_BUF2[79..64],BL_SRC_BUF2[95..80],BL_SRC_BUF2[111..96],BL_SRC_BUF2[127..112]); BL_BSIN[383..256] = (BL_SRC_BUF1[15..0],BL_SRC_BUF1[31..16],BL_SRC_BUF1[47..32],BL_SRC_BUF1[63..48],BL_SRC_BUF1[79..64],BL_SRC_BUF1[95..80],BL_SRC_BUF1[111..96],BL_SRC_BUF1[127..112]); WHEN H"4" => -- LONG WEISE BL_BSIN[127..0] = (BL_SRC_BUF3[31..0],BL_SRC_BUF3[63..32],BL_SRC_BUF3[95..64],BL_SRC_BUF3[127..96]); BL_BSIN[255..128] = (BL_SRC_BUF2[31..0],BL_SRC_BUF2[63..32],BL_SRC_BUF2[95..64],BL_SRC_BUF2[127..96]); BL_BSIN[383..256] = (BL_SRC_BUF1[31..0],BL_SRC_BUF1[63..32],BL_SRC_BUF1[95..64],BL_SRC_BUF1[127..96]); WHEN OTHERS => -- LINE WEISE BL_BSIN[127..0] = BL_SRC_BUF3[]; BL_BSIN[255..128] = BL_SRC_BUF2[]; BL_BSIN[383..256] = BL_SRC_BUF1[]; END CASE; ELSE -- SONST NORMAL BEI VORWÄRTS BL_BSIN[127..0] = BL_SRC_BUF1[]; BL_BSIN[255..128] = BL_SRC_BUF2[]; BL_BSIN[383..256] = BL_SRC_BUF3[]; END IF; -- DST BUFFER READ BL_DST_BUFRD[].CLK = DDRCLK0; BL_DST_BUFRD[127..64].ENA = BLITTER_DACK1 & BL_READ_DST; BL_DST_BUFRD[63..0].ENA = BLITTER_DACK0 & BL_READ_DST; BL_DST_BUFRD[] = (VDP_IN[],VDP_IN[]); -- barell shift ***************************************************************************** -- SOURCE SHIFT RIGHT = LPM_CSHIFT RIGTH ;SKEW SHIFT: IF FXRS==0 THEN RIGHT ELSE LEFT DIST_RIGHT[] = (16 * ((0,DST_ADR_NODE[3..1]) - (0,SRC_ADR_NODE[3..1]))) + (!BL_SKEW7 & (0,BL_SKEW[3..0])) - (BL_SKEW7 & (0,BL_SKEW[3..0])); IF DIST_RIGHT8 == 0 THEN BL_BS_SKEW[] = DIST_RIGHT[7..0]; -- LPM SHIFT RIGHT SHIFT_DIR = VCC; -- DIR = RIGHT else BL_BS_SKEW[] = !DIST_RIGHT[7..0] + 1; -- LPM SHIFT LEFT SHIFT_DIR = GND; -- DIR = LEFT end if; -- barell shifter: direction 0=links 1=rechts IN BEZUG AUF ausgabewert! BL_BSOUT[] = lpm_clshift384(BL_BSIN[], SHIFT_DIR , BL_BS_SKEW[]); -- wir brauchen 128bit -- HOP *************************************************************************************** CASE BL_HOP[1..0] IS WHEN H"0" => -- 12345678901234567890123456789012 HOP_OUT[] = H"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"; WHEN H"1" => HOP_OUT[] = (BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[]); WHEN H"2" => HOP_OUT[] = BL_BSOUT[255..128]; WHEN OTHERS => HOP_OUT[] = (BL_BSOUT[255..128] & (BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[])); END CASE; -- OP ***************************************************************************************** CASE BL_OP[3..0] IS WHEN H"0" => OP_OUT[] = H"0"; SRC_READ = B"0"; WHEN H"1" => OP_OUT[] = HOP_OUT[] & BL_DST_BUFRD[]; SRC_READ = BL_HOP1 # BL_HOP0; WHEN H"2" => OP_OUT[] = HOP_OUT[] & !BL_DST_BUFRD[]; SRC_READ = BL_HOP1 # BL_HOP0; WHEN H"3" => OP_OUT[] = HOP_OUT[]; SRC_READ = BL_HOP1 # BL_HOP0; WHEN H"4" => OP_OUT[] = !HOP_OUT[] & BL_DST_BUFRD[]; SRC_READ = BL_HOP1 # BL_HOP0; WHEN H"5" => OP_OUT[] = BL_DST_BUFRD[]; SRC_READ = B"0"; WHEN H"6" => OP_OUT[] = HOP_OUT[] $ BL_DST_BUFRD[]; SRC_READ = BL_HOP1 # BL_HOP0; WHEN H"7" => OP_OUT[] = HOP_OUT[] # BL_DST_BUFRD[]; SRC_READ = BL_HOP1 # BL_HOP0; WHEN H"8" => OP_OUT[] = !HOP_OUT[] & !BL_DST_BUFRD[]; SRC_READ = BL_HOP1 # BL_HOP0; WHEN H"9" => OP_OUT[] = !HOP_OUT[] $ BL_DST_BUFRD[]; SRC_READ = BL_HOP1 # BL_HOP0; WHEN H"A" => OP_OUT[] = !BL_DST_BUFRD[]; SRC_READ = B"0"; WHEN H"B" => OP_OUT[] = HOP_OUT[] # !BL_DST_BUFRD[]; SRC_READ = BL_HOP1 # BL_HOP0; WHEN H"C" => OP_OUT[] = !HOP_OUT[]; SRC_READ = BL_HOP1 # BL_HOP0; WHEN H"D" => OP_OUT[] = !HOP_OUT[] # BL_DST_BUFRD[]; SRC_READ = BL_HOP1 # BL_HOP0; WHEN H"E" => OP_OUT[] = !HOP_OUT[] # !BL_DST_BUFRD[]; SRC_READ = BL_HOP1 # BL_HOP0; WHEN OTHERS => -- 12345678901234567890123456789012 OP_OUT[] = H"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"; SRC_READ = B"0"; END CASE; ------------ ENDMASKEN SETZEN ****************************************************************************** ENDMASK1_SHIFT[3..0] = 0; ENDMASK2_SHIFT[3..0] = 0; IF BL_DST_X_INC15 THEN ---------------------------- RÜCKWÄRTS X_INC NEGATIV IF X_INDEX[]==0 THEN -- ENDE? ENDMASK2_SHIFT[7..4] = 9 - (0,(DST_ADR_NODE[3..1])) + (8 & (DST_ADR_NODE[3..1]==0)); -- JA ENDMASK 3 SETZEN ELSE ENDMASK2_SHIFT[7..4] = 0; -- NEIN -> ENDMASK 3 AUF ENDMASK2 SETZEN END IF; IF BL_X_CNT[]<=(X_CNT_NODE[] + 8) THEN -- SCHON ZEILENANFANG? ENDMASKEND[] = X_INDEX[] - BL_X_CNT[] + (0,(DST_ADR_NODE[3..1])); ENDMASK2_SHIFT[7..4] = 1 + (0,(ENDMASKEND[3..1])); -- JA: ENDMASK 3 SETZEN ELSE ENDMASK1_SHIFT[7..4] = 0; -- NEIN -> ENDMASK 3 AUF ENDMASK2 SETZEN END IF; ELSE ------------------------------------------- VORWÄRTS X_INC POSITIV IF X_INDEX[]==0 THEN -- ANFANG? ENDMASK1_SHIFT[7..4] = 1 + (0,(DST_ADR_NODE[3..1])); -- JA -> ENDMASK 1 SETZEN ELSE ENDMASK1_SHIFT[7..4] = 0; -- NEIN->ENDMASK1 AUF ENDMASK2 SETZEN END IF; IF BL_X_CNT[]<=(X_CNT_NODE[] + 8) THEN -- SCHON ZEILENENDE? ENDMASKEND[] = X_CNT_NODE[] + 8 - BL_X_CNT[]; ENDMASK2_SHIFT[7..4] = 1 + ENDMASKEND[3..0]; -- JA: ENDMASK 3 SETZEN ELSE ENDMASK2_SHIFT[7..4] = 0; -- NOCH NICHT AKTIV->ENDMASK 3 AUF ENDMASK2 SETZEN END IF; END IF; -- ENDMASKEN -- barell shifter 144 bit, direction 0 = links 1 = rechts -- 1234567890123456789012345678 ENDMASK12_IN[] = (BL_ENDMASK1[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[]); ENDMASK12_OUT[] = lpm_clshift144(ENDMASK12_IN[],1,ENDMASK1_SHIFT[]); -- IMMER rechts SCHIEBEN ENDMASK23_IN[] = (BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK3[]); ENDMASK23_OUT[] = lpm_clshift144(ENDMASK23_IN[],0,ENDMASK2_SHIFT[]); -- IMMER LINKS SCHIEBEN ENDMASK123[] = ENDMASK12_OUT[127..0] & ENDMASK23_OUT[143..16]; BLITTER_DOUT[] = ((ENDMASK123[] & OP_OUT[]) # (!ENDMASK123[] & BL_DST_BUFRD[])); NOT_DST_READ = ((BL_OP[3..0]==H"0") # (BL_OP[3..0]==H"3") # (BL_OP[3..0]==H"C") # (BL_OP[3..0]==H"F")) & (ENDMASK123[]==H"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"); -- STATE MACHINE **********************************************************************************---------------------------12345678901234567890123456789012 BLITTER_RUN = BLITTER_ON; -- BLITTER IST DA! BLITTER_ADR[3..0] = H"0"; -- IMMER LINE SRC_DDR_ADR[] = (SRC_ADR_NODE[] - (0,(16 & BL_SRC_X_INC15))); -- WENN RÜCKWÄRTS NEXT ADRESS SRC DST_DDR_ADR[] = (DST_ADR_NODE[] - (0,(16 & BL_DST_X_INC15))); -- WENN RÜCKWÄRTS NEXT ADRESS DST BLITTER_REQ.CLK = DDRCLK0; BLITTER_SIG = BLITTER_REQ & BLITTER_DACK[]==H"0"; -- BLITTER MAIN STATE MACHINE ----------------------------------------------- BL_SM.CLK = DDRCLK0; CASE BL_SM IS WHEN START => ------------------------- START IF BLITTER_ON & BL_LN7 & ((BL_X_CNT[] - X_CNT_NODE[])>0) & ((BL_Y_CNT[] - Y_INDEX[]) > 0) THEN BL_SM = NEW_LINE; ELSE BL_SM = START; END IF; WHEN NEW_LINE => ----------------------- NEU LINIE X_INDEX_CLR = VCC; -- LÖSCHEN BL_SM = RDSRC0; WHEN RDSRC0 => ------------------------ READ SRC1 IF SRC_READ THEN BLITTER_ADR[31..4] = SRC_DDR_ADR[31..4] - 1; BLITTER_REQ = VCC; BL_READ_SRC = VCC; -- LATCH UND SB1->SB2 IF BLITTER_DACK0 THEN BL_SM = RDSRC2; ELSE BL_SM = RDSRC1; END IF; ELSE BL_SM = RDDST; END IF; WHEN RDSRC1 => ------------------------ READ SRC1 IF SRC_READ THEN BLITTER_ADR[31..4] = SRC_DDR_ADR[31..4]; BLITTER_REQ = VCC; BL_READ_SRC = VCC; -- LATCH UND SB1->SB2 IF BLITTER_DACK0 THEN SIINC = VCC; -- INC SRC ADR BL_SM = RDSRC2; ELSE BL_SM = RDSRC1; END IF; ELSE BL_SM = RDDST; END IF; WHEN RDSRC2 => ------------------------ READ SRC2 IF SRC_READ THEN BLITTER_ADR[31..4] = SRC_DDR_ADR[31..4]; BLITTER_REQ = VCC; BL_READ_SRC = VCC; -- LATCH UND SB1->SB2 IF BLITTER_DACK0 THEN SIINC = VCC; -- INC SRC ADR BL_SM = RDDST; ELSE BL_SM = RDSRC2; END IF; ELSE BL_SM = RDDST; END IF; WHEN RDDST => ----------------------- READ DEST IF NOT_DST_READ THEN BL_SM = WRDSTW1; ELSE BLITTER_ADR[31..4] = DST_DDR_ADR[31..4]; BLITTER_REQ = VCC; BL_READ_DST = VCC; IF BLITTER_DACK0 THEN BL_SM = WRDSTW1; ELSE BL_SM = RDDST; END IF; END IF; WHEN WRDSTW1 => ------------------- WRITE DEST WAIT AUF ERGEBNIS BL_SM = WRDST; WHEN WRDST => ------------------- WRITE DEST BLITTER_ADR[31..4] = DST_DDR_ADR[31..4]; BLITTER_WR = VCC; BLITTER_REQ = VCC; IF BLITTER_DACK0 THEN XIINC = VCC; -- INC X_INDEX DIINC = VCC; -- INC DEST ADR BL_SM = TESTZEILENENDE; ELSE BL_SM = WRDST; END IF; WHEN TESTZEILENENDE => ----------------- ZEILENDE? IF X_CNT_NODE[] >= BL_X_CNT[] THEN -- SCHON ZEILENENDE? YIINC = VCC; -- JA -> INC Y-INDEX UND ZEILE SRC UND DEST BL_SM = TESTFERTIG; -- -> ELSE BL_SM = RDSRC2; -- NEIN NEXT END IF; WHEN TESTFERTIG => --------------------- TEST AUF FERTIG ZIINC = VCC; -- INC ADRESSEN ZEILENUMBRUCH IF Y_INDEX[] >= BL_Y_CNT[] THEN -- LETZTE ZEILE? BL_SM = FERTIG; -- JA --> ELSE ZYINC = VCC; -- YINC ADDIEREN ZEILENENDE BL_SM = NEW_LINE; -- NEIN NEXT -> END IF; WHEN FERTIG => -------------------------- FERTIG BLITTER_INT = VCC; -- BLITTER INTERRUPT LN7CLR = VCC; -- BUSY BIT LÖSCHEN IF BL_LN7==0 THEN -- WARTEN BIS GELÖSCHT (GEHT NUR MIT 33MHz) BL_SM = START; ELSE BL_SM = FERTIG; END IF; WHEN OTHERS => BL_SM = FERTIG; END CASE; END;