Firebee/FPGA_Config
1
0
Fork 1
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

patch with Fredi's lp fix (and others)

Browse Source
This commit is contained in:
Markus Fröschle
2015-10-26 06:48:18 +00:00
parent 1c661c8052
commit fc8034d93b
43 changed files with 5765 additions and 5956 deletions
Download Patch File Download Diff File Expand all files Collapse all files

435
FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd
View File

@@ -115,7 +115,7 @@ ENTITY falconio_sdcard_ide_cf IS
nCF_CS0 : OUT std_logic;
nIDE_RD : INOUT std_logic;
nIDE_WR : INOUT std_logic;
AMKB_TX : OUT std_logic;
AMKB_TX : buffer std_logic;
IDE_RES : OUT std_logic;
DTR : OUT std_logic;
RTS : OUT std_logic;
@@ -132,6 +132,7 @@ ENTITY falconio_sdcard_ide_cf IS
DMA_DRQ : OUT std_logic;
FB_AD : INOUT std_logic_vector(31 DOWNTO 0);
LP_D : INOUT std_logic_vector(7 DOWNTO 0);
SND_A : INOUT std_logic_vector(7 downto 0);
ACSI_D : INOUT std_logic_vector(7 DOWNTO 0);
SCSI_D : INOUT std_logic_vector(7 DOWNTO 0);
SCSI_PAR : INOUT std_logic;
@@ -141,14 +142,13 @@ ENTITY falconio_sdcard_ide_cf IS
SD_CD_DATA3 : INOUT std_logic;
SD_CDM_D1 : INOUT std_logic
);
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
END falconio_sdcard_ide_cf;
-- Architecture Body
ARCHITECTURE rtl OF falconio_sdcard_ide_cf IS
ARCHITECTURE rtl OF FalconIO_SDCard_IDE_CF IS
-- system
SIGNAL SYS_CLK : std_logic;
SIGNAL RESETn : std_logic;
@@ -156,12 +156,15 @@ ARCHITECTURE rtl OF falconio_sdcard_ide_cf IS
SIGNAL FB_B1 : std_logic; -- LOWER BYT BEI 16BIT BUS
SIGNAL BYT : std_logic; -- WENN BYT -> 1
SIGNAL LONG : std_logic; -- WENN -> 1
signal FB_ADI : STD_LOGIC_VECTOR(15 downto 0); -- gespeicherte writedaten
signal nResetatio : STD_LOGIC; -- reset atari bausteine
-- KEYBOARD MIDI
SIGNAL ACIA_CS_I : std_logic;
SIGNAL IRQ_KEYBDn : std_logic;
SIGNAL IRQ_MIDIn : std_logic;
SIGNAL KEYB_RxD : std_logic;
SIGNAL AMKB_REG : std_logic_vector(4 DOWNTO 0);
signal AMKB_REG : STD_LOGIC_VECTOR(3 downto 0);
signal AMKB_TX_sync : std_logic;
SIGNAL MIDI_OUT : std_logic;
SIGNAL DATA_OUT_ACIA_I : std_logic_vector(7 DOWNTO 0);
SIGNAL DATA_OUT_ACIA_II : std_logic_vector(7 DOWNTO 0);
@@ -169,8 +172,8 @@ ARCHITECTURE rtl OF falconio_sdcard_ide_cf IS
SIGNAL MFP_CS : std_logic;
SIGNAL MFP_INTACK : std_logic;
SIGNAL LDS : std_logic;
signal acia_irq : STD_LOGIC;
SIGNAL DTACK_OUT_MFPn : std_logic;
SIGNAL IRQ_ACIAn : std_logic;
SIGNAL DINTn : std_logic;
SIGNAL DATA_OUT_MFP : std_logic_vector(7 DOWNTO 0);
SIGNAL TDO : std_logic;
@@ -180,7 +183,22 @@ ARCHITECTURE rtl OF falconio_sdcard_ide_cf IS
SIGNAL SNDIR_I : std_logic;
SIGNAL LP_DIR_X : std_logic;
SIGNAL DA_OUT_X : std_logic_vector(7 DOWNTO 0);
signal SND_A_X : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL LP_D_X : std_logic_vector(7 DOWNTO 0);
signal nLP_STR : STD_LOGIC;
-- DMA SOUND
signal dma_snd_cs : STD_LOGIC;
signal sndmactl : STD_LOGIC_VECTOR(7 downto 0);
signal sndbashi : STD_LOGIC_VECTOR(7 downto 0);
signal sndbasmi : STD_LOGIC_VECTOR(7 downto 0);
signal sndbaslo : STD_LOGIC_VECTOR(7 downto 0);
signal sndadrhi : STD_LOGIC_VECTOR(7 downto 0);
signal sndadrmi : STD_LOGIC_VECTOR(7 downto 0);
signal sndadrlo : STD_LOGIC_VECTOR(7 downto 0);
signal sndendhi : STD_LOGIC_VECTOR(7 downto 0);
signal sndendmi : STD_LOGIC_VECTOR(7 downto 0);
signal sndendlo : STD_LOGIC_VECTOR(7 downto 0);
signal sndmode : STD_LOGIC_VECTOR(7 downto 0);
-- DIV
SIGNAL SUB_BUS : std_logic; -- SUB BUS MIT ROM-PORT, CF UND IDE
SIGNAL ROM_CS : std_logic;
@@ -228,9 +246,7 @@ ARCHITECTURE rtl OF falconio_sdcard_ide_cf IS
SIGNAL WRF_RDE : std_logic;
SIGNAL WRF_WRE : std_logic;
SIGNAL nFDC_WR : std_logic;
TYPE FCF_STATES IS (FCF_IDLE, FCF_T0, FCF_T1, FCF_T2, FCF_T3, FCF_T6, FCF_T7);
SIGNAL FCF_STATE : FCF_STATES;
SIGNAL NEXT_FCF_STATE : FCF_STATES;
SIGNAL DMA_REQ : std_logic;
@@ -241,7 +257,6 @@ ARCHITECTURE rtl OF falconio_sdcard_ide_cf IS
SIGNAL DMA_ACTIV : std_logic;
SIGNAL DMA_ACTIV_NEW : std_logic;
SIGNAL FDC_OUT : std_logic_vector(7 DOWNTO 0);
-- SCSI
SIGNAL SCSI_CS : std_logic;
SIGNAL SCSI_CSn : std_logic;
@@ -259,7 +274,6 @@ ARCHITECTURE rtl OF falconio_sdcard_ide_cf IS
SIGNAL BSY_EN : std_logic;
SIGNAL SEL_OUTn : std_logic;
SIGNAL SEL_EN : std_logic;
-- IDE
SIGNAL nnIDE_RES : std_logic;
SIGNAL IDE_CF_CS : std_logic;
@@ -269,7 +283,8 @@ ARCHITECTURE rtl OF falconio_sdcard_ide_cf IS
type CMD_STATES is( IDLE, T1, T6, T7);
SIGNAL CMD_STATE : CMD_STATES;
SIGNAL NEXT_CMD_STATE : CMD_STATES;
-- Paddle
SIGNAL paddle_cs : std_logic;
BEGIN
LONG <= '1' WHEN FB_SIZE1 = '0' AND FB_SIZE0 = '0' ELSE '0';
@@ -277,23 +292,34 @@ BEGIN
FB_B0 <= '1' WHEN FB_ADR(0) = '0' OR BYT = '0' ELSE '0';
FB_B1 <= '1' WHEN FB_ADR(0) = '1' OR BYT = '0' ELSE '0';
FALCON_IO_TA <= '1' WHEN SNDCS = '1' OR DTACK_OUT_MFPn = '0' OR ACIA_CS_I = '1' OR DMA_MODUS_CS ='1'
OR DMA_ADR_CS = '1' OR DMA_DIRM_CS = '1' OR DMA_BYT_CNT_CS = '1' OR FCF_CS = '1' OR IDE_CF_TA = '1' ELSE '0';
FALCON_IO_TA <= '1' when ACIA_CS_I = '1' or DTACK_OUT_MFPn = '0' or DMA_MODUS_CS ='1' or dma_snd_cs = '1' or paddle_cs = '1'
or DMA_ADR_CS = '1' or DMA_DIRM_CS = '1' or DMA_BYT_CNT_CS = '1' or FCF_CS = '1' or IDE_CF_TA = '1' else '0';--SNDCS = '1' or
SUB_BUS <= '1' WHEN nFB_WR = '1' AND ROM_CS = '1' ELSE
'1' WHEN nFB_WR = '1' AND IDE_CF_CS = '1' ELSE
'1' WHEN nFB_WR = '0' AND nIDE_WR = '0' ELSE '0';
nRP_UDS <= '0' WHEN SUB_BUS = '1' AND FB_B0 = '1' ELSE '1';
nRP_LDS <= '0' WHEN SUB_BUS = '1' AND FB_B1 = '1' ELSE '1';
nRP_UDS <= '0' when nFB_CS1 = '0' and SUB_BUS = '1' and FB_B0 = '1' else '1';
nRP_LDS <= '0' when nFB_CS1 = '0' and SUB_BUS = '1' and FB_B1 = '1' else '1';
nDREQ0 <= '0';
-- input daten halten
p_hold_input_data : PROCESS(MAIN_CLK, nFB_WR, FB_AD(31 DOWNTO 16), FB_ADI(15 DOWNTO 0))
BEGIN
IF rising_edge(MAIN_CLK) THEN
IF nFB_WR = '0' THEN
FB_ADI <= FB_AD(31 downto 16);
ELSE
FB_ADI <= FB_ADI;
END IF;
ELSE
FB_ADI <= FB_ADI;
END IF;
END PROCESS;
----------------------------------------------------------------------------
-- SD
----------------------------------------------------------------------------
SD_CLK <= 'Z';
SD_CD_DATA3 <= 'Z';
SD_CDM_D1 <= 'Z';
----------------------------------------------------------------------------
-- IDE
----------------------------------------------------------------------------
@@ -353,24 +379,19 @@ BEGIN
IDE_RES <= NOT nnIDE_RES AND nRSTO;
IDE_CF_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 7) = x"0" ELSE '0'; -- FFF0'0000/80
nCF_CS0 <= '0' WHEN ACP_CONF(31) = '0' AND FB_ADR(19 DOWNTO 5) = x"0" ELSE -- FFFO'0000-FFF0'001F
'0' WHEN ACP_CONF(31) = '1' AND FB_ADR(19 DOWNTO 5) = x"2" ELSE '1'; -- FFFO'0040-FFF0'005F
nCF_CS1 <= '0' WHEN ACP_CONF(31) = '0' AND FB_ADR(19 DOWNTO 5) = x"1" ELSE -- FFF0'0020-FFF0'003F
'0' WHEN ACP_CONF(31) = '1' AND FB_ADR(19 DOWNTO 5) = x"3" ELSE '1'; -- FFFO'0060-FFF0'007F
nIDE_CS0 <= '0' WHEN ACP_CONF(30) = '0' AND FB_ADR(19 DOWNTO 5) = x"2" ELSE -- FFF0'0040-FFF0'005F
'0' WHEN ACP_CONF(30) = '1' AND FB_ADR(19 DOWNTO 5) = x"0" ELSE '1'; -- FFFO'0000-FFF0'001F
nIDE_CS1 <= '0' WHEN ACP_CONF(30) = '0' AND FB_ADR(19 DOWNTO 5) = x"3" ELSE -- FFF0'0060-FFF0'007F
'0' WHEN ACP_CONF(30) = '1' AND FB_ADR(19 DOWNTO 5) = x"1" ELSE '1'; -- FFFO'0020-FFF0'003F
-----------------------------------------------------------------------------------------------------------------------------------------
-- ACSI, SCSI UND FLOPPY WD1772
-------------------------------------------------------------------------------------------------------------------------------------------
-- daten read fifo
i_data_read_fifo: dcfifo0
RDF: dcfifo0
PORT MAP(
aclr => CLR_FIFO,
data => RDF_DIN,
@@ -381,16 +402,15 @@ BEGIN
q => RDF_DOUT,
wrusedw => RDF_AZ
);
FCF_CS <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"0020110" AND LONG = '1' ELSE '0'; -- F002'0110 LONG ONLY
FCF_APH <= '1' WHEN FB_ALE = '1' AND FB_AD(31 DOWNTO 0) = x"F0020110" AND LONG = '1' ELSE '0'; -- ADRESSPHASE F0020110 LONG ONLY
RDF_RDE <= '1' WHEN FCF_APH = '1' AND nFB_WR = '1' ELSE '0'; -- AKTIVIEREN IN ADRESSPHASE
FB_AD <= RDF_DOUT(7 DOWNTO 0) & RDF_DOUT(15 DOWNTO 8) & RDF_DOUT(23 DOWNTO 16) & RDF_DOUT(31 DOWNTO 24) WHEN FCF_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z');
FB_AD <= RDF_DOUT(7 DOWNTO 0) & RDF_DOUT(15 DOWNTO 8) & RDF_DOUT(23 DOWNTO 16) & RDF_DOUT(31 DOWNTO 24) WHEN FCF_CS = '1' and nFB_OE = '0'
ELSE (OTHERS => 'Z');
RDF_DIN <= CD_OUT_FDC WHEN DMA_MODUS(7) = '1' ELSE SCSI_DOUT;
-- daten write fifo
i_data_write_fifo: dcfifo1
WRF: dcfifo1
PORT MAP(
aclr => CLR_FIFO,
data => FB_AD(7 DOWNTO 0) & FB_AD(15 DOWNTO 8) & FB_AD(23 DOWNTO 16) & FB_AD(31 DOWNTO 24),
@@ -401,14 +421,14 @@ BEGIN
q => WRF_DOUT,
rdusedw => WRF_AZ
);
CD_IN_FDC <= WRF_DOUT WHEN DMA_ACTIV = '1' AND DMA_MODUS(8) = '1' ELSE FB_AD(23 DOWNTO 16); -- BEI DMA WRITE <-FIFO SONST <-FB
CD_IN_FDC <= WRF_DOUT WHEN DMA_ACTIV = '1' and DMA_MODUS(8) = '1' ELSE FB_ADI(7 DOWNTO 0); -- BEI DMA WRITE <-FIFO SONST <-FB
DMA_AZ_CS <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"002010C" ELSE '0'; -- F002'010C LONG
FB_AD <= DMA_DRQ_Q & DMA_DRQ_REG & IDE_INT & FDINT & SCSI_INT & RDF_AZ & "0" & DMA_STATUS & "00" & WRF_AZ WHEN DMA_AZ_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z');
FB_AD <= DMA_DRQ_Q & DMA_DRQ_REG & IDE_INT & FDINT & SCSI_INT & RDF_AZ & "0" & DMA_STATUS & "00" & WRF_AZ WHEN DMA_AZ_CS = '1' and nFB_OE = '0'
ELSE (OTHERS => 'Z');
DMA_DRQ_Q <= '1' WHEN DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' ELSE '0';
-- FIFO WRITE: GENAU 1 MAIN_CLK -------------------------------------------------------------------------
PROCESS(MAIN_CLK, nRSTO, WRF_WRE, nFB_WR, FCF_APH)
p_fifo_write : PROCESS(MAIN_CLK, nRSTO, WRF_WRE, nFB_WR, FCF_APH)
BEGIN
IF nRSTO = '0' THEN
WRF_WRE <= '0';
@@ -530,7 +550,7 @@ BEGIN
i_fdc : WF1772IP_TOP_SOC
PORT MAP(
CLK => FDC_CLK,
RESETn => nRSTO,
RESETn => nResetatio,
CSn => FDCS_In,
RWn => nFDC_WR,
A1 => CA2,
@@ -552,25 +572,20 @@ BEGIN
DRQ => DMA_DRQ_I,
INTRQ => FDINT
);
DMA_DATEN_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C302" ELSE '0'; -- F8604/2
DMA_MODUS_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C303" ELSE '0'; -- F8606/2
WDC_BSL_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C307" ELSE '0'; -- F860E/2
HD_DD_OUT <= HD_DD WHEN ACP_CONF(29) = '0' ELSE WDC_BSL(0);
nFDC_WR <= NOT DMA_MODUS(8) WHEN DMA_ACTIV = '1' ELSE nFB_WR;
nFDC_WR <= (not DMA_MODUS(8)) WHEN DMA_ACTIV = '1' ELSE nFB_WR;
CA0 <= '1' WHEN DMA_ACTIV = '1' ELSE DMA_MODUS(0);
CA1 <= '1' WHEN DMA_ACTIV = '1' ELSE DMA_MODUS(1);
CA2 <= '1' WHEN DMA_ACTIV = '1' ELSE DMA_MODUS(2);
FB_AD(23 DOWNTO 16) <= "0000" & (NOT DMA_STATUS(1)) & "0" & WDC_BSL(1) & HD_DD WHEN WDC_BSL_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z');
FB_AD(31 DOWNTO 24) <= "00000000" WHEN DMA_DATEN_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z');
FB_AD(23 downto 16) <= "0000" & (not DMA_STATUS(1)) & "0" & WDC_BSL(1) & HD_DD when WDC_BSL_CS = '1' and nFB_OE = '0' else (OTHERS => 'Z');
FB_AD(31 downto 24) <= "00000000" when DMA_DATEN_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ";
FB_AD(23 DOWNTO 16) <= FDC_OUT WHEN DMA_DATEN_CS = '1' AND DMA_MODUS(4 DOWNTO 3) = "00" AND nFB_OE = '0' ELSE
SCSI_DOUT WHEN DMA_DATEN_CS = '1' AND DMA_MODUS(4 DOWNTO 3) = "01" AND nFB_OE = '0' ELSE
DMA_BYT_CNT(16 DOWNTO 9) WHEN DMA_DATEN_CS = '1' AND DMA_MODUS(4) = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z');
DMA_BYT_CNT(16 downto 9) when DMA_DATEN_CS = '1' and DMA_MODUS(4) = '1' and nFB_OE = '0' else "ZZZZZZZZ";
--- WDC BSL REGISTER -------------------------------------------------------
PROCESS(MAIN_CLK, nRSTO, WDC_BSL_CS, WDC_BSL, nFB_WR, FB_B0, FB_B1)
BEGIN
@@ -584,7 +599,6 @@ BEGIN
END IF;
END IF;
END PROCESS;
--- DMA MODUS REGISTER -------------------------------------------------------
PROCESS(MAIN_CLK, nRSTO, DMA_MODUS_CS, DMA_MODUS, nFB_WR, FB_B0, FB_B1)
BEGIN
@@ -605,16 +619,15 @@ BEGIN
DMA_MODUS <= DMA_MODUS;
END IF;
END PROCESS;
-- BYT COUNTER, SECTOR COUNTER ----------------------------------------------------
PROCESS(MAIN_CLK, nRSTO, DMA_DATEN_CS, DMA_BYT_CNT_CS, DMA_BYT_CNT, nFB_WR, FB_B0, FB_B1, DMA_MODUS, CLR_FIFO)
BEGIN
IF nRSTO = '0' OR CLR_FIFO = '1' THEN
DMA_BYT_CNT <= x"00000000";
ELSIF rising_edge(MAIN_CLK) AND nFB_WR = '0' AND DMA_DATEN_CS = '1' AND nFB_WR = '0' AND DMA_MODUS(4) = '1' AND FB_B1 = '1' THEN
DMA_BYT_CNT(31 DOWNTO 17) <= (OTHERS => 'Z');
DMA_BYT_CNT(31 downto 17) <= "000000000000000";
DMA_BYT_CNT(16 DOWNTO 9) <= FB_AD(23 DOWNTO 16);
DMA_BYT_CNT(8 DOWNTO 0) <= (OTHERS => 'Z');
DMA_BYT_CNT(8 downto 0) <= "000000000";
ELSIF rising_edge(MAIN_CLK) AND nFB_WR = '0' AND DMA_BYT_CNT_CS = '1' THEN
DMA_BYT_CNT <= FB_AD;
ELSE
@@ -622,15 +635,13 @@ BEGIN
END IF;
END PROCESS;
--------------------------------------------------------------------
FB_AD(31 DOWNTO 16) <= "0000000000000" & DMA_STATUS WHEN DMA_MODUS_CS = '1' and nFB_OE = '0' ELSE (OTHERS => 'Z');
FB_AD(31 downto 16) <= "0000000000000" & DMA_STATUS when DMA_MODUS_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
DMA_STATUS(0) <= '1'; -- DMA OK
DMA_STATUS(1) <= '1' WHEN DMA_BYT_CNT /= 0 AND DMA_BYT_CNT(31) = '0' ELSE '0'; -- WENN byts UND NICHT MINUS
DMA_STATUS(2) <= '0' WHEN DMA_DRQ_I = '1' OR SCSI_DRQ = '1' ELSE '0';
DMA_DRQQ <= '1' WHEN DMA_STATUS(1) = '1' AND DMA_MODUS(8) = '0' AND RDF_AZ > 15 AND DMA_MODUS(6) = '0' ELSE
'1' WHEN DMA_STATUS(1) = '1' AND DMA_MODUS(8) = '1' AND WRF_AZ < 512 AND DMA_MODUS(6) = '0' ELSE '0';
DMA_DRQ <= '1' WHEN DMA_DRQ_REG = "11" AND DMA_MODUS(6) = '0' ELSE '0';
-- DMA REQUEST: SPIKES AUSFILTERN ------------------------------------------
PROCESS(FDC_CLK, nRSTO, DMA_DRQ_REG)
BEGIN
@@ -643,7 +654,6 @@ BEGIN
DMA_DRQ_REG <= DMA_DRQ_REG;
END IF;
END PROCESS;
-- DMA ADRESSE ------------------------------------------------------
PROCESS(MAIN_CLK, nRSTO, DMA_TOP_CS, DMA_TOP, nFB_WR, DMA_ADR_CS)
BEGIN
@@ -655,7 +665,6 @@ BEGIN
DMA_TOP <= DMA_TOP;
END IF;
END PROCESS;
PROCESS(MAIN_CLK, nRSTO, DMA_HIGH_CS, DMA_HIGH, nFB_WR, DMA_ADR_CS)
BEGIN
IF nRSTO = '0' THEN
@@ -666,7 +675,6 @@ BEGIN
DMA_HIGH <= DMA_HIGH;
END IF;
END PROCESS;
PROCESS(MAIN_CLK, nRSTO, DMA_MID_CS, DMA_MID, nFB_WR)
BEGIN
DMA_MID <= DMA_MID;
@@ -680,7 +688,6 @@ BEGIN
END IF;
END IF;
END PROCESS;
PROCESS(MAIN_CLK, nRSTO, DMA_LOW_CS, DMA_LOW, nFB_WR)
BEGIN
DMA_LOW <= DMA_LOW;
@@ -694,29 +701,26 @@ BEGIN
END IF;
END IF;
END PROCESS;
--------------------------------------------------------------------------------------------
DMA_TOP_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C304" AND FB_B0 = '1' ELSE '0'; -- F8608/2
DMA_HIGH_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C304" AND FB_B1 = '1' ELSE '0'; -- F8609/2
DMA_MID_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C305" AND FB_B1 = '1' ELSE '0'; -- F860B/2
DMA_LOW_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C306" AND FB_B1 = '1' ELSE '0'; -- F860D/2
FB_AD(31 DOWNTO 24) <= DMA_TOP WHEN DMA_TOP_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z');
FB_AD(23 DOWNTO 16) <= DMA_HIGH WHEN DMA_HIGH_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z');
FB_AD(23 DOWNTO 16) <= DMA_MID WHEN DMA_MID_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z');
FB_AD(23 DOWNTO 16) <= DMA_LOW WHEN DMA_LOW_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z');
FB_AD(31 DOWNTO 24) <= DMA_TOP WHEN DMA_TOP_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ";
FB_AD(23 DOWNTO 16) <= DMA_HIGH WHEN DMA_HIGH_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ";
FB_AD(23 DOWNTO 16) <= DMA_MID WHEN DMA_MID_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ";
FB_AD(23 DOWNTO 16) <= DMA_LOW WHEN DMA_LOW_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ";
-- DIRECTZUGRIFF
DMA_DIRM_CS <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"20100" ELSE '0'; -- F002'0100 WORD
DMA_ADR_CS <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"20104" ELSE '0'; -- F002'0104 LONG
DMA_BYT_CNT_CS <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"20108" ELSE '0'; -- F002'0108 LONG
FB_AD <= DMA_TOP & DMA_HIGH & DMA_MID & DMA_LOW WHEN DMA_ADR_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z');
FB_AD(31 DOWNTO 16) <= DMA_MODUS WHEN DMA_DIRM_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z');
FB_AD <= DMA_BYT_CNT WHEN DMA_BYT_CNT_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z');
FB_AD <= DMA_TOP & DMA_HIGH & DMA_MID & DMA_LOW when DMA_ADR_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
FB_AD(31 DOWNTO 16) <= DMA_MODUS WHEN DMA_DIRM_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ";
FB_AD <= DMA_BYT_CNT WHEN DMA_BYT_CNT_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
-- DMA RW TOGGLE ------------------------------------------
PROCESS(MAIN_CLK, nRSTO, DMA_MODUS_CS, DMA_MODUS, DMA_DIR_OLD)
BEGIN
IF nRSTO = '0' THEN
@@ -727,20 +731,18 @@ BEGIN
DMA_DIR_OLD <= DMA_DIR_OLD;
END IF;
END PROCESS;
CLR_FIFO <= DMA_MODUS(8) XOR DMA_DIR_OLD;
-- SCSI ----------------------------------------------------------------------------------
i_scsi : WF5380_TOP_SOC
PORT MAP(
CLK => FDC_CLK,
RESETn => nRSTO,
RESETn => nResetatio,
ADR => CA2 & CA1 & CA0,
DATA_IN => CD_IN_FDC,
DATA_OUT => SCSI_DOUT,
--DATA_EN : out bit;
-- Bus and DMA controls:
CSn => '1', --SCSI_CSn, ABGESCHALTET
CSn => SCSI_CSn,
RDn => (not nFDC_WR) or (not SCSI_CS),
WRn => nFDC_WR or (not SCSI_CS),
EOPn => '1',
@@ -783,37 +785,36 @@ BEGIN
-- MSG_OUTn => MSG_OUTn,
-- MSG_EN => MSG_EN
);
-- SCSI ACSI ---------------------------------------------------------------
SCSI_D <= DB_OUTn WHEN DB_EN = '1' ELSE (OTHERS => 'Z');
SCSI_DIR <= '1'; --'0' WHEN DB_EN = '1' ELSE '1'; --ABGESCHALTET
SCSI_D <= "ZZZZZZZZ"; --DB_OUTn when DB_EN = '1' else "ZZZZZZZZ";
SCSI_DIR <= '1';-- when DB_EN = '1' else '1';
SCSI_PAR <= DBP_OUTn WHEN DBP_EN = '1' ELSE 'Z';
nSCSI_RST <= RST_OUTn WHEN RST_EN = '1' ELSE 'Z';
nSCSI_BUSY <= BSY_OUTn WHEN BSY_EN = '1' ELSE 'Z';
nSCSI_SEL <= SEL_OUTn WHEN SEL_EN = '1' ELSE 'Z';
nSCSI_RST <= 'Z';--RST_OUTn when RST_EN = '1' else 'Z';
nSCSI_BUSY <= 'Z';--BSY_OUTn when BSY_EN = '1' else 'Z';
nSCSI_SEL <= 'Z';--SEL_OUTn when SEL_EN = '1' else 'Z';
ACSI_DIR <= '0';
ACSI_D <= (OTHERS => 'Z');
ACSI_D <= "ZZZZZZZZ";
nACSI_CS <= '1';
ACSI_A1 <= CA1;
nACSI_RESET <= nRSTO;
nACSI_ACK <= '1';
nResetatio <= '0' when nRSTO = '0' or ACP_CONF(24) = '1' else '1';
----------------------------------------------------------------------------
-- ROM-PORT TA KOMMT FROM DEFAULT TA = 16 BUSCYCLEN = 500ns
----------------------------------------------------------------------------
ROM_CS <= '1' WHEN nFB_CS1 = '0' AND nFB_WR = '1' AND FB_ADR(19 DOWNTO 17) = x"5" ELSE '0'; -- FFF A'0000/2'0000
nROM4 <= '0' WHEN ROM_CS = '1' AND FB_ADR(16) = '0' ELSE '1';
nROM3 <= '0' WHEN ROM_CS = '1' AND FB_ADR(16) = '1' ELSE '1';
----------------------------------------------------------------------------
-- ACIA KEYBOARD
----------------------------------------------------------------------------
i_acia_keyboard : WF6850IP_TOP_SOC
PORT MAP(
CLK => MAIN_CLK,
RESETn => nRSTO,
RESETn => nResetatio,
CS2n => FB_ADR(2),
CS1 => '1',
@@ -822,7 +823,7 @@ BEGIN
RWn => nFB_WR,
RS => FB_ADR(1),
DATA_IN => FB_AD(31 DOWNTO 24),
DATA_IN => FB_ADI(15 downto 8),
DATA_OUT => DATA_OUT_ACIA_I,
-- DATA_EN => DATA_EN_ACIA_I,
@@ -834,43 +835,48 @@ BEGIN
DCDn => '0',
IRQn => IRQ_KEYBDn,
TXDATA => AMKB_TX
TXDATA => AMKB_TX_sync
--RTSn => -- Not used.
);
ACIA_CS_I <= '1' WHEN nFB_CS1 = '0'AND FB_ADR(19 DOWNTO 3) = x"1FF80" ELSE '0'; -- FFC00-FFC07 FFC00/8
KEYB_RxD <= '1' WHEN AMKB_REG(3) = '1' OR PIC_AMKB_RX = '0' ELSE '0'; -- TASTATUR DATEN VOM PIC(PS2) OR NORMAL
FB_AD(31 DOWNTO 24) <= DATA_OUT_ACIA_I WHEN ACIA_CS_I = '1' AND FB_ADR(2) = '0' AND nFB_OE = '0' ELSE "ZZZZZZZZ";
-- AMKB_TX: SPIKES AUSFILTERN ------------------------------------------
KEYB_RxD <= '0' WHEN AMKB_REG(3) = '0' or PIC_AMKB_RX = '0' ELSE '1'; -- TASTATUR DATEN VOM PIC(PS2) OR NORMAL //
FB_AD(31 DOWNTO 24) <= DATA_OUT_ACIA_I WHEN ACIA_CS_I = '1' and FB_ADR(2) = '0' and nFB_OE = '0' ELSE
DATA_OUT_ACIA_II WHEN ACIA_CS_I = '1' and FB_ADR(2) = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ";
-- AMKB_TX: SPIKES AUSFILTERN und sychronisieren ------------------------------------------
PROCESS(CLK2M, AMKB_RX, AMKB_REG)
BEGIN
IF rising_edge(CLK2M) THEN
if rising_edge(CLK500k) then
AMKB_TX <= AMKB_TX_sync;
IF AMKB_RX = '0' THEN
IF AMKB_REG < 16 THEN
AMKB_REG <= "00000";
IF AMKB_REG < 8 THEN
AMKB_REG <= "0000";
ELSE
AMKB_REG <= AMKB_REG - 1;
END IF;
ELSE
IF AMKB_REG > 15 THEN
AMKB_REG <= "11111";
IF AMKB_REG > 7 THEN
AMKB_REG <= "1111";
ELSE
AMKB_REG <= AMKB_REG + 1;
END IF;
END IF;
ELSE
AMKB_TX <= AMKB_TX;
AMKB_REG <= AMKB_REG;
END IF;
END PROCESS;
-- acia interrupt ------------------------------------------
acia_irq <= '0' WHEN IRQ_KEYBDn = '0' or IRQ_MIDIn = '0' ELSE '1';
----------------------------------------------------------------------------
-- ACIA MIDI
----------------------------------------------------------------------------
i_acia_midi : WF6850IP_TOP_SOC
PORT MAP(
CLK => MAIN_CLK,
RESETn => nRSTO,
RESETn => nResetatio,
CS2n => '0',
CS1 => FB_ADR(2),
@@ -879,7 +885,7 @@ BEGIN
RWn => nFB_WR,
RS => FB_ADR(1),
DATA_IN => FB_AD(31 DOWNTO 24),
DATA_IN => FB_ADI(15 downto 8),
DATA_OUT => DATA_OUT_ACIA_II,
-- DATA_EN => DATA_EN_ACIA_II,
@@ -893,19 +899,16 @@ BEGIN
TXDATA => MIDI_OUT
--RTSn => -- Not used.
);
MIDI_TLR <= MIDI_OUT;
MIDI_TLR <= MIDI_IN;
MIDI_OLR <= MIDI_OUT;
FB_AD(31 DOWNTO 24) <= DATA_OUT_ACIA_II WHEN ACIA_CS_I = '1' AND FB_ADR(2) = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z');
----------------------------------------------------------------------------
-- MFP
----------------------------------------------------------------------------
i_mfp : WF68901IP_TOP_SOC
PORT MAP(
-- System control:
CLK => MAIN_CLK,
RESETn => nRSTO,
CLK => not MAIN_CLK,
RESETn => nResetatio,
-- Asynchronous bus control:
DSn => NOT LDS,
CSn => NOT MFP_CS,
@@ -919,7 +922,7 @@ BEGIN
GPIP_IN(7) => NOT DMA_DRQ_Q,
GPIP_IN(6) => NOT RI,
GPIP_IN(5) => DINTn,
GPIP_IN(4) => IRQ_ACIAn,
GPIP_IN(4) => acia_irq,
GPIP_IN(3) => DSP_INT,
GPIP_IN(2) => NOT CTS,
GPIP_IN(1) => NOT DCD,
@@ -953,35 +956,21 @@ BEGIN
MFP_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 6) = x"3FE8" ELSE '0'; -- FFA00/40
MFP_INTACK <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"20000" ELSE '0'; --F002'0000
LDS <= '1' WHEN MFP_CS = '1' OR MFP_INTACK = '1' ELSE '0';
FB_AD(23 DOWNTO 16) <= DATA_OUT_MFP WHEN MFP_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z');
FB_AD(31 DOWNTO 10) <= (OTHERS => '0') WHEN MFP_INTACK = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z');
FB_AD(9 DOWNTO 2) <= DATA_OUT_MFP WHEN MFP_INTACK = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z') ;
FB_AD(23 DOWNTO 16) <= DATA_OUT_MFP WHEN MFP_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ";
FB_AD(31 DOWNTO 10) <= "0000000000000000000000" WHEN MFP_INTACK = '1' and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZZZZZZZ";
FB_AD(9 DOWNTO 2) <= DATA_OUT_MFP when MFP_INTACK = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ";
FB_AD(1 DOWNTO 0) <= "00" WHEN MFP_INTACK = '1' AND nFB_OE = '0' ELSE "ZZ";
DINTn <= '0' WHEN IDE_INT = '1' AND ACP_CONF(28) = '1' ELSE
'0' WHEN FDINT = '1' ELSE
'0' WHEN SCSI_INT = '1' AND ACP_CONF(28) = '1' ELSE '1';
-- TASTATUR UND KEYBOARD INTERRUPT: SPIKES AUSFILTERN ------------------------------------------
PROCESS(MAIN_CLK, nRSTO, IRQ_ACIAn, IRQ_KEYBDn, IRQ_MIDIn)
BEGIN
IF nRSTO = '0' THEN
IRQ_ACIAn <= '1';
ELSIF rising_edge(MAIN_CLK) THEN
IRQ_ACIAn <= IRQ_KEYBDn AND IRQ_MIDIn;
ELSE
IRQ_ACIAn <= IRQ_ACIAn;
END IF;
END PROCESS;
----------------------------------------------------------------------------
-- Sound
----------------------------------------------------------------------------
i_sound : WF2149IP_TOP_SOC
PORT MAP(
SYS_CLK => MAIN_CLK,
RESETn => nRSTO,
SYS_CLK => not MAIN_CLK,
RESETn => nResetatio,
WAV_CLK => CLK2M,
SELn => '1',
@@ -992,18 +981,11 @@ BEGIN
A9n => '0',
A8 => '1',
DA_IN => FB_AD(31 DOWNTO 24),
DA_IN => FB_ADI(15 downto 8),
DA_OUT => DA_OUT_X,
IO_A_IN => x"00", -- All port pins are dedicated outputs.
IO_A_OUT(7) => nnIDE_RES,
IO_A_OUT(6) => LP_DIR_X,
IO_A_OUT(5) => LP_STR,
IO_A_OUT(4) => DTR,
IO_A_OUT(3) => RTS,
-- IO_A_OUT(2) => FDD_D1SEL,
IO_A_OUT(1) => DSA_D,
IO_A_OUT(0) => nSDSEL,
IO_A_IN => SND_A,
IO_A_OUT => SND_A_X,
-- IO_A_EN =>, -- Not required.
IO_B_IN => LP_D,
IO_B_OUT => LP_D_X,
@@ -1017,8 +999,185 @@ BEGIN
SNDCS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 2) = x"3E200" ELSE '0'; -- 8800-8803 F8800/4
SNDCS_I <= '1' WHEN SNDCS = '1' AND FB_ADR (1 DOWNTO 1) = "0" ELSE '0';
SNDIR_I <= '1' WHEN SNDCS = '1' AND nFB_WR = '0' ELSE '0';
FB_AD(31 DOWNTO 24) <= DA_OUT_X WHEN SNDCS_I = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z');
LP_D <= LP_D_X WHEN LP_DIR_X = '0' ELSE (OTHERS => 'Z');
FB_AD(31 DOWNTO 24) <= DA_OUT_X WHEN SNDCS_I = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ";
nnIDE_RES <= SND_A_X(7);
LP_DIR_X <= SND_A_X(6);
LP_STR <= SND_A_X(5);
DTR <= SND_A_X(4);
RTS <= SND_A_X(3);
-- FDD_D1SEL <= SND_A_X(2)
DSA_D <= SND_A_X(1);
nSDSEL <= SND_A_X(0);
SND_A <= SND_A_X;
LP_D <= LP_D_X WHEN LP_DIR_X = '0' ELSE "ZZZZZZZZ";
LP_DIR <= LP_DIR_X;
----------------------------------------------------------------------------
-- DMA Sound register
----------------------------------------------------------------------------
dma_snd_cs <= '1' WHEN nFB_CS1 = '0' and FB_ADR(19 DOWNTO 6) = x"3E24" ELSE '0'; -- F8900-F893F
PROCESS(nRSTO,MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs)
BEGIN
IF nRSTO = '0' THEN
sndmactl <= x"00";
ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"0" and nFB_WR = '0' and FB_B1 ='1' THEN
sndmactl <= FB_AD(23 DOWNTO 16);
ELSE
sndmactl <= sndmactl;
END IF;
END PROCESS;
FB_AD(23 DOWNTO 16) <= sndmactl WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"0" and nFB_OE = '0' ELSE "ZZZZZZZZ";
PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs)
begin
IF nRSTO = '0' THEN
sndbashi <= x"00";
ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"1" and nFB_WR = '0' and FB_B1 ='1' THEN
sndbashi <= FB_AD(23 DOWNTO 16);
ELSE
sndbashi <= sndbashi;
END IF;
END PROCESS;
FB_AD(23 DOWNTO 16) <= sndbashi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"1" and nFB_OE = '0' ELSE "ZZZZZZZZ";
PROCESS(nRSTO,MAIN_CLK,FB_ADR(5 DOWNTO 1), dma_snd_cs)
BEGIN
IF nRSTO = '0' THEN
sndbasmi <= x"00";
ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"2" and nFB_WR = '0' and FB_B1 ='1' THEN
sndbasmi <= FB_AD(23 DOWNTO 16);
ELSE
sndbasmi <= sndbasmi;
END IF;
END PROCESS;
FB_AD(23 DOWNTO 16) <= sndbasmi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"2" and nFB_OE = '0' ELSE "ZZZZZZZZ";
PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs)
BEGIN
IF nRSTO = '0' THEN
sndbaslo <= x"00";
ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"3" and nFB_WR = '0' and FB_B1 ='1' THEN
sndbaslo <= FB_AD(23 DOWNTO 16);
ELSE
sndbaslo <= sndbaslo;
END IF;
END PROCESS;
FB_AD(23 DOWNTO 16) <= sndbaslo WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"3" and nFB_OE = '0' ELSE "ZZZZZZZZ";
PROCESS(nRSTO,MAIN_CLK,FB_ADR(5 DOWNTO 1), dma_snd_cs)
BEGIN
IF nRSTO = '0' THEN
sndadrhi <= x"00";
ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"4" and nFB_WR = '0' and FB_B1 ='1' THEN
sndadrhi <= FB_AD(23 DOWNTO 16);
ELSE
sndadrhi <= sndadrhi;
END IF;
END PROCESS;
FB_AD(23 DOWNTO 16) <= sndadrhi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"4" and nFB_OE = '0' ELSE "ZZZZZZZZ";
PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs)
BEGIN
IF nRSTO = '0' THEN
sndadrmi <= x"00";
ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"5" and nFB_WR = '0' and FB_B1 ='1' THEN
sndadrmi <= FB_AD(23 DOWNTO 16);
ELSE
sndadrmi <= sndadrmi;
END IF;
END PROCESS;
FB_AD(23 DOWNTO 16) <= sndadrmi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"5" and nFB_OE = '0' else "ZZZZZZZZ";
PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs)
BEGIN
IF nRSTO = '0' THEN
sndadrlo <= x"00";
ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"6" and nFB_WR = '0' and FB_B1 ='1' THEN
sndadrlo <= FB_AD(23 DOWNTO 16);
ELSE
sndadrlo <= sndadrlo;
END IF;
END PROCESS;
FB_AD(23 DOWNTO 16) <= sndadrlo WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"6" and nFB_OE = '0' ELSE "ZZZZZZZZ";
PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs)
BEGIN
IF nRSTO = '0' THEN
sndendhi <= x"00";
ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"7" and nFB_WR = '0' and FB_B1 ='1' THEN
sndendhi <= FB_AD(23 DOWNTO 16);
ELSE
sndendhi <= sndendhi;
END IF;
END PROCESS;
FB_AD(23 DOWNTO 16) <= sndendhi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"7" and nFB_OE = '0' ELSE "ZZZZZZZZ";
PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs)
BEGIN
IF nRSTO = '0' THEN
sndendmi <= x"00";
ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"8" and nFB_WR = '0' and FB_B1 ='1' THEN
sndendmi <= FB_AD(23 DOWNTO 16);
ELSE
sndendmi <= sndendmi;
END IF;
END PROCESS;
FB_AD(23 DOWNTO 16) <= sndendmi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"8" and nFB_OE = '0' ELSE "ZZZZZZZZ";
PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs)
BEGIN
IF nRSTO = '0' THEN
sndendlo <= x"00";
ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"9" and nFB_WR = '0' and FB_B1 ='1' THEN
sndendlo <= FB_AD(23 DOWNTO 16);
ELSE
sndendlo <= sndendlo;
END IF;
END PROCESS;
FB_AD(23 DOWNTO 16) <= sndendlo WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"9" and nFB_OE = '0' ELSE "ZZZZZZZZ";
PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs)
BEGIN
IF nRSTO = '0' THEN
sndmode <= x"00";
ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"10" and nFB_WR = '0' and FB_B1 ='1' THEN
sndmode <= FB_AD(23 DOWNTO 16);
ELSE
sndmode <= sndmode;
END IF;
END PROCESS;
FB_AD(23 DOWNTO 16) <= sndmode WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"10" and nFB_OE = '0' ELSE "ZZZZZZZZ";
----------------------------------------------------------------------------
-- Paddle
----------------------------------------------------------------------------
paddle_cs <= '1' WHEN nFB_CS1 = '0' and FB_ADR(19 DOWNTO 6) = x"3E48" ELSE '0'; -- F9200-F923F
FB_AD(31 DOWNTO 16) <= x"bfff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"0" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ";
FB_AD(31 DOWNTO 16) <= x"ffff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"1" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ";
FB_AD(31 DOWNTO 16) <= x"ffff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"8" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ";
FB_AD(31 DOWNTO 16) <= x"ffff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"9" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ";
FB_AD(31 DOWNTO 16) <= x"ffff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"A" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ";
FB_AD(31 DOWNTO 16) <= x"ffff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"B" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ";
FB_AD(31 DOWNTO 16) <= x"0000" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"10" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ";
FB_AD(31 DOWNTO 16) <= x"0000" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"11" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ";
END rtl;

2
FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd
View File

@@ -64,7 +64,7 @@ type BUSCYCLES is (INACTIVE, R_READ, R_WRITE, ADDRESS);
component WF2149IP_WAVE
port(
RESETn : in bit;
SYS_CLK : in std_logic;
SYS_CLK : in bit;
WAV_STRB : in bit;

15
FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd
View File

@@ -83,7 +83,7 @@ LIBRARY ieee;
ENTITY WF2149IP_TOP_SOC IS
PORT(
SYS_CLK : IN std_logic; -- Read the inforation in the header!
SYS_CLK : in bit; -- Read the inforation in the header!
RESETn : IN bit;
WAV_CLK : IN bit; -- Read the inforation in the header!
@@ -110,7 +110,7 @@ ENTITY WF2149IP_TOP_SOC IS
);
END WF2149IP_TOP_SOC;
ARCHITECTURE rtl OF WF2149IP_TOP_SOC IS
architecture STRUCTURE of WF2149IP_TOP_SOC is
SIGNAL BUSCYCLE : BUSCYCLES;
SIGNAL DATA_OUT_I : std_logic_vector(7 DOWNTO 0);
SIGNAL DATA_EN_I : bit;
@@ -127,11 +127,10 @@ BEGIN
IF RESETn = '0' THEN
LOCK := false;
TMP := '0';
ELSIF rising_edge(SYS_CLK) THEN
elsif SYS_CLK = '1' and SYS_CLK' event then
IF WAV_CLK = '1' and LOCK = false THEN
LOCK := true;
TMP := not TMP; -- Divider by 2.
CASE SELn IS
WHEN '1' => WAV_STRB <= '1';
WHEN OTHERS => WAV_STRB <= TMP;
@@ -158,7 +157,7 @@ BEGIN
BEGIN
IF RESETn = '0' THEN
ADR_I <= (OTHERS => '0');
ELSIF rising_edge(SYS_CLK) THEN
elsif SYS_CLK = '1' and SYS_CLK' event then
IF BUSCYCLE = ADDRESS AND A9n = '0' AND A8 = '1' AND DA_IN(7 DOWNTO 4) = x"0" THEN
ADR_I <= To_BitVector(DA_IN(3 DOWNTO 0));
END IF;
@@ -170,7 +169,7 @@ BEGIN
BEGIN
IF RESETn = '0' THEN
CTRL_REG <= x"00";
ELSIF rising_edge(SYS_CLK) THEN
elsif SYS_CLK = '1' and SYS_CLK' event then
IF BUSCYCLE = R_WRITE AND ADR_I = x"7" THEN
CTRL_REG <= To_BitVector(DA_IN);
END IF;
@@ -182,7 +181,7 @@ BEGIN
IF RESETn = '0' THEN
PORT_A <= x"00";
PORT_B <= x"00";
ELSIF rising_edge(SYS_CLK) THEN
elsif SYS_CLK = '1' and SYS_CLK' event then
IF BUSCYCLE = R_WRITE AND ADR_I = x"E" THEN
PORT_A <= To_BitVector(DA_IN);
ELSIF BUSCYCLE = R_WRITE and ADR_I = x"F" THEN
@@ -227,4 +226,4 @@ BEGIN
To_StdLogicVector(IO_B_IN) WHEN BUSCYCLE = R_READ and ADR_I = x"F" ELSE
To_StdLogicVector(CTRL_REG) WHEN BUSCYCLE = R_READ and ADR_I = x"7" ELSE (OTHERS => '0');
END rtl;
end STRUCTURE;

2
FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd
View File

@@ -65,7 +65,7 @@ use work.wf2149ip_pkg.all;
entity WF2149IP_WAVE is
port(
RESETn : in bit;
SYS_CLK : in std_logic;
SYS_CLK : in bit;
WAV_STRB : in bit;

96
FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd
View File

@@ -67,7 +67,7 @@ use ieee.std_logic_unsigned.all;
entity WF6850IP_CTRL_STATUS is
port (
CLK : in bit;
CLK : in std_logic;
RESETn : in bit;
CS : in bit_vector(2 downto 0); -- Active if "011".
@@ -94,7 +94,7 @@ entity WF6850IP_CTRL_STATUS is
CDS : out bit_vector(1 downto 0); -- Clock control.
WS : out bit_vector(2 downto 0); -- Word select.
TC : out bit_vector(1 downto 0); -- Transmit control.
IRQn : out bit -- Interrupt request.
IRQn : buffer bit -- Interrupt request.
);
end entity WF6850IP_CTRL_STATUS;
@@ -102,19 +102,14 @@ architecture BEHAVIOR of WF6850IP_CTRL_STATUS is
signal CTRL_REG : bit_vector(7 downto 0);
signal STATUS_REG : bit_vector(7 downto 0);
signal RIE : bit;
signal IRQ_I : bit;
signal CTS_In : bit;
signal DCD_In : bit;
signal DCD_FLAGn : bit;
begin
P_SAMPLE: process
begin
wait until CLK = '0' and CLK' event;
CTS_In <= CTSn; -- Sample CTSn on the negative clock edge.
DCD_In <= DCDn; -- Sample DCDn on the negative clock edge.
end process P_SAMPLE;
CTS_In <= CTSn;
DCD_In <= DCDn; -- immer 0
STATUS_REG(7) <= IRQ_I;
STATUS_REG(7) <= not IRQn;
STATUS_REG(6) <= PE;
STATUS_REG(5) <= OVR;
STATUS_REG(4) <= FE;
@@ -123,8 +118,8 @@ begin
STATUS_REG(1) <= TDRE and not CTS_In; -- No TDRE for CTSn = '1'.
STATUS_REG(0) <= RDRF and not DCD_In; -- DCDn = '1' indicates empty.
DATA_OUT <= STATUS_REG when CS = "011" and RWn = '1' and RS = '0' and E = '1' else (others => '0');
DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '0' and E = '1' else '0';
DATA_OUT <= STATUS_REG when CS = "011" and RWn = '1' and RS = '0' else (others => '0');
DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '0' else '0';
MCLR <= '1' when CTRL_REG(1 downto 0) = "11" else '0';
RTSn <= '0' when CTRL_REG(6 downto 5) /= "10" else '1';
@@ -134,90 +129,52 @@ begin
TC <= CTRL_REG(6 downto 5);
RIE <= CTRL_REG(7);
P_IRQ: process
variable DCD_OVR_LOCK : boolean;
variable DCD_LOCK : boolean;
variable DCD_TRANS : boolean;
P_IRQ: process(CLK)
begin
wait until CLK = '1' and CLK' event;
if RESETn = '0' then
DCD_OVR_LOCK := false;
IRQn <= '1';
IRQ_I <= '0';
elsif CS = "011" and RWn = '1' and RS = '0' and E = '1' then
DCD_OVR_LOCK := false; -- Enable reset by reading the status.
end if;
-- Clear interrupts when disabled.
if CTRL_REG(7) = '0' then
if rising_edge(CLK) then
if RESETn = '0' or MCLR = '1' then
IRQn <= '1';
IRQ_I <= '0';
elsif CTRL_REG(6 downto 5) /= "01" then
IRQn <= '1';
IRQ_I <= '0';
end if;
else
-- Transmitter interrupt:
if TDRE = '1' and CTRL_REG(6 downto 5) = "01" and CTS_In = '0' then
if TDRE = '1' and CTRL_REG(6 downto 5) = "01" then
IRQn <= '0';
IRQ_I <= '1';
elsif CS = "011" and RWn = '0' and RS = '1' and E = '1' then
IRQn <= '1'; -- Clear by writing to the transmit data register.
end if;
-- Receiver interrupts:
if RDRF = '1' and RIE = '1' and DCD_In = '0' then
if RDRF = '1' and RIE = '1' then
IRQn <= '0';
IRQ_I <= '1';
elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' then
IRQn <= '1'; -- Clear by reading the receive data register.
end if;
-- Overrun
if OVR = '1' and RIE = '1' then
IRQn <= '0';
IRQ_I <= '1';
DCD_OVR_LOCK := true;
elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' and DCD_OVR_LOCK = false then
IRQn <= '1'; -- Clear by reading the receive data register after the status.
end if;
if DCD_In = '1' and RIE = '1' and DCD_TRANS = false then
IRQn <= '0';
IRQ_I <= '1';
-- DCD_TRANS is used to detect a low to high transition of DCDn.
DCD_TRANS := true;
DCD_OVR_LOCK := true;
elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' and DCD_OVR_LOCK = false then
IRQn <= '1'; -- Clear by reading the receive data register after the status.
elsif DCD_In = '0' then
DCD_TRANS := false;
end if;
-- The reset of the IRQ status flag:
-- Clear by writing to the transmit data register.
-- Clear by reading the receive data register.
if CS = "011" and RS = '1' and E = '1' then
IRQ_I <= '0';
if CS = "011" and RS = '1' then
IRQn <= '1';
end if;
end if;
end if;
end process P_IRQ;
CONTROL: process
CONTROL: process(CLK)
begin
wait until CLK = '1' and CLK' event;
if rising_edge(CLK) then
if RESETn = '0' then
CTRL_REG <= "01000000";
elsif CS = "011" and RWn = '0' and RS = '0' and E = '1' then
elsif CS = "011" and RWn = '0' and RS = '0' then
CTRL_REG <= DATA_IN;
end if;
end if;
end process CONTROL;
P_DCD: process
P_DCD: process(CLK)
-- This process is some kind of tricky. Refer to the MC6850 data
-- sheet for more information.
variable READ_LOCK : boolean;
variable DCD_RELEASE : boolean;
begin
wait until CLK = '1' and CLK' event;
if rising_edge(CLK) then
if RESETn = '0' then
DCD_FLAGn <= '0'; -- This interrupt source must initialise low.
READ_LOCK := true;
@@ -227,9 +184,9 @@ begin
READ_LOCK := true;
elsif DCD_In = '1' then
DCD_FLAGn <= '1';
elsif CS = "011" and RWn = '1' and RS = '0' and E = '1' then
elsif CS = "011" and RWn = '1' and RS = '0' then
READ_LOCK := false; -- Un-READ_LOCK if receiver data register is read.
elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' and READ_LOCK = false then
elsif CS = "011" and RWn = '1' and RS = '1' and READ_LOCK = false then
-- Clear if receiver status register read access.
-- After data register has ben read and READ_LOCK again.
DCD_RELEASE := true;
@@ -239,6 +196,7 @@ begin
DCD_FLAGn <= '0';
DCD_RELEASE := false;
end if;
end if;
end process P_DCD;
end architecture BEHAVIOR;

619
FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd
View File

@@ -54,362 +54,379 @@
-- Minor changes.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
entity WF6850IP_RECEIVE is
port (
CLK : in bit;
RESETn : in bit;
MCLR : in bit;
ENTITY WF6850IP_RECEIVE IS
PORT
(
CLK : IN std_logic;
RESETn : IN bit;
MCLR : IN bit;
CS : in bit_vector(2 downto 0);
E : in bit;
RWn : in bit;
RS : in bit;
CS : IN bit_vector(2 DOWNTO 0);
E : IN bit;
RWn : IN bit;
RS : IN bit;
DATA_OUT : out bit_vector(7 downto 0);
DATA_EN : out bit;
DATA_OUT : OUT bit_vector(7 DOWNTO 0);
DATA_EN : OUT bit;
WS : in bit_vector(2 downto 0);
CDS : in bit_vector(1 downto 0);
WS : IN bit_vector(2 DOWNTO 0);
CDS : IN bit_vector(1 DOWNTO 0);
RXCLK : in bit;
RXDATA : in bit;
RXCLK : IN bit;
RXDATA : IN bit;
RDRF : buffer bit;
OVR : out bit;
PE : out bit;
FE : out bit
RDRF : BUFFER bit;
OVR : OUT bit;
PE : OUT bit;
FE : OUT bit
);
end entity WF6850IP_RECEIVE;
END ENTITY WF6850IP_RECEIVE;
architecture BEHAVIOR of WF6850IP_RECEIVE is
type RCV_STATES is (IDLE, WAIT_START, SAMPLE, PARITY, STOP1, STOP2, SYNC);
signal RCV_STATE, RCV_NEXT_STATE : RCV_STATES;
signal RXDATA_I : bit;
signal RXDATA_S : bit;
signal DATA_REG : bit_vector(7 downto 0);
signal SHIFT_REG : bit_vector(7 downto 0);
signal CLK_STRB : bit;
signal BITCNT : std_logic_vector(2 downto 0);
begin
P_SAMPLE: process
-- This filter provides a synchronisation to the system
-- clock, even for random baud rates of the received data
-- stream.
variable FLT_TMP : integer range 0 to 2;
begin
wait until CLK = '1' and CLK' event;
--
RXDATA_I <= RXDATA;
--
if RXDATA_I = '1' and FLT_TMP < 2 then
FLT_TMP := FLT_TMP + 1;
elsif RXDATA_I = '1' then
RXDATA_S <= '1';
elsif RXDATA_I = '0' and FLT_TMP > 0 then
FLT_TMP := FLT_TMP - 1;
elsif RXDATA_I = '0' then
RXDATA_S <= '0';
end if;
end process P_SAMPLE;
CLKDIV: process
variable CLK_LOCK : boolean;
variable STRB_LOCK : boolean;
variable CLK_DIVCNT : std_logic_vector(6 downto 0);
begin
wait until CLK = '1' and CLK' event;
if CDS = "00" then -- Divider off.
if RXCLK = '1' and STRB_LOCK = false then
CLK_STRB <= '1';
STRB_LOCK := true;
elsif RXCLK = '0' then
CLK_STRB <= '0';
STRB_LOCK := false;
else
CLK_STRB <= '0';
end if;
elsif RCV_STATE = IDLE then
-- Preset the CLKDIV with the start delays.
if CDS = "01" then
CLK_DIVCNT := "0001000"; -- Half of div by 16 mode.
elsif CDS = "10" then
CLK_DIVCNT := "0100000"; -- Half of div by 64 mode.
end if;
CLK_STRB <= '0';
else
if CLK_DIVCNT > "0000000" and RXCLK = '1' and CLK_LOCK = false then
CLK_DIVCNT := CLK_DIVCNT - '1';
CLK_STRB <= '0';
CLK_LOCK := true;
elsif CDS = "01" and CLK_DIVCNT = "0000000" then
CLK_DIVCNT := "0010000"; -- Div by 16 mode.
--
if STRB_LOCK = false then
STRB_LOCK := true;
CLK_STRB <= '1';
else
CLK_STRB <= '0';
end if;
elsif CDS = "10" and CLK_DIVCNT = "0000000" then
CLK_DIVCNT := "1000000"; -- Div by 64 mode.
if STRB_LOCK = false then
STRB_LOCK := true;
CLK_STRB <= '1';
else
CLK_STRB <= '0';
end if;
elsif RXCLK = '0' then
CLK_LOCK := false;
STRB_LOCK := false;
CLK_STRB <= '0';
else
CLK_STRB <= '0';
end if;
end if;
end process CLKDIV;
ARCHITECTURE rtl OF WF6850IP_RECEIVE IS
TYPE RCV_STATES IS (IDLE, WAIT_START, SAMPLE, PARITY, STOP1, STOP2, SYNC);
SIGNAL RCV_STATE, RCV_NEXT_STATE : RCV_STATES;
SIGNAL RXDATA_I : bit;
SIGNAL RXDATA_S : bit;
SIGNAL DATA_REG : bit_vector(7 DOWNTO 0);
SIGNAL SHIFT_REG : bit_vector(7 DOWNTO 0);
SIGNAL CLK_STRB : bit;
SIGNAL BITCNT : std_logic_vector(2 DOWNTO 0);
BEGIN
p_sample : PROCESS(CLK)
-- This filter provides a synchronisation to the system
-- clock, even for random baud rates of the received data
-- stream.
VARIABLE FLT_TMP : integer RANGE 0 TO 2;
BEGIN
IF rising_edge(CLK) THEN
--
RXDATA_I <= RXDATA;
--
IF RXDATA_I = '1' and FLT_TMP < 2 THEN
FLT_TMP := FLT_TMP + 1;
ELSIF RXDATA_I = '1' THEN
RXDATA_S <= '1';
ELSIF RXDATA_I = '0' and FLT_TMP > 0 THEN
FLT_TMP := FLT_TMP - 1;
ELSIF RXDATA_I = '0' THEN
RXDATA_S <= '0';
END IF;
END IF;
END PROCESS p_sample;
clkdiv : PROCESS(CLK)
VARIABLE CLK_LOCK : boolean;
VARIABLE STRB_LOCK : boolean;
VARIABLE CLK_DIVCNT : std_logic_vector(6 DOWNTO 0);
BEGIN
IF rising_edge(CLK) THEN
IF CDS = "00" THEN -- Divider off.
IF RXCLK = '1' and STRB_LOCK = false THEN
CLK_STRB <= '1';
STRB_LOCK := true;
ELSIF RXCLK = '0' THEN
CLK_STRB <= '0';
STRB_LOCK := false;
ELSE
CLK_STRB <= '0';
END IF;
ELSIF RCV_STATE = IDLE THEN
-- Preset the CLKDIV with the start delays.
IF CDS = "01" THEN
CLK_DIVCNT := "0001000"; -- Half of div by 16 mode.
ELSIF CDS = "10" THEN
CLK_DIVCNT := "0100000"; -- Half of div by 64 mode.
END IF;
CLK_STRB <= '0';
ELSE
IF CLK_DIVCNT > "0000000" and RXCLK = '1' and CLK_LOCK = false THEN
CLK_DIVCNT := CLK_DIVCNT - '1';
CLK_STRB <= '0';
CLK_LOCK := true;
ELSIF CDS = "01" and CLK_DIVCNT = "0000000" THEN
CLK_DIVCNT := "0010000"; -- Div by 16 mode.
--
IF STRB_LOCK = false THEN
STRB_LOCK := true;
CLK_STRB <= '1';
ELSE
CLK_STRB <= '0';
END IF;
ELSIF CDS = "10" and CLK_DIVCNT = "0000000" THEN
CLK_DIVCNT := "1000000"; -- Div by 64 mode.
IF STRB_LOCK = false THEN
STRB_LOCK := true;
CLK_STRB <= '1';
ELSE
CLK_STRB <= '0';
END IF;
ELSIF RXCLK = '0' THEN
CLK_LOCK := false;
STRB_LOCK := false;
CLK_STRB <= '0';
ELSE
CLK_STRB <= '0';
END IF;
END IF;
END IF;
END PROCESS clkdiv;
DATAREG: process(RESETn, CLK)
begin
if RESETn = '0' then
DATA_REG <= x"00";
elsif CLK = '1' and CLK' event then
if MCLR = '1' then
datareg : PROCESS(RESETn, CLK)
BEGIN
IF RESETn = '0' or MCLR = '1' THEN
DATA_REG <= x"00";
elsif RCV_STATE = SYNC and WS(2) = '0' and RDRF = '0' then -- 7 bit data.
-- Transfer from shift- to data register only if
-- data register is empty (RDRF = '0').
DATA_REG <= '0' & SHIFT_REG(7 downto 1);
elsif RCV_STATE = SYNC and WS(2) = '1' and RDRF = '0' then -- 8 bit data.
-- Transfer from shift- to data register only if
-- data register is empty (RDRF = '0').
DATA_REG <= SHIFT_REG;
end if;
end if;
end process DATAREG;
DATA_OUT <= DATA_REG when CS = "011" and RWn = '1' and RS = '1' and E = '1' else (others => '0');
DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '1' and E = '1' else '0';
ELSE
IF rising_edge(CLK) THEN
IF RCV_STATE = SYNC and WS(2) = '0' and RDRF = '0' THEN -- 7 bit data.
-- Transfer from shift- to data register only if
-- data register is empty (RDRF = '0').
DATA_REG <= '0' & SHIFT_REG(7 downto 1);
ELSIF RCV_STATE = SYNC and WS(2) = '1' and RDRF = '0' THEN -- 8 bit data.
-- Transfer from shift- to data register only if
-- data register is empty (RDRF = '0').
DATA_REG <= SHIFT_REG;
END IF;
END IF;
END IF;
END PROCESS datareg;
DATA_OUT <= DATA_REG WHEN CS = "011" and RWn = '1' and RS = '1' ELSE (OTHERS => '0');
DATA_EN <= '1' WHEN CS = "011" and RWn = '1' and RS = '1' ELSE '0';
SHIFTREG: process(RESETn, CLK)
begin
if RESETn = '0' then
SHIFT_REG <= x"00";
elsif CLK = '1' and CLK' event then
if MCLR = '1' then
shiftreg : PROCESS(RESETn, CLK)
BEGIN
IF RESETn = '0' or MCLR = '1' THEN
SHIFT_REG <= x"00";
elsif RCV_STATE = SAMPLE and CLK_STRB = '1' then
SHIFT_REG <= RXDATA_S & SHIFT_REG(7 downto 1); -- Shift right.
end if;
end if;
end process SHIFTREG;
ELSE
IF rising_edge(CLK) THEN
IF RCV_STATE = SAMPLE and CLK_STRB = '1' THEN
SHIFT_REG <= RXDATA_S & SHIFT_REG(7 DOWNTO 1); -- Shift right.
END IF;
END IF;
END IF;
END PROCESS shiftreg;
P_BITCNT: process
begin
wait until CLK = '1' and CLK' event;
if RCV_STATE = SAMPLE and CLK_STRB = '1' then
BITCNT <= BITCNT + '1';
elsif RCV_STATE /= SAMPLE then
BITCNT <= (others => '0');
end if;
end process P_BITCNT;
p_bitcnt : PROCESS(CLK)
BEGIN
IF rising_edge(CLK) THEN
IF RCV_STATE = SAMPLE and CLK_STRB = '1' THEN
BITCNT <= BITCNT + '1';
ELSIF RCV_STATE /= SAMPLE THEN
BITCNT <= (OTHERS => '0');
END IF;
END IF;
END PROCESS p_bitcnt;
FRAME_ERR: process(RESETn, CLK)
p_frame_err: PROCESS(RESETn, CLK)
-- This module detects a framing error
-- during stop bit 1 and stop bit 2.
variable FE_I: bit;
begin
if RESETn = '0' then
VARIABLE FE_I: bit;
BEGIN
IF RESETn = '0' THEN
FE_I := '0';
FE <= '0';
elsif CLK = '1' and CLK' event then
if MCLR = '1' then
FE_I := '0';
FE <= '0';
elsif CLK_STRB = '1' then
if RCV_STATE = STOP1 and RXDATA_S = '0' then
FE_I := '1';
elsif RCV_STATE = STOP2 and RXDATA_S = '0' then
FE_I := '1';
elsif RCV_STATE = STOP1 or RCV_STATE = STOP2 then
FE_I := '0'; -- Error resets when correct data appears.
end if;
end if;
if RCV_STATE = SYNC then
FE <= FE_I; -- Update the FE every SYNC time.
end if;
end if;
end process FRAME_ERR;
ELSE
IF rising_edge(CLK) THEN
IF MCLR = '1' THEN
FE_I := '0';
FE <= '0';
ELSIF CLK_STRB = '1' THEN
IF RCV_STATE = STOP1 and RXDATA_S = '0' THEN
FE_I := '1';
ELSIF RCV_STATE = STOP2 and RXDATA_S = '0' THEN
FE_I := '1';
ELSIF RCV_STATE = STOP1 or RCV_STATE = STOP2 THEN
FE_I := '0'; -- Error resets when correct data appears.
END IF;
END IF;
IF RCV_STATE = SYNC THEN
FE <= FE_I; -- Update the FE every SYNC time.
END IF;
END IF;
END IF;
END PROCESS p_frame_err;
OVERRUN: process(RESETn, CLK)
variable OVR_I : bit;
variable FIRST_READ : boolean;
begin
if RESETn = '0' then
OVR_I := '0';
OVR <= '0';
FIRST_READ := false;
elsif CLK = '1' and CLK' event then
if MCLR = '1' then
p_overrun : PROCESS(RESETn, CLK)
VARIABLE OVR_I : bit;
VARIABLE FIRST_READ : boolean;
BEGIN
IF rising_edge(CLK) THEN
IF RESETn = '0' or MCLR = '1' THEN
OVR_I := '0';
OVR <= '0';
FIRST_READ := false;
elsif CLK_STRB = '1' and RCV_STATE = STOP1 then
-- Overrun appears if RDRF is '1' in this state.
OVR_I := RDRF;
end if;
if CS = "011" and RWn = '1' and RS = '1' and E = '1' and OVR_I = '1' then
-- If an overrun was detected, the concerning flag is
-- set when the valid data word in the receiver data
-- register is read. Thereafter the RDRF flag is reset
-- and the overrun disappears (OVR_I goes low) after
-- a second read (in time) of the receiver data register.
if FIRST_READ = false then
OVR <= '1';
FIRST_READ := true;
else
OVR <= '0';
ELSE
IF CLK_STRB = '1' and RCV_STATE = STOP1 THEN
-- Overrun appears if RDRF is '1' in this state.
OVR_I := RDRF;
END IF;
IF CS = "011" and RWn = '1' and RS = '1' THEN
-- If an overrun was detected, the concerning flag is
-- set when the valid data word in the receiver data
-- register is read. Thereafter the RDRF flag is reset
-- and the overrun disappears (OVR_I goes low) after
-- a second read (in time) of the receiver data register.
IF FIRST_READ = false THEN
IF OVR_I = '1' THEN
OVR <= '1';
OVR_I := '0';
FIRST_READ := true;
ELSE
OVR <= '0';
END IF;
END IF;
ELSE
FIRST_READ := false;
end if;
end if;
end if;
end process OVERRUN;
END IF;
END IF;
END IF;
END PROCESS p_overrun;
PARITY_TEST: process(RESETn, CLK)
variable PAR_TMP : bit;
variable PE_I : bit;
begin
if RESETn = '0' then
p_parity_test : PROCESS(RESETn,MCLR,CLK)
VARIABLE PAR_TMP : bit;
VARIABLE PE_I : bit;
BEGIN
IF RESETn = '0' or MCLR = '1' THEN
PE <= '0';
elsif CLK = '1' and CLK' event then
if MCLR = '1' then
PE <= '0';
elsif CLK_STRB = '1' then -- Sample parity on clock strobe.
PE_I := '0'; -- Initialise.
if RCV_STATE = PARITY then
for i in 1 to 7 loop
if i = 1 then
PAR_TMP := SHIFT_REG(i-1) xor SHIFT_REG(i);
else
PAR_TMP := PAR_TMP xor SHIFT_REG(i);
end if;
end loop;
if WS = "000" or WS = "010" or WS = "110" then -- Even parity.
PE_I := PAR_TMP xor RXDATA_S;
elsif WS = "001" or WS = "011" or WS = "111" then -- Odd parity.
PE_I := not PAR_TMP xor RXDATA_S;
else -- No parity for WS = "100" and WS = "101".
PE_I := '0';
end if;
end if;
end if;
ELSE
IF rising_edge(CLK) THEN
IF CLK_STRB = '1' THEN -- Sample parity on clock strobe.
PE_I := '0'; -- Initialise.
IF RCV_STATE = PARITY THEN
FOR i in 1 TO 7 LOOP
IF i = 1 THEN
PAR_TMP := SHIFT_REG(i - 1) xor SHIFT_REG(i);
ELSE
PAR_TMP := PAR_TMP xor SHIFT_REG(i);
END IF;
END LOOP;
IF WS = "000" or WS = "010" or WS = "110" THEN -- Even parity.
PE_I := PAR_TMP xor RXDATA_S;
ELSIF WS = "001" or WS = "011" or WS = "111" THEN -- Odd parity.
PE_I := not PAR_TMP xor RXDATA_S;
ELSE -- No parity for WS = "100" and WS = "101".
PE_I := '0';
END IF;
END IF;
END IF;
END IF;
-- Transmit the parity flag together with the data
-- In other words: no parity to the status register
-- when RDRF inhibits the data transfer to the
-- receiver data register.
if RCV_STATE = SYNC and RDRF = '0' then
IF RCV_STATE = SYNC and RDRF = '0' THEN
PE <= PE_I;
elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' then
ELSIF CS = "011" and RWn = '1' and RS = '1' THEN
PE <= '0'; -- Clear when reading the data register.
end if;
end if;
end process PARITY_TEST;
END IF;
END IF;
END PROCESS p_parity_test;
P_RDRF: process(RESETn, CLK)
p_rdrf : process(RESETn, CLK)
-- Receive data register full flag.
begin
if RESETn = '0' then
RDRF <= '0';
elsif CLK = '1' and CLK' event then
if MCLR = '1' then
RDRF <= '0';
elsif RCV_STATE = SYNC then
RDRF <= '1'; -- Data register is full until now!
elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' then
RDRF <= '0'; -- After reading the data register ...
end if;
end if;
end process P_RDRF;
BEGIN
IF rising_edge(CLK) THEN
IF RESETn = '0' or MCLR = '1' THEN
RDRF <= '0';
ELSE
IF RCV_STATE = SYNC THEN
RDRF <= '1'; -- Data register is full until now!
END IF;
IF CS = "011" and RWn = '1' and RS = '1' THEN
RDRF <= '0'; -- when reading the data register ...
END IF;
END IF;
END IF;
END PROCESS p_rdrf;
RCV_STATEREG: process(RESETn, CLK)
begin
if RESETn = '0' then
p_rcv_statereg : PROCESS(RESETn, CLK)
BEGIN
IF RESETn = '0' THEN
RCV_STATE <= IDLE;
elsif CLK = '1' and CLK' event then
if MCLR = '1' then
RCV_STATE <= IDLE;
else
RCV_STATE <= RCV_NEXT_STATE;
end if;
end if;
end process RCV_STATEREG;
ELSE
IF rising_edge(CLK) THEN
IF MCLR = '1' THEN
RCV_STATE <= IDLE;
ELSE
RCV_STATE <= RCV_NEXT_STATE;
END IF;
END IF;
END IF;
END PROCESS p_rcv_statereg;
RCV_STATEDEC: process(RCV_STATE, RXDATA_S, CDS, WS, BITCNT, CLK_STRB)
begin
case RCV_STATE is
when IDLE =>
if RXDATA_S = '0' and CDS = "00" then
p_rcv_statedec : PROCESS(RCV_STATE, RXDATA_S, CDS, WS, BITCNT, CLK_STRB)
BEGIN
CASE RCV_STATE IS
WHEN IDLE =>
IF RXDATA_S = '0' and CDS = "00" THEN
RCV_NEXT_STATE <= SAMPLE; -- Startbit detected in div by 1 mode.
elsif RXDATA_S = '0' and CDS = "01" then
ELSIF RXDATA_S = '0' and CDS = "01" THEN
RCV_NEXT_STATE <= WAIT_START; -- Startbit detected in div by 16 mode.
elsif RXDATA_S = '0' and CDS = "10" then
ELSIF RXDATA_S = '0' and CDS = "10" THEN
RCV_NEXT_STATE <= WAIT_START; -- Startbit detected in div by 64 mode.
else
ELSE
RCV_NEXT_STATE <= IDLE; -- No startbit; sleep well :-)
end if;
when WAIT_START =>
if CLK_STRB = '1' then
if RXDATA_S = '0' then
END IF;
WHEN WAIT_START =>
IF CLK_STRB = '1' THEN
IF RXDATA_S = '0' THEN
RCV_NEXT_STATE <= SAMPLE; -- Start condition in no div by 1 modes.
else
ELSE
RCV_NEXT_STATE <= IDLE; -- No valid start condition, go back.
end if;
else
END IF;
ELSE
RCV_NEXT_STATE <= WAIT_START; -- Stay.
end if;
when SAMPLE =>
if CLK_STRB = '1' then
if BITCNT < "110" and WS(2) = '0' then
END IF;
WHEN SAMPLE =>
IF CLK_STRB = '1' THEN
IF BITCNT < "110" and WS(2) = '0' THEN
RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 7 data bits.
elsif BITCNT < "111" and WS(2) = '1' then
ELSIF BITCNT < "111" and WS(2) = '1' THEN
RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 8 data bits.
elsif WS = "100" or WS = "101" then
ELSIF WS = "100" or WS = "101" THEN
RCV_NEXT_STATE <= STOP1; -- No parity check enabled.
else
ELSE
RCV_NEXT_STATE <= PARITY; -- Parity enabled.
end if;
else
END IF;
ELSE
RCV_NEXT_STATE <= SAMPLE; -- Stay in sample mode.
end if;
when PARITY =>
if CLK_STRB = '1' then
END IF;
WHEN PARITY =>
IF CLK_STRB = '1' THEN
RCV_NEXT_STATE <= STOP1;
else
ELSE
RCV_NEXT_STATE <= PARITY;
end if;
when STOP1 =>
if CLK_STRB = '1' then
if RXDATA_S = '0' then
END IF;
WHEN STOP1 =>
IF CLK_STRB = '1' THEN
IF RXDATA_S = '0' THEN
RCV_NEXT_STATE <= SYNC; -- Framing error detected.
elsif WS = "000" or WS = "001" or WS = "100" then
ELSIF WS = "000" or WS = "001" or WS = "100" THEN
RCV_NEXT_STATE <= STOP2; -- Two stop bits selected.
else
ELSE
RCV_NEXT_STATE <= SYNC; -- One stop bit selected.
end if;
else
END IF;
ELSE
RCV_NEXT_STATE <= STOP1;
end if;
when STOP2 =>
if CLK_STRB = '1' then
END IF;
WHEN STOP2 =>
IF CLK_STRB = '1' THEN
RCV_NEXT_STATE <= SYNC;
else
ELSE
RCV_NEXT_STATE <= STOP2;
end if;
when SYNC =>
END IF;
WHEN SYNC =>
RCV_NEXT_STATE <= IDLE;
end case;
end process RCV_STATEDEC;
end architecture BEHAVIOR;
END CASE;
END PROCESS p_rcv_statedec;
END ARCHITECTURE rtl;

10
FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd
View File

@@ -158,7 +158,6 @@ ARCHITECTURE structure OF WF6850IP_TOP_SOC IS
TXDATA : OUT bit
);
END COMPONENT;
SIGNAL DATA_IN_I : bit_vector(7 DOWNTO 0);
SIGNAL DATA_RX : bit_vector(7 DOWNTO 0);
SIGNAL DATA_RX_EN : bit;
@@ -183,8 +182,7 @@ BEGIN
IRQn <= '0' when IRQ_In = '0' else '1';
I_UART_CTRL_STATUS: WF6850IP_CTRL_STATUS
PORT MAP
(
port map(
CLK => CLK,
RESETn => RESETn,
CS(2) => CS2n,
@@ -212,8 +210,7 @@ BEGIN
);
I_UART_RECEIVE: WF6850IP_RECEIVE
PORT MAP
(
port map (
CLK => CLK,
RESETn => RESETn,
MCLR => MCLR_I,
@@ -236,8 +233,7 @@ BEGIN
);
I_UART_TRANSMIT: WF6850IP_TRANSMIT
PORT MAP
(
port map (
CLK => CLK,
RESETn => RESETn,
MCLR => MCLR_I,

45
FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd
View File

@@ -63,7 +63,7 @@ use ieee.std_logic_unsigned.all;
entity WF6850IP_TRANSMIT is
port (
CLK : in bit;
CLK : in std_logic;
RESETn : in bit;
MCLR : in bit;
@@ -108,12 +108,12 @@ begin
'1' when TR_STATE = STOP1 else
'1' when TR_STATE = STOP2 else '1';
CLKDIV: process
CLKDIV: process(CLK)
variable CLK_LOCK : boolean;
variable STRB_LOCK : boolean;
variable CLK_DIVCNT : std_logic_vector(6 downto 0);
begin
wait until CLK = '1' and CLK' event;
if rising_edge(CLK) then
if CDS = "00" then -- divider off
if TXCLK = '0' and STRB_LOCK = false then -- Works on negative TXCLK edge.
CLK_STRB <= '1';
@@ -162,13 +162,14 @@ begin
CLK_STRB <= '0';
end if;
end if;
end if;
end process CLKDIV;
DATAREG: process(RESETn, CLK)
begin
if RESETn = '0' then
DATA_REG <= x"00";
elsif CLK = '1' and CLK' event then
elsif rising_edge(CLK) then
if MCLR = '1' then
DATA_REG <= x"00";
elsif WS(2) = '0' and CS = "011" and RWn = '0' and RS = '1' and E = '1' then
@@ -183,7 +184,7 @@ begin
begin
if RESETn = '0' then
SHIFT_REG <= x"00";
elsif CLK = '1' and CLK' event then
elsif rising_edge(CLK) then
if MCLR = '1' then
SHIFT_REG <= x"00";
elsif TR_STATE = LOAD_SHFT and TDRE = '0' then
@@ -198,47 +199,42 @@ begin
end if;
end process SHIFTREG;
P_BITCNT: process
P_BITCNT: process(CLK)
-- Counter for the data bits transmitted.
begin
wait until CLK = '1' and CLK' event;
if rising_edge(CLK) then
if TR_STATE = SHIFTOUT and CLK_STRB = '1' then
BITCNT <= BITCNT + '1';
elsif TR_STATE /= SHIFTOUT then
BITCNT <= "000";
end if;
end if;
end process P_BITCNT;
P_TDRE: process(RESETn, CLK)
-- Transmit data register empty flag.
variable LOCK : boolean;
begin
if RESETn = '0' then
if rising_edge(CLK) then
if RESETn = '0' or MCLR = '1' then
TDRE <= '1';
LOCK := false;
elsif CLK = '1' and CLK' event then
if MCLR = '1' then
TDRE <= '1';
elsif TR_NEXT_STATE = START and TR_STATE /= START then
else
if TR_NEXT_STATE = START and TR_STATE /= START then
-- Data has been loaded to shift register, thus data register is free again.
-- Thanks to Lyndon Amsdon for finding a bug here. The TDRE is set to one once
-- entering the state now.
TDRE <= '1';
elsif CS = "011" and RWn = '0' and RS = '1' and E = '1' and LOCK = false then
LOCK := true;
elsif E = '0' and LOCK = true then
-- This construction clears TDRE after the falling edge of E
-- and after the transmit data register has been written to.
end if;
if CS = "011" and RWn = '0' and RS = '1' then
TDRE <= '0';
LOCK := false;
end if;
end if;
end if;
end process P_TDRE;
PARITY_GEN: process
PARITY_GEN: process(CLK)
variable PAR_TMP : bit;
begin
wait until CLK = '1' and CLK' event;
if rising_edge(CLK) then
if TR_STATE = START then -- Calculate the parity during the start phase.
for i in 1 to 7 loop
if i = 1 then
@@ -255,19 +251,22 @@ begin
PARITY_I <= '0';
end if;
end if;
end if;
end process PARITY_GEN;
TR_STATEREG: process(RESETn, CLK)
begin
if RESETn = '0' then
TR_STATE <= IDLE;
elsif CLK = '1' and CLK' event then
else
if rising_edge(CLK) then
if MCLR = '1' then
TR_STATE <= IDLE;
else
TR_STATE <= TR_NEXT_STATE;
end if;
end if;
end if;
end process TR_STATEREG;
TR_STATEDEC: process(TR_STATE, CLK_STRB, TC, BITCNT, WS, TDRE, CTSn)