renamed components to lower case

FPGA_Quartus_13.1/DSP/DSP.vhd

@@ -26,7 +26,7 @@ USE ieee.std_logic_1164.all;
 
 --  Entity Declaration
 
-ENTITY DSP IS
+ENTITY dsp IS
 	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
 	PORT
 	(
@@ -55,12 +55,12 @@ ENTITY DSP IS
 	);
 	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
 	
-END DSP;
+END dsp;
 
 
 --  Architecture Body
 
-ARCHITECTURE DSP_architecture OF DSP IS
+ARCHITECTURE rtl OF DSP IS
 
 	
 BEGIN
@@ -76,4 +76,4 @@ BEGIN
 	FB_AD(31 downto 16) <= SRD(15 downto 0) when nFB_OE = '0' and nSRCS = '0' else "ZZZZZZZZZZZZZZZZ";
 	
 	
-END DSP_architecture;
+END rtl;