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fix video base address and video counter register

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This commit is contained in:
Markus Fröschle
2016-01-14 22:02:44 +00:00
parent c4d56bb652
commit f11629ac29
2 changed files with 811 additions and 807 deletions
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36
FPGA_Quartus_13.1/Video/DDR_CTR.vhd
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@@ -521,13 +521,15 @@ BEGIN
END IF; END IF;
END PROCESS; END PROCESS;
PROCESS (REFRESH_TIME_clk) BEGIN PROCESS (REFRESH_TIME_clk)
BEGIN
IF REFRESH_TIME_clk'event and REFRESH_TIME_clk = '1' THEN IF REFRESH_TIME_clk'event and REFRESH_TIME_clk = '1' THEN
REFRESH_TIME_q <= REFRESH_TIME_d; REFRESH_TIME_q <= REFRESH_TIME_d;
END IF; END IF;
END PROCESS; END PROCESS;
PROCESS (VIDEO_BASE_L_D0_clk_ctrl) BEGIN PROCESS (VIDEO_BASE_L_D0_clk_ctrl)
BEGIN
IF VIDEO_BASE_L_D0_clk_ctrl'event and VIDEO_BASE_L_D0_clk_ctrl='1' THEN IF VIDEO_BASE_L_D0_clk_ctrl'event and VIDEO_BASE_L_D0_clk_ctrl='1' THEN
IF VIDEO_BASE_L_D0_ena_ctrl='1' THEN IF VIDEO_BASE_L_D0_ena_ctrl='1' THEN
VIDEO_BASE_L_D_q <= VIDEO_BASE_L_D_d; VIDEO_BASE_L_D_q <= VIDEO_BASE_L_D_d;
@@ -535,7 +537,8 @@ BEGIN
END IF; END IF;
END PROCESS; END PROCESS;
PROCESS (VIDEO_BASE_M_D0_clk_ctrl) BEGIN PROCESS (VIDEO_BASE_M_D0_clk_ctrl)
BEGIN
IF VIDEO_BASE_M_D0_clk_ctrl'event and VIDEO_BASE_M_D0_clk_ctrl='1' THEN IF VIDEO_BASE_M_D0_clk_ctrl'event and VIDEO_BASE_M_D0_clk_ctrl='1' THEN
IF VIDEO_BASE_M_D0_ena_ctrl='1' THEN IF VIDEO_BASE_M_D0_ena_ctrl='1' THEN
VIDEO_BASE_M_D_q <= VIDEO_BASE_M_D_d; VIDEO_BASE_M_D_q <= VIDEO_BASE_M_D_d;
@@ -543,7 +546,8 @@ BEGIN
END IF; END IF;
END PROCESS; END PROCESS;
PROCESS (VIDEO_BASE_H_D0_clk_ctrl) BEGIN PROCESS (VIDEO_BASE_H_D0_clk_ctrl)
BEGIN
IF VIDEO_BASE_H_D0_clk_ctrl'event and VIDEO_BASE_H_D0_clk_ctrl='1' THEN IF VIDEO_BASE_H_D0_clk_ctrl'event and VIDEO_BASE_H_D0_clk_ctrl='1' THEN
IF VIDEO_BASE_H_D0_ena_ctrl='1' THEN IF VIDEO_BASE_H_D0_ena_ctrl='1' THEN
VIDEO_BASE_H_D_q <= VIDEO_BASE_H_D_d; VIDEO_BASE_H_D_q <= VIDEO_BASE_H_D_d;
@@ -551,7 +555,8 @@ BEGIN
END IF; END IF;
END PROCESS; END PROCESS;
PROCESS (VIDEO_BASE_X_D0_clk_ctrl) BEGIN PROCESS (VIDEO_BASE_X_D0_clk_ctrl)
BEGIN
IF VIDEO_BASE_X_D0_clk_ctrl'event and VIDEO_BASE_X_D0_clk_ctrl='1' THEN IF VIDEO_BASE_X_D0_clk_ctrl'event and VIDEO_BASE_X_D0_clk_ctrl='1' THEN
IF VIDEO_BASE_X_D0_ena_ctrl='1' THEN IF VIDEO_BASE_X_D0_ena_ctrl='1' THEN
VIDEO_BASE_X_D_q <= VIDEO_BASE_X_D_d; VIDEO_BASE_X_D_q <= VIDEO_BASE_X_D_d;
@@ -559,7 +564,8 @@ BEGIN
END IF; END IF;
END PROCESS; END PROCESS;
PROCESS (VIDEO_ADR_CNT0_clk_ctrl) BEGIN PROCESS (VIDEO_ADR_CNT0_clk_ctrl)
BEGIN
IF VIDEO_ADR_CNT0_clk_ctrl'event and VIDEO_ADR_CNT0_clk_ctrl='1' THEN IF VIDEO_ADR_CNT0_clk_ctrl'event and VIDEO_ADR_CNT0_clk_ctrl='1' THEN
IF VIDEO_ADR_CNT0_ena_ctrl='1' THEN IF VIDEO_ADR_CNT0_ena_ctrl='1' THEN
VIDEO_ADR_CNT_q <= VIDEO_ADR_CNT_d; VIDEO_ADR_CNT_q <= VIDEO_ADR_CNT_d;
@@ -573,27 +579,21 @@ BEGIN
-- BYT SELECT -- BYT SELECT
-- ADR==0 -- ADR==0
-- LONG UND LINE -- LONG UND LINE
FB_B(0) <= to_std_logic(FB_ADR(1 DOWNTO 0) = "00") or (FB_SIZE1 and FB_B(0) <= to_std_logic(FB_ADR(1 DOWNTO 0) = "00") or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0));
FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0));
-- ADR==1 -- ADR==1
-- HIGH WORD -- HIGH WORD
-- LONG UND LINE -- LONG UND LINE
FB_B(1) <= to_std_logic(FB_ADR(1 DOWNTO 0) = "01") or (FB_SIZE1 and (not FB_B(1) <= to_std_logic(FB_ADR(1 DOWNTO 0) = "01") or (FB_SIZE1 and (not FB_SIZE0) and (not FB_ADR(1))) or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0));
FB_SIZE0) and (not FB_ADR(1))) or (FB_SIZE1 and FB_SIZE0) or ((not
FB_SIZE1) and (not FB_SIZE0));
-- ADR==2 -- ADR==2
-- LONG UND LINE -- LONG UND LINE
FB_B(2) <= to_std_logic(FB_ADR(1 DOWNTO 0) = "10") or (FB_SIZE1 and FB_B(2) <= to_std_logic(FB_ADR(1 DOWNTO 0) = "10") or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0));
FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0));
-- ADR==3 -- ADR==3
-- LOW WORD -- LOW WORD
-- LONG UND LINE -- LONG UND LINE
FB_B(3) <= to_std_logic(FB_ADR(1 DOWNTO 0) = "11") or (FB_SIZE1 and (not FB_B(3) <= to_std_logic(FB_ADR(1 DOWNTO 0) = "11") or (FB_SIZE1 and (not FB_SIZE0) and FB_ADR(1)) or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0));
FB_SIZE0) and FB_ADR(1)) or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1)
and (not FB_SIZE0));
-- CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR) -------------------------------------------------- -- CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR) --------------------------------------------------
FB_REGDDR_0_clk_ctrl <= MAIN_CLK; FB_REGDDR_0_clk_ctrl <= MAIN_CLK;
@@ -1335,6 +1335,10 @@ BEGIN
-- VIDEO_BASE_H & (0, VIDEO_BASE_X_D[]) -- VIDEO_BASE_H & (0, VIDEO_BASE_X_D[])
-- # VIDEO_CNT_H & (0, VIDEO_ACT_ADR[26..24]), -- # VIDEO_CNT_H & (0, VIDEO_ACT_ADR[26..24]),
-- (VIDEO_BASE_H # VIDEO_CNT_H) & !nFB_OE); -- (VIDEO_BASE_H # VIDEO_CNT_H) & !nFB_OE);
fb_ad(31 DOWNTO 24) <= "00000" & video_base_x_d_d WHEN video_base_h and not nfb_oe ELSE
"00000" & video_act_adr(26 DOWNTO 24) WHEN video_cnt_h and not nfb_oe ELSE
(OTHERS => 'Z');
u0_data <= (sizeIt(VIDEO_BASE_L,8) and VIDEO_BASE_L_D_q) or u0_data <= (sizeIt(VIDEO_BASE_L,8) and VIDEO_BASE_L_D_q) or
(sizeIt(VIDEO_BASE_M,8) and VIDEO_BASE_M_D_q) or (sizeIt(VIDEO_BASE_M,8) and VIDEO_BASE_M_D_q) or
(sizeIt(VIDEO_BASE_H,8) and VIDEO_BASE_H_D_q) or (sizeIt(VIDEO_BASE_H,8) and VIDEO_BASE_H_D_q) or