Firebee/FPGA_Config
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fix capitalization in include path name

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This commit is contained in:
Markus Fröschle
2019-08-28 08:11:34 +02:00
parent 6021b6ee96
commit eb3e414002
1 changed files with 19 additions and 19 deletions
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38
FPGA_by_Fredi/blitter.tdf
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@@ -20,10 +20,10 @@
-- Generated by Quartus II Version 9.1 (Build Build 350 03/24/2010)
-- Created on Sat Jan 15 11:06:17 2011
INCLUDE "lpm_bustri_WORD.inc";
INCLUDE "VIDEO/BLITTER/lpm_clshift384.INC";
INCLUDE "VIDEO/BLITTER/altsyncram0.INC";
INCLUDE "VIDEO/BLITTER/lpm_clshift144.inc";
INCLUDE "VIDEO/BLITTER/lpm_ror128.inc";
INCLUDE "Video/BLITTER/lpm_clshift384.inc";
INCLUDE "Video/BLITTER/altsyncram0.inc";
INCLUDE "Video/BLITTER/lpm_clshift144.inc";
INCLUDE "Video/BLITTER/lpm_ror128.inc";
--CONSTANT BL_SKEW_LF = 255;
@@ -151,8 +151,8 @@ VARIABLE
WREN_B :NODE; -- WR ENA HALFTONE RAM
X_INDEX_CS :NODE;
X_INDEX[15..0] :DFF; -- LAUFZEIGER X COUNT
X_INDEX_CLR :DFF; -- X INDEX L<>SCHEN CPU WRITE
X_INDEX_CLR_DIR :NODE; -- X INDEX L<>SCHEN STATE MACHINE
X_INDEX_CLR :DFF; -- X INDEX L<>SCHEN CPU WRITE
X_INDEX_CLR_DIR :NODE; -- X INDEX L<>SCHEN STATE MACHINE
DST_X_INC[15..0] :NODE; -- ANZAHL WORTE PRO DURCHLAUF
X_CNT_T[15..0] :NODE;
Y_INDEX_CS :NODE;
@@ -235,7 +235,7 @@ BEGIN
SRC_IADRH_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C520"); -- $F8A40.w
SRC_IADRL_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C521"); -- $F8A42.w
SRC_IADR_CLR.CLK = MAIN_CLK;
SRC_IADR_CLR = (BL_SRC_ADRL_CS # BL_SRC_ADRH_CS) & !nFB_WR; -- L<>SCHEN BEI WRITE
SRC_IADR_CLR = (BL_SRC_ADRL_CS # BL_SRC_ADRH_CS) & !nFB_WR; -- L<>SCHEN BEI WRITE
SRC_IADR[] = (((SRC_IADR[] + (SRC_ADR_INC[] & SDXINC)) & !ZAINC) + ((((((0,BL_X_CNT[]) - 1) * SRC_XINC32[]) + SRC_YINC32[]) * (0,Y_INDEX[])) & ZAINC)) & SRC_READ & !SRC_IADR_CLR;
SRC_ADR32[] = BL_SRC_ADR[] + SRC_IADR[]; -- ZUGRIFFSADRESSE THEORETISCH
-- ENDMASK 1
@@ -291,7 +291,7 @@ BEGIN
DST_IADRH_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C522"); -- $F8A44.w
DST_IADRL_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C523"); -- $F8A46.w
DST_IADR_CLR.CLK = MAIN_CLK;
DST_IADR_CLR = (BL_DST_ADRL_CS # BL_DST_ADRH_CS) & !nFB_WR; -- L<>SCHEN BEI WRITE
DST_IADR_CLR = (BL_DST_ADRL_CS # BL_DST_ADRH_CS) & !nFB_WR; -- L<>SCHEN BEI WRITE
DST_IADR[] = (((DST_IADR[] + (DST_ADR_INC[] & SDXINC)) & !ZAINC) + ((((((0,BL_X_CNT[]) - 1) * DST_XINC32[]) + DST_YINC32[]) * (0,Y_INDEX[])) & ZAINC)) & !DST_IADR_CLR;
DST_ADR32[] = BL_DST_ADR[] + DST_IADR[]; -- ZUGRIFFSADRESSE THEORETISCH
-- X COUNT
@@ -303,7 +303,7 @@ BEGIN
X_INDEX[].CLK = DDRCLK0;
X_INDEX_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C524"); -- $F8A48.w
X_INDEX_CLR.CLK = MAIN_CLK;
X_INDEX_CLR = BL_X_CNT_CS & !nFB_WR; -- L<>SCHEN BEI WRITE
X_INDEX_CLR = BL_X_CNT_CS & !nFB_WR; -- L<>SCHEN BEI WRITE
X_INDEX[] = ((X_INDEX[] & !ZAINC) + (DST_X_INC[] & SDXINC) + (BL_X_CNT[] & ZAINC)) & !X_INDEX_CLR & !X_INDEX_CLR_DIR;
X_CNT16[] = X_INDEX[] - (X_CNT_T[] & (X_INDEX[]!=0)); -- EFFEKTIV geschrieben
-- SCHRITTWEITEN BEI PALLETTENMOD
@@ -369,7 +369,7 @@ BEGIN
Y_INDEX[].CLK = DDRCLK0;
Y_INDEX_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C525"; -- $F8A4A.w
Y_INDEX_CLR.CLK = MAIN_CLK;
Y_INDEX_CLR = BL_Y_CNT_CS & !nFB_WR; -- L<>SCHEN BEI WRITE
Y_INDEX_CLR = BL_Y_CNT_CS & !nFB_WR; -- L<>SCHEN BEI WRITE
Y_INDEX[] = (Y_INDEX[] + (1 & YIINC)) & !Y_INDEX_CLR;
-- HOP LOGIC
BL_HOP[].CLK = MAIN_CLK;
@@ -439,7 +439,7 @@ BEGIN
BL_BSIN[127..0] = BL_SRC_BUF3[];
BL_BSIN[255..128] = BL_SRC_BUF2[];
BL_BSIN[383..256] = BL_SRC_BUF1[];
ELSE -- SONST NORMAL BEI VORW<52>RTS
ELSE -- SONST NORMAL BEI VORW<52>RTS
BL_BSIN[127..0] = BL_SRC_BUF1[];
BL_BSIN[255..128] = BL_SRC_BUF2[];
BL_BSIN[383..256] = BL_SRC_BUF3[];
@@ -529,7 +529,7 @@ BEGIN
ENDMASK1_SHIFT[3..0] = 0;
ENDMASK2_SHIFT[3..0] = 0;
ENDMASKEND[] = DST_ADR32[] + (0,(BL_X_CNT[] - X_INDEX[]) - 1) * DST_XINC32[];
IF BL_DST_X_INC15 THEN ---------------------------- R<>CKW<4B>RTS X_INC NEGATIV
IF BL_DST_X_INC15 THEN ---------------------------- R<>CKW<4B>RTS X_INC NEGATIV
IF X_INDEX[] == 0 THEN -- ENDE?
ENDMASK2_SHIFT[7..4] = 8 - (0,(DST_ADR32[3..1])); -- JA ENDMASK 3 SETZEN
ELSE
@@ -540,7 +540,7 @@ BEGIN
ELSE
ENDMASK1_SHIFT[7..4] = 0; -- NEIN -> ENDMASK 3 AUF ENDMASK2 SETZEN
END IF;
ELSE ------------------------------------------- VORW<52>RTS X_INC POSITIV (immer bei memcopy)
ELSE ------------------------------------------- VORW<52>RTS X_INC POSITIV (immer bei memcopy)
IF X_INDEX[] == 0 THEN -- ANFANG?
ENDMASK1_SHIFT[7..4] = 1 + (0,(DST_ADR32[3..1])); -- JA -> ENDMASK 1 SETZEN
ELSE
@@ -602,8 +602,8 @@ BEGIN
BL_SM = START; -- NICHT STARTEN
END IF;
WHEN NEW_LINE => ----------------------- NEU LINIE
X_INDEX_CLR_DIR = VCC; -- JA -> X INDEX L<>SCHEN F<>R START LINE
IF SRC_READ THEN -- SOURCE READ N<>TIG?
X_INDEX_CLR_DIR = VCC; -- JA -> X INDEX L<>SCHEN F<>R START LINE
IF SRC_READ THEN -- SOURCE READ N<>TIG?
BL_SM = RDSRC3; -- JA
ELSE
BL_SM = RDDST; -- NEIN -> DIREKT ZU READ DEST
@@ -668,10 +668,10 @@ BEGIN
BL_SM = TESTFERTIG; -- => TEST OB FERTIG
ELSE
IF !SRC_READ THEN -- KEIN SOURCE READ?
BL_SM = RDDST; -- JA => LESEN UNN<4E>TIG ->
BL_SM = RDDST; -- JA => LESEN UNN<4E>TIG ->
ELSE
IF SRC_ADR32[31..4] == SRC_OLD[] THEN -- ADRESSE IMMER NOCH IN DER LINE?
BL_SM = RDDST; -- DATEN SIND G<>LTIG -> READ DEST
BL_SM = RDDST; -- DATEN SIND G<>LTIG -> READ DEST
ELSE
BL_SM = RDSRC1; -- SONST NEXT SRC
END IF;
@@ -687,8 +687,8 @@ BEGIN
WHEN FERTIG => -------------------------- FERTIG
BL_NOTRUN = VCC; -- BLITTER NOT RUN
BLITTER_INT = VCC; -- BLITTER INTERRUPT
LN7_CLR = VCC; -- BUSY BIT L<>SCHEN
IF (BL_LN7 == 0) & (BL_START == 0) THEN -- WARTEN BIS GEL<45>SCHT (SYNC MIT 33MHz)
LN7_CLR = VCC; -- BUSY BIT L<>SCHEN
IF (BL_LN7 == 0) & (BL_START == 0) THEN -- WARTEN BIS GEL<45>SCHT (SYNC MIT 33MHz)
BL_SM = START;
ELSE
BL_SM = FERTIG;