From d774f3bd95bff57f9bf38f8315551ea4ebcbfc5f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 19 Aug 2018 19:01:52 +0200 Subject: [PATCH] fix formatting --- FPGA_Quartus_13.1/DSP/DSP.vhd | 101 +++++++++++++--------------------- 1 file changed, 37 insertions(+), 64 deletions(-) diff --git a/FPGA_Quartus_13.1/DSP/DSP.vhd b/FPGA_Quartus_13.1/DSP/DSP.vhd index 2873ce7..7f91a79 100644 --- a/FPGA_Quartus_13.1/DSP/DSP.vhd +++ b/FPGA_Quartus_13.1/DSP/DSP.vhd @@ -1,79 +1,52 @@ --- WARNING: Do NOT edit the input AND output ports in this file in a text --- editor if you plan to continue editing the block that represents it in --- the Block Editor! File corruption is VERY likely to occur. - --- Copyright (C) 1991-2008 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- AND other software AND tools, AND its AMPP partner logic --- functions, AND any output files from any of the foregoing --- (including device programming or simulation files), AND any --- associated documentation or information are expressly subject --- to the terms AND conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera AND sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. - - --- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008) --- Created on Tue Sep 08 16:24:57 2009 - -LIBRARY ieee; - USE ieee.std_logic_1164.all; +library ieee; + use ieee.std_logic_1164.all; -- Entity Declaration -ENTITY dsp IS - -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! - PORT +entity dsp is + port ( - CLK33M : IN std_logic; - MAIN_CLK : IN std_logic; - nFB_OE : IN std_logic; - nFB_WR : IN std_logic; - nFB_CS1 : IN std_logic; - nFB_CS2 : IN std_logic; - FB_SIZE0 : IN std_logic; - FB_SIZE1 : IN std_logic; - nFB_BURST : IN std_logic; - FB_ADR : IN std_logic_vector(31 DOWNTO 0); - nRSTO : IN std_logic; - nFB_CS3 : IN std_logic; - nSRCS : INOUT std_logic; - nSRBLE : OUT std_logic; - nSRBHE : OUT std_logic; - nSRWE : OUT std_logic; - nSROE : OUT std_logic; - DSP_INT : OUT std_logic; - DSP_TA : OUT std_logic; + CLK33M : in std_logic; + MAIN_CLK : in std_logic; + nFB_OE : in std_logic; + nFB_WR : in std_logic; + nFB_CS1 : in std_logic; + nFB_CS2 : in std_logic; + FB_SIZE0 : in std_logic; + FB_SIZE1 : in std_logic; + nFB_BURST : in std_logic; + FB_ADR : in std_logic_vector(31 downto 0); + nRSTO : in std_logic; + nFB_CS3 : in std_logic; + nSRCS : inout std_logic; + nSRBLE : out std_logic; + nSRBHE : out std_logic; + nSRWE : out std_logic; + nSROE : out std_logic; + DSP_INT : out std_logic; + DSP_TA : out std_logic; fb_ad_in : in std_logic_vector(31 downto 0); fb_ad_out : out std_logic_vector(31 downto 0); - IO : INOUT std_logic_vector(17 DOWNTO 0); - SRD : INOUT std_logic_vector(15 DOWNTO 0) + IO : inout std_logic_vector(17 downto 0); + SRD : inout std_logic_vector(15 downto 0) ); - -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! - -END dsp; +end dsp; -- Architecture Body -ARCHITECTURE rtl OF dsp IS - - -BEGIN - nSRCS <= '0' WHEN nFB_CS2 = '0' AND FB_ADR(27 DOWNTO 24) = x"4" ELSE '1'; --nFB_CS3; - nSRBHE <= '0' WHEN FB_ADR(0 DOWNTO 0) = "0" ELSE '1'; - nSRBLE <= '1' WHEN FB_ADR(0 DOWNTO 0) = "0" AND FB_SIZE1 = '0' AND FB_SIZE0 = '1' ELSE '0'; - nSRWE <= '0' WHEN nFB_WR = '0' AND nSRCS = '0' AND MAIN_CLK = '0' ELSE '1'; - nSROE <= '0' WHEN nFB_OE = '0' AND nSRCS = '0' ELSE '1'; +architecture rtl of dsp is +begin + nSRCS <= '0' when nFB_CS2 = '0' and FB_ADR(27 downto 24) = x"4" else '1'; --nFB_CS3; + nSRBHE <= '0' when FB_ADR(0 downto 0) = "0" else '1'; + nSRBLE <= '1' when FB_ADR(0 downto 0) = "0" and FB_SIZE1 = '0' and FB_SIZE0 = '1' else '0'; + nSRWE <= '0' when nFB_WR = '0' and nSRCS = '0' and MAIN_CLK = '0' else '1'; + nSROE <= '0' when nFB_OE = '0' and nSRCS = '0' else '1'; DSP_INT <= '0'; DSP_TA <= '0'; - IO(17 DOWNTO 0) <= FB_ADR(18 DOWNTO 1); - SRD(15 DOWNTO 0) <= fb_ad_in(31 DOWNTO 16) WHEN nFB_WR = '0' AND nSRCS = '0' ELSE (others => 'Z'); - -- fb_ad_out(31 DOWNTO 16) <= SRD(15 DOWNTO 0) WHEN nFB_OE = '0' AND nSRCS = '0' ELSE (others => 'Z'); + IO(17 downto 0) <= FB_ADR(18 downto 1); + SRD(15 downto 0) <= fb_ad_in(31 downto 16) when nFB_WR = '0' and nSRCS = '0' else (others => 'Z'); + -- fb_ad_out(31 downto 16) <= srd(15 DOWNTO 0 )when nFB_OE = '0' AND nSRCS = '0' ELSE (others => 'Z'); fb_ad_out(31 downto 0) <= (others => 'Z'); -- otherwise we get a constant driver error -END rtl; +end rtl;