From c4d56bb65241fddc47d52204639833b3557e90bf Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= <mfro@mubf.de>
Date: Thu, 14 Jan 2016 16:49:11 +0000
Subject: [PATCH] reformat

---
 .../Video/video_mod_mux_clutctr.vhd           | 1237 +++++++-------
 FPGA_Quartus_13.1/firebee1.qsf                | 1472 ++++++++---------
 FPGA_Quartus_13.1/firebee1.qws                |  Bin 5478 -> 4827 bytes
 3 files changed, 1356 insertions(+), 1353 deletions(-)

diff --git a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd
index be83692..50ec8f9 100755
--- a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd
+++ b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd
@@ -375,862 +375,866 @@ ARCHITECTURE rtl OF video_mod_mux_clutctr IS
     END FUNCTION to_std_logic;
 
 
-   -- sizeIt replicates a value to an array of specific length.
-   Function sizeIt(a: std_Logic; len: integer) return std_logic_vector is
-      variable rep: std_logic_vector( len-1 DOWNTO 0);
-   begin for i in rep'range loop rep(i) := a;  end loop; return rep;
-   end sizeIt;
-begin
+    -- sizeIt replicates a value to an array of specific length.
+    FUNCTION sizeit(a : std_Logic; len : integer) RETURN std_logic_vector IS
+        VARIABLE rep: std_logic_vector(len - 1 DOWNTO 0);
+    BEGIN
+        FOR i IN rep'RANGE LOOP
+            rep(i) := a;
+        END LOOP;
+        RETURN rep;
+    END FUNCTION sizeit;
 
--- Sub Module Section
-   u0: lpm_bustri_WORD port map (data=>u0_data, enabledt=>u0_enabledt,
-	 tridata=>u0_tridata);
-   u1: lpm_bustri_WORD port map (data=>u1_data, enabledt=>u1_enabledt,
-	 tridata=>u1_tridata);
+BEGIN
 
--- Register Section
+    -- Sub Module Section
+    u0 : lpm_bustri_WORD
+        PORT MAP
+        (
+            data => u0_data,
+            enabledt => u0_enabledt,
+            tridata => u0_tridata
+        );
+        
+    u1 : lpm_bustri_WORD
+        PORT MAP
+        (
+            data => u1_data,
+            enabledt => u1_enabledt,
+            tridata => u1_tridata
+        );
 
-   CLUT_MUX_ADR <= CLUT_MUX_ADR_q;
-   process (CLUT_MUX_ADR0_clk_ctrl) begin
-      if CLUT_MUX_ADR0_clk_ctrl'event and CLUT_MUX_ADR0_clk_ctrl='1' then
-	 CLUT_MUX_ADR_q <= CLUT_MUX_ADR_d;
-      end if;
-   end process;
+    -- Register Section
 
-   HSYNC <= HSYNC_q;
-   process (HSYNC_clk) begin
-      if HSYNC_clk'event and HSYNC_clk='1' then
-	 HSYNC_q <= HSYNC_d;
-      end if;
-   end process;
+    CLUT_MUX_ADR <= CLUT_MUX_ADR_q;
+    
+    PROCESS (CLUT_MUX_ADR0_clk_ctrl)
+    BEGIN
+        IF CLUT_MUX_ADR0_clk_ctrl'EVENT and CLUT_MUX_ADR0_clk_ctrl = '1' THEN
+            CLUT_MUX_ADR_q <= CLUT_MUX_ADR_d;
+        END IF;
+    END PROCESS;
 
-   VSYNC <= VSYNC_q;
-   process (VSYNC_clk) begin
-      if VSYNC_clk'event and VSYNC_clk='1' then
-	 VSYNC_q <= VSYNC_d;
-      end if;
-   end process;
+    HSYNC <= HSYNC_q;
+    PROCESS (HSYNC_clk)
+    BEGIN
+        IF HSYNC_clk'EVENT and HSYNC_clk = '1' THEN
+            HSYNC_q <= HSYNC_d;
+        END IF;
+    END PROCESS;
 
-   nBLANK <= nBLANK_q;
-   process (nBLANK_clk) begin
-      if nBLANK_clk'event and nBLANK_clk='1' then
-	 nBLANK_q <= nBLANK_d;
-      end if;
-   end process;
+    VSYNC <= VSYNC_q;
+    PROCESS (VSYNC_clk)
+    BEGIN
+        IF VSYNC_clk'EVENT and VSYNC_clk = '1' THEN
+            VSYNC_q <= VSYNC_d;
+        END IF;
+    END PROCESS;
 
-   FIFO_RDE <= FIFO_RDE_q;
-   process (FIFO_RDE_clk) begin
-      if FIFO_RDE_clk'event and FIFO_RDE_clk='1' then
-	 FIFO_RDE_q <= FIFO_RDE_d;
-      end if;
-   end process;
+    nBLANK <= nBLANK_q;
+    PROCESS (nBLANK_clk)
+    BEGIN
+        IF nBLANK_clk'EVENT and nBLANK_clk = '1' THEN
+            nBLANK_q <= nBLANK_d;
+        END IF;
+    END PROCESS;
 
-   BORDER_COLOR(23 DOWNTO 16) <= BORDER_COLOR_q(23 DOWNTO 16);
-   process (BORDER_COLOR0_clk_ctrl) begin
-      if BORDER_COLOR0_clk_ctrl'event and BORDER_COLOR0_clk_ctrl='1' then
-	 if BORDER_COLOR16_ena_ctrl='1' then
-	    (BORDER_COLOR_q(23), BORDER_COLOR_q(22), BORDER_COLOR_q(21),
-		  BORDER_COLOR_q(20), BORDER_COLOR_q(19), BORDER_COLOR_q(18),
-		  BORDER_COLOR_q(17), BORDER_COLOR_q(16)) <= BORDER_COLOR_d(23
-		  DOWNTO 16);
-	 end if;
-      end if;
-   end process;
+    FIFO_RDE <= FIFO_RDE_q;
+    PROCESS (FIFO_RDE_clk)
+    BEGIN
+        IF FIFO_RDE_clk'EVENT and FIFO_RDE_clk = '1' THEN
+            FIFO_RDE_q <= FIFO_RDE_d;
+        END IF;
+    END PROCESS;
 
-   BORDER_COLOR(15 DOWNTO 8) <= BORDER_COLOR_q(15 DOWNTO 8);
-   process (BORDER_COLOR0_clk_ctrl) begin
-      if BORDER_COLOR0_clk_ctrl'event and BORDER_COLOR0_clk_ctrl='1' then
-	 if BORDER_COLOR8_ena_ctrl='1' then
-	    (BORDER_COLOR_q(15), BORDER_COLOR_q(14), BORDER_COLOR_q(13),
-		  BORDER_COLOR_q(12), BORDER_COLOR_q(11), BORDER_COLOR_q(10),
-		  BORDER_COLOR_q(9), BORDER_COLOR_q(8)) <= BORDER_COLOR_d(15
-		  DOWNTO 8);
-	 end if;
-      end if;
-   end process;
+    BORDER_COLOR(23 DOWNTO 16) <= BORDER_COLOR_q(23 DOWNTO 16);
+    BORDER_COLOR(15 DOWNTO 8) <= BORDER_COLOR_q(15 DOWNTO 8);
+    BORDER_COLOR(7 DOWNTO 0) <= BORDER_COLOR_q(7 DOWNTO 0);
+    
+    PROCESS (BORDER_COLOR0_clk_ctrl) BEGIN
+        IF BORDER_COLOR0_clk_ctrl'EVENT and BORDER_COLOR0_clk_ctrl = '1' THEN
+            IF BORDER_COLOR16_ena_ctrl = '1' THEN
+                border_color_q(23 DOWNTO 16) <= border_color_d(23 DOWNTO 16);
+            END IF;
+            IF BORDER_COLOR8_ena_ctrl = '1' THEN
+                border_color_q(15 DOWNTO 8) <= border_color_d(15 DOWNTO 8);
+            END IF;
+            IF BORDER_COLOR0_ena_ctrl = '1' THEN
+                border_color_q(7 DOWNTO 0) <= border_color_d(7 DOWNTO 0);
+            END IF;
+        END IF;
+    END PROCESS;
 
-   BORDER_COLOR(7 DOWNTO 0) <= BORDER_COLOR_q(7 DOWNTO 0);
-   process (BORDER_COLOR0_clk_ctrl) begin
-      if BORDER_COLOR0_clk_ctrl'event and BORDER_COLOR0_clk_ctrl='1' then
-	 if BORDER_COLOR0_ena_ctrl='1' then
-	    (BORDER_COLOR_q(7), BORDER_COLOR_q(6), BORDER_COLOR_q(5),
-		  BORDER_COLOR_q(4), BORDER_COLOR_q(3), BORDER_COLOR_q(2),
-		  BORDER_COLOR_q(1), BORDER_COLOR_q(0)) <= BORDER_COLOR_d(7
-		  DOWNTO 0);
-	 end if;
-      end if;
-   end process;
+    CCSEL <= CCSEL_q;
+    PROCESS (CCSEL0_clk_ctrl)
+    BEGIN
+        IF CCSEL0_clk_ctrl'EVENT and CCSEL0_clk_ctrl = '1' THEN
+            CCSEL_q <= CCSEL_d;
+        END IF;
+    END PROCESS;
 
-   CCSEL <= CCSEL_q;
-   process (CCSEL0_clk_ctrl) begin
-      if CCSEL0_clk_ctrl'event and CCSEL0_clk_ctrl='1' then
-	 CCSEL_q <= CCSEL_d;
-      end if;
-   end process;
+    INTER_ZEI <= INTER_ZEI_q;
+    PROCESS (INTER_ZEI_clk)
+    BEGIN
+        IF INTER_ZEI_clk'EVENT and INTER_ZEI_clk = '1' THEN
+            INTER_ZEI_q <= INTER_ZEI_d;
+        END IF;
+    END PROCESS;
 
-   INTER_ZEI <= INTER_ZEI_q;
-   process (INTER_ZEI_clk) begin
-      if INTER_ZEI_clk'event and INTER_ZEI_clk='1' then
-	 INTER_ZEI_q <= INTER_ZEI_d;
-      end if;
-   end process;
+    DOP_FIFO_CLR <= DOP_FIFO_CLR_q;
+    PROCESS (DOP_FIFO_CLR_clk)
+    BEGIN
+        IF DOP_FIFO_CLR_clk'EVENT and DOP_FIFO_CLR_clk = '1' THEN
+            DOP_FIFO_CLR_q <= DOP_FIFO_CLR_d;
+        END IF;
+    END PROCESS;
 
-   DOP_FIFO_CLR <= DOP_FIFO_CLR_q;
-   process (DOP_FIFO_CLR_clk) begin
-      if DOP_FIFO_CLR_clk'event and DOP_FIFO_CLR_clk='1' then
-	 DOP_FIFO_CLR_q <= DOP_FIFO_CLR_d;
-      end if;
-   end process;
+    VIDEO_RECONFIG <= VIDEO_RECONFIG_q;
+    PROCESS (VIDEO_RECONFIG_clk)
+    BEGIN
+        IF VIDEO_RECONFIG_clk'EVENT and VIDEO_RECONFIG_clk = '1' THEN
+            VIDEO_RECONFIG_q <= VIDEO_RECONFIG_d;
+        END IF;
+    END PROCESS;
 
-   VIDEO_RECONFIG <= VIDEO_RECONFIG_q;
-   process (VIDEO_RECONFIG_clk) begin
-      if VIDEO_RECONFIG_clk'event and VIDEO_RECONFIG_clk='1' then
-	 VIDEO_RECONFIG_q <= VIDEO_RECONFIG_d;
-      end if;
-   end process;
+    VR_WR <= VR_WR_q;
+    PROCESS (VR_WR_clk)
+    BEGIN
+        IF VR_WR_clk'EVENT and VR_WR_clk = '1' THEN
+            VR_WR_q <= VR_WR_d;
+        END IF;
+    END PROCESS;
 
-   VR_WR <= VR_WR_q;
-   process (VR_WR_clk) begin
-      if VR_WR_clk'event and VR_WR_clk='1' then
-	 VR_WR_q <= VR_WR_d;
-      end if;
-   end process;
+    CLR_FIFO <= CLR_FIFO_q;
+    PROCESS (CLR_FIFO_clk)
+    BEGIN
+        IF CLR_FIFO_clk'EVENT and CLR_FIFO_clk = '1' THEN
+            IF CLR_FIFO_ena = '1' THEN
+                CLR_FIFO_q <= CLR_FIFO_d;
+            END IF;
+        END IF;
+    END PROCESS;
 
-   CLR_FIFO <= CLR_FIFO_q;
-   process (CLR_FIFO_clk) begin
-      if CLR_FIFO_clk'event and CLR_FIFO_clk='1' then
-	 if CLR_FIFO_ena='1' then
-	    CLR_FIFO_q <= CLR_FIFO_d;
-	 end if;
-      end if;
-   end process;
+    PROCESS (CLK17M_clk)
+    BEGIN
+        IF CLK17M_clk'EVENT and CLK17M_clk = '1' THEN
+            CLK17M_q <= CLK17M_d;
+        END IF;
+    END PROCESS;
 
-   process (CLK17M_clk) begin
-      if CLK17M_clk'event and CLK17M_clk='1' then
-	 CLK17M_q <= CLK17M_d;
-      end if;
-   end process;
+    PROCESS (CLK13M_clk)
+    BEGIN
+        IF CLK13M_clk'EVENT and CLK13M_clk = '1' THEN
+            CLK13M_q <= CLK13M_d;
+        END IF;
+    END PROCESS;
 
-   process (CLK13M_clk) begin
-      if CLK13M_clk'event and CLK13M_clk='1' then
-	 CLK13M_q <= CLK13M_d;
-      end if;
-   end process;
+    PROCESS (VR_DOUT0_clk_ctrl)
+    BEGIN
+        IF VR_DOUT0_clk_ctrl'EVENT and VR_DOUT0_clk_ctrl = '1' THEN
+            IF VR_DOUT0_ena_ctrl = '1' THEN
+                VR_DOUT_q <= VR_DOUT_d;
+            END IF;
+        END IF;
+    END PROCESS;
 
-   process (VR_DOUT0_clk_ctrl) begin
-      if VR_DOUT0_clk_ctrl'event and VR_DOUT0_clk_ctrl='1' then
-	 if VR_DOUT0_ena_ctrl='1' then
-	    VR_DOUT_q <= VR_DOUT_d;
-	 end if;
-      end if;
-   end process;
+    PROCESS (VR_FRQ0_clk_ctrl)
+    BEGIN
+        IF VR_FRQ0_clk_ctrl'EVENT and VR_FRQ0_clk_ctrl = '1' THEN
+            IF VR_FRQ0_ena_ctrl = '1' THEN
+                VR_FRQ_q <= VR_FRQ_d;
+            END IF;
+        END IF;
+    END PROCESS;
 
-   process (VR_FRQ0_clk_ctrl) begin
-      if VR_FRQ0_clk_ctrl'event and VR_FRQ0_clk_ctrl='1' then
-	 if VR_FRQ0_ena_ctrl='1' then
-	    VR_FRQ_q <= VR_FRQ_d;
-	 end if;
-      end if;
-   end process;
+    PROCESS (ST_SHIFT_MODE0_clk_ctrl)
+    BEGIN
+        IF ST_SHIFT_MODE0_clk_ctrl'EVENT and ST_SHIFT_MODE0_clk_ctrl = '1' THEN
+            IF ST_SHIFT_MODE0_ena_ctrl = '1' THEN
+                ST_SHIFT_MODE_q <= ST_SHIFT_MODE_d;
+            END IF;
+        END IF;
+    END PROCESS;
 
-   process (ST_SHIFT_MODE0_clk_ctrl) begin
-      if ST_SHIFT_MODE0_clk_ctrl'event and ST_SHIFT_MODE0_clk_ctrl='1' then
-	 if ST_SHIFT_MODE0_ena_ctrl='1' then
-	    ST_SHIFT_MODE_q <= ST_SHIFT_MODE_d;
-	 end if;
-      end if;
-   end process;
+    PROCESS (FALCON_SHIFT_MODE0_clk_ctrl)
+    BEGIN
+        IF FALCON_SHIFT_MODE0_clk_ctrl'EVENT and FALCON_SHIFT_MODE0_clk_ctrl = '1' THEN
+            IF FALCON_SHIFT_MODE8_ena_ctrl = '1' THEN
+                falcon_shift_mode_q(10 DOWNTO 8) <= falcon_shift_mode_d(10 DOWNTO 8);
+            END IF;
+            IF FALCON_SHIFT_MODE0_ena_ctrl = '1' THEN
+                falcon_shift_mode_q(7 DOWNTO 0) <= falcon_shift_mode_d(7 DOWNTO 0);
+            END IF;
+        END IF;
+    END PROCESS;
 
-   process (FALCON_SHIFT_MODE0_clk_ctrl) begin
-      if FALCON_SHIFT_MODE0_clk_ctrl'event and FALCON_SHIFT_MODE0_clk_ctrl='1'
-	    then
-	 if FALCON_SHIFT_MODE8_ena_ctrl='1' then
-	    (FALCON_SHIFT_MODE_q(10), FALCON_SHIFT_MODE_q(9),
-		  FALCON_SHIFT_MODE_q(8)) <= FALCON_SHIFT_MODE_d(10 DOWNTO 8);
-	 end if;
-      end if;
-   end process;
-
-   process (FALCON_SHIFT_MODE0_clk_ctrl) begin
-      if FALCON_SHIFT_MODE0_clk_ctrl'event and FALCON_SHIFT_MODE0_clk_ctrl='1'
-	    then
-	 if FALCON_SHIFT_MODE0_ena_ctrl='1' then
-	    (FALCON_SHIFT_MODE_q(7), FALCON_SHIFT_MODE_q(6),
-		  FALCON_SHIFT_MODE_q(5), FALCON_SHIFT_MODE_q(4),
-		  FALCON_SHIFT_MODE_q(3), FALCON_SHIFT_MODE_q(2),
-		  FALCON_SHIFT_MODE_q(1), FALCON_SHIFT_MODE_q(0)) <=
-		  FALCON_SHIFT_MODE_d(7 DOWNTO 0);
-	 end if;
-      end if;
-   end process;
-
-   process (CLUT_MUX_AV1_0_clk_ctrl) begin
-      if CLUT_MUX_AV1_0_clk_ctrl'event and CLUT_MUX_AV1_0_clk_ctrl='1' then
+   PROCESS (CLUT_MUX_AV1_0_clk_ctrl) BEGIN
+      if CLUT_MUX_AV1_0_clk_ctrl'EVENT and CLUT_MUX_AV1_0_clk_ctrl='1' THEN
 	 CLUT_MUX_AV1_q <= CLUT_MUX_AV1_d;
-      end if;
-   end process;
+      END IF;
+   END PROCESS;
 
-   process (CLUT_MUX_AV0_0_clk_ctrl) begin
-      if CLUT_MUX_AV0_0_clk_ctrl'event and CLUT_MUX_AV0_0_clk_ctrl='1' then
+   PROCESS (CLUT_MUX_AV0_0_clk_ctrl) BEGIN
+      if CLUT_MUX_AV0_0_clk_ctrl'EVENT and CLUT_MUX_AV0_0_clk_ctrl='1' THEN
 	 CLUT_MUX_AV0_q <= CLUT_MUX_AV0_d;
-      end if;
-   end process;
+      END IF;
+   END PROCESS;
 
-   process (ACP_VCTR0_clk_ctrl) begin
-      if ACP_VCTR0_clk_ctrl'event and ACP_VCTR0_clk_ctrl='1' then
-	 if ACP_VCTR24_ena_ctrl='1' then
+   PROCESS (ACP_VCTR0_clk_ctrl) BEGIN
+      if ACP_VCTR0_clk_ctrl'EVENT and ACP_VCTR0_clk_ctrl='1' THEN
+	 if ACP_VCTR24_ena_ctrl='1' THEN
 	    (ACP_VCTR_q(31), ACP_VCTR_q(30), ACP_VCTR_q(29), ACP_VCTR_q(28),
 		  ACP_VCTR_q(27), ACP_VCTR_q(26), ACP_VCTR_q(25),
 		  ACP_VCTR_q(24)) <= ACP_VCTR_d(31 DOWNTO 24);
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (ACP_VCTR0_clk_ctrl) begin
-      if ACP_VCTR0_clk_ctrl'event and ACP_VCTR0_clk_ctrl='1' then
-	 if ACP_VCTR16_ena_ctrl='1' then
+   PROCESS (ACP_VCTR0_clk_ctrl) BEGIN
+      if ACP_VCTR0_clk_ctrl'EVENT and ACP_VCTR0_clk_ctrl='1' THEN
+	 if ACP_VCTR16_ena_ctrl='1' THEN
 	    (ACP_VCTR_q(23), ACP_VCTR_q(22), ACP_VCTR_q(21), ACP_VCTR_q(20),
 		  ACP_VCTR_q(19), ACP_VCTR_q(18), ACP_VCTR_q(17),
 		  ACP_VCTR_q(16)) <= ACP_VCTR_d(23 DOWNTO 16);
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (ACP_VCTR0_clk_ctrl) begin
-      if ACP_VCTR0_clk_ctrl'event and ACP_VCTR0_clk_ctrl='1' then
-	 if ACP_VCTR8_ena_ctrl='1' then
+   PROCESS (ACP_VCTR0_clk_ctrl) BEGIN
+      if ACP_VCTR0_clk_ctrl'EVENT and ACP_VCTR0_clk_ctrl='1' THEN
+	 if ACP_VCTR8_ena_ctrl='1' THEN
 	    (ACP_VCTR_q(15), ACP_VCTR_q(14), ACP_VCTR_q(13), ACP_VCTR_q(12),
 		  ACP_VCTR_q(11), ACP_VCTR_q(10), ACP_VCTR_q(9), ACP_VCTR_q(8))
 		  <= ACP_VCTR_d(15 DOWNTO 8);
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (ACP_VCTR0_clk_ctrl) begin
-      if ACP_VCTR0_clk_ctrl'event and ACP_VCTR0_clk_ctrl='1' then
-	 if ACP_VCTR6_ena_ctrl='1' then
+   PROCESS (ACP_VCTR0_clk_ctrl) BEGIN
+      if ACP_VCTR0_clk_ctrl'EVENT and ACP_VCTR0_clk_ctrl='1' THEN
+	 if ACP_VCTR6_ena_ctrl='1' THEN
 	    (ACP_VCTR_q(7), ACP_VCTR_q(6)) <= ACP_VCTR_d(7 DOWNTO 6);
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (ACP_VCTR0_clk_ctrl) begin
-      if ACP_VCTR0_clk_ctrl'event and ACP_VCTR0_clk_ctrl='1' then
-	 if ACP_VCTR0_ena_ctrl='1' then
+   PROCESS (ACP_VCTR0_clk_ctrl) BEGIN
+      if ACP_VCTR0_clk_ctrl'EVENT and ACP_VCTR0_clk_ctrl='1' THEN
+	 if ACP_VCTR0_ena_ctrl='1' THEN
 	    (ACP_VCTR_q(5), ACP_VCTR_q(4), ACP_VCTR_q(3), ACP_VCTR_q(2),
 		  ACP_VCTR_q(1), ACP_VCTR_q(0)) <= ACP_VCTR_d(5 DOWNTO 0);
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (SYS_CTR0_clk_ctrl) begin
-      if SYS_CTR0_clk_ctrl'event and SYS_CTR0_clk_ctrl='1' then
-	 if SYS_CTR0_ena_ctrl='1' then
+   PROCESS (SYS_CTR0_clk_ctrl) BEGIN
+      if SYS_CTR0_clk_ctrl'EVENT and SYS_CTR0_clk_ctrl='1' THEN
+	 if SYS_CTR0_ena_ctrl='1' THEN
 	    SYS_CTR_q <= SYS_CTR_d;
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (LOF0_clk_ctrl) begin
-      if LOF0_clk_ctrl'event and LOF0_clk_ctrl='1' then
-	 if LOF8_ena_ctrl='1' then
+   PROCESS (LOF0_clk_ctrl) BEGIN
+      if LOF0_clk_ctrl'EVENT and LOF0_clk_ctrl='1' THEN
+	 if LOF8_ena_ctrl='1' THEN
 	    (LOF_q(15), LOF_q(14), LOF_q(13), LOF_q(12), LOF_q(11), LOF_q(10),
 		  LOF_q(9), LOF_q(8)) <= LOF_d(15 DOWNTO 8);
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (LOF0_clk_ctrl) begin
-      if LOF0_clk_ctrl'event and LOF0_clk_ctrl='1' then
-	 if LOF0_ena_ctrl='1' then
+   PROCESS (LOF0_clk_ctrl) BEGIN
+      if LOF0_clk_ctrl'EVENT and LOF0_clk_ctrl='1' THEN
+	 if LOF0_ena_ctrl='1' THEN
 	    (LOF_q(7), LOF_q(6), LOF_q(5), LOF_q(4), LOF_q(3), LOF_q(2),
 		  LOF_q(1), LOF_q(0)) <= LOF_d(7 DOWNTO 0);
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (LWD0_clk_ctrl) begin
-      if LWD0_clk_ctrl'event and LWD0_clk_ctrl='1' then
-	 if LWD8_ena_ctrl='1' then
+   PROCESS (LWD0_clk_ctrl) BEGIN
+      if LWD0_clk_ctrl'EVENT and LWD0_clk_ctrl='1' THEN
+	 if LWD8_ena_ctrl='1' THEN
 	    (LWD_q(15), LWD_q(14), LWD_q(13), LWD_q(12), LWD_q(11), LWD_q(10),
 		  LWD_q(9), LWD_q(8)) <= LWD_d(15 DOWNTO 8);
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (LWD0_clk_ctrl) begin
-      if LWD0_clk_ctrl'event and LWD0_clk_ctrl='1' then
-	 if LWD0_ena_ctrl='1' then
+   PROCESS (LWD0_clk_ctrl) BEGIN
+      if LWD0_clk_ctrl'EVENT and LWD0_clk_ctrl='1' THEN
+	 if LWD0_ena_ctrl='1' THEN
 	    (LWD_q(7), LWD_q(6), LWD_q(5), LWD_q(4), LWD_q(3), LWD_q(2),
 		  LWD_q(1), LWD_q(0)) <= LWD_d(7 DOWNTO 0);
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (CLUT_TA_clk) begin
-      if CLUT_TA_clk'event and CLUT_TA_clk='1' then
+   PROCESS (CLUT_TA_clk) BEGIN
+      if CLUT_TA_clk'EVENT and CLUT_TA_clk='1' THEN
 	 CLUT_TA_q <= CLUT_TA_d;
-      end if;
-   end process;
+      END IF;
+   END PROCESS;
 
-   process (HSYNC_I0_clk_ctrl) begin
-      if HSYNC_I0_clk_ctrl'event and HSYNC_I0_clk_ctrl='1' then
+   PROCESS (HSYNC_I0_clk_ctrl) BEGIN
+      if HSYNC_I0_clk_ctrl'EVENT and HSYNC_I0_clk_ctrl='1' THEN
 	 HSYNC_I_q <= HSYNC_I_d;
-      end if;
-   end process;
+      END IF;
+   END PROCESS;
 
-   process (HSY_LEN0_clk_ctrl) begin
-      if HSY_LEN0_clk_ctrl'event and HSY_LEN0_clk_ctrl='1' then
+   PROCESS (HSY_LEN0_clk_ctrl) BEGIN
+      if HSY_LEN0_clk_ctrl'EVENT and HSY_LEN0_clk_ctrl='1' THEN
 	 HSY_LEN_q <= HSY_LEN_d;
-      end if;
-   end process;
+      END IF;
+   END PROCESS;
 
-   process (HSYNC_START_clk) begin
-      if HSYNC_START_clk'event and HSYNC_START_clk='1' then
+   PROCESS (HSYNC_START_clk) BEGIN
+      if HSYNC_START_clk'EVENT and HSYNC_START_clk='1' THEN
 	 HSYNC_START_q <= HSYNC_START_d;
-      end if;
-   end process;
+      END IF;
+   END PROCESS;
 
-   process (LAST_clk) begin
-      if LAST_clk'event and LAST_clk='1' then
+   PROCESS (LAST_clk) BEGIN
+      if LAST_clk'EVENT and LAST_clk='1' THEN
 	 LAST_q <= LAST_d;
-      end if;
-   end process;
+      END IF;
+   END PROCESS;
 
-   process (VSYNC_START_clk) begin
-      if VSYNC_START_clk'event and VSYNC_START_clk='1' then
-	 if VSYNC_START_ena='1' then
+   PROCESS (VSYNC_START_clk) BEGIN
+      if VSYNC_START_clk'EVENT and VSYNC_START_clk='1' THEN
+	 if VSYNC_START_ena='1' THEN
 	    VSYNC_START_q <= VSYNC_START_d;
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (VSYNC_I0_clk_ctrl) begin
-      if VSYNC_I0_clk_ctrl'event and VSYNC_I0_clk_ctrl='1' then
-	 if VSYNC_I0_ena_ctrl='1' then
+   PROCESS (VSYNC_I0_clk_ctrl) BEGIN
+      if VSYNC_I0_clk_ctrl'EVENT and VSYNC_I0_clk_ctrl='1' THEN
+	 if VSYNC_I0_ena_ctrl='1' THEN
 	    VSYNC_I_q <= VSYNC_I_d;
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (DISP_ON_clk) begin
-      if DISP_ON_clk'event and DISP_ON_clk='1' then
+   PROCESS (DISP_ON_clk) BEGIN
+      if DISP_ON_clk'EVENT and DISP_ON_clk='1' THEN
 	 DISP_ON_q <= DISP_ON_d;
-      end if;
-   end process;
+      END IF;
+   END PROCESS;
 
-   process (DPO_ZL_clk) begin
-      if DPO_ZL_clk'event and DPO_ZL_clk='1' then
-	 if DPO_ZL_ena='1' then
+   PROCESS (DPO_ZL_clk) BEGIN
+      if DPO_ZL_clk'EVENT and DPO_ZL_clk='1' THEN
+	 if DPO_ZL_ena='1' THEN
 	    DPO_ZL_q <= DPO_ZL_d;
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (DPO_ON_clk) begin
-      if DPO_ON_clk'event and DPO_ON_clk='1' then
+   PROCESS (DPO_ON_clk) BEGIN
+      if DPO_ON_clk'EVENT and DPO_ON_clk='1' THEN
 	 DPO_ON_q <= DPO_ON_d;
-      end if;
-   end process;
+      END IF;
+   END PROCESS;
 
-   process (DPO_OFF_clk) begin
-      if DPO_OFF_clk'event and DPO_OFF_clk='1' then
+   PROCESS (DPO_OFF_clk) BEGIN
+      if DPO_OFF_clk'EVENT and DPO_OFF_clk='1' THEN
 	 DPO_OFF_q <= DPO_OFF_d;
-      end if;
-   end process;
+      END IF;
+   END PROCESS;
 
-   process (VDTRON_clk) begin
-      if VDTRON_clk'event and VDTRON_clk='1' then
+   PROCESS (VDTRON_clk) BEGIN
+      if VDTRON_clk'EVENT and VDTRON_clk='1' THEN
 	 VDTRON_q <= VDTRON_d;
-      end if;
-   end process;
+      END IF;
+   END PROCESS;
 
-   process (VCO_ZL_clk) begin
-      if VCO_ZL_clk'event and VCO_ZL_clk='1' then
-	 if VCO_ZL_ena='1' then
+   PROCESS (VCO_ZL_clk) BEGIN
+      if VCO_ZL_clk'EVENT and VCO_ZL_clk='1' THEN
+	 if VCO_ZL_ena='1' THEN
 	    VCO_ZL_q <= VCO_ZL_d;
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (VCO_ON_clk) begin
-      if VCO_ON_clk'event and VCO_ON_clk='1' then
+   PROCESS (VCO_ON_clk) BEGIN
+      if VCO_ON_clk'EVENT and VCO_ON_clk='1' THEN
 	 VCO_ON_q <= VCO_ON_d;
-      end if;
-   end process;
+      END IF;
+   END PROCESS;
 
-   process (VCO_OFF_clk) begin
-      if VCO_OFF_clk'event and VCO_OFF_clk='1' then
+   PROCESS (VCO_OFF_clk) BEGIN
+      if VCO_OFF_clk'EVENT and VCO_OFF_clk='1' THEN
 	 VCO_OFF_q <= VCO_OFF_d;
-      end if;
-   end process;
+      END IF;
+   END PROCESS;
 
-   process (VHCNT0_clk_ctrl) begin
-      if VHCNT0_clk_ctrl'event and VHCNT0_clk_ctrl='1' then
+   PROCESS (VHCNT0_clk_ctrl) BEGIN
+      if VHCNT0_clk_ctrl'EVENT and VHCNT0_clk_ctrl='1' THEN
 	 VHCNT_q <= VHCNT_d;
-      end if;
-   end process;
+      END IF;
+   END PROCESS;
 
-   process (SUB_PIXEL_CNT0_clk_ctrl) begin
-      if SUB_PIXEL_CNT0_clk_ctrl'event and SUB_PIXEL_CNT0_clk_ctrl='1' then
-	 if SUB_PIXEL_CNT0_ena_ctrl='1' then
+   PROCESS (SUB_PIXEL_CNT0_clk_ctrl) BEGIN
+      if SUB_PIXEL_CNT0_clk_ctrl'EVENT and SUB_PIXEL_CNT0_clk_ctrl='1' THEN
+	 if SUB_PIXEL_CNT0_ena_ctrl='1' THEN
 	    SUB_PIXEL_CNT_q <= SUB_PIXEL_CNT_d;
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (VVCNT0_clk_ctrl) begin
-      if VVCNT0_clk_ctrl'event and VVCNT0_clk_ctrl='1' then
-	 if VVCNT0_ena_ctrl='1' then
+   PROCESS (VVCNT0_clk_ctrl) BEGIN
+      if VVCNT0_clk_ctrl'EVENT and VVCNT0_clk_ctrl='1' THEN
+	 if VVCNT0_ena_ctrl='1' THEN
 	    VVCNT_q <= VVCNT_d;
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (VERZ2_0_clk_ctrl) begin
-      if VERZ2_0_clk_ctrl'event and VERZ2_0_clk_ctrl='1' then
+   PROCESS (VERZ2_0_clk_ctrl) BEGIN
+      if VERZ2_0_clk_ctrl'EVENT and VERZ2_0_clk_ctrl='1' THEN
 	 VERZ2_q <= VERZ2_d;
-      end if;
-   end process;
+      END IF;
+   END PROCESS;
 
-   process (VERZ1_0_clk_ctrl) begin
-      if VERZ1_0_clk_ctrl'event and VERZ1_0_clk_ctrl='1' then
+   PROCESS (VERZ1_0_clk_ctrl) BEGIN
+      if VERZ1_0_clk_ctrl'EVENT and VERZ1_0_clk_ctrl='1' THEN
 	 VERZ1_q <= VERZ1_d;
-      end if;
-   end process;
+      END IF;
+   END PROCESS;
 
-   process (VERZ0_0_clk_ctrl) begin
-      if VERZ0_0_clk_ctrl'event and VERZ0_0_clk_ctrl='1' then
+   PROCESS (VERZ0_0_clk_ctrl) BEGIN
+      if VERZ0_0_clk_ctrl'EVENT and VERZ0_0_clk_ctrl='1' THEN
 	 VERZ0_q <= VERZ0_d;
-      end if;
-   end process;
+      END IF;
+   END PROCESS;
 
-   process (RAND0_clk_ctrl) begin
-      if RAND0_clk_ctrl'event and RAND0_clk_ctrl='1' then
+   PROCESS (RAND0_clk_ctrl) BEGIN
+      if RAND0_clk_ctrl'EVENT and RAND0_clk_ctrl='1' THEN
 	 RAND_q <= RAND_d;
-      end if;
-   end process;
+      END IF;
+   END PROCESS;
 
-   process (START_ZEILE_clk) begin
-      if START_ZEILE_clk'event and START_ZEILE_clk='1' then
-	 if START_ZEILE_ena='1' then
+   PROCESS (START_ZEILE_clk) BEGIN
+      if START_ZEILE_clk'EVENT and START_ZEILE_clk='1' THEN
+	 if START_ZEILE_ena='1' THEN
 	    START_ZEILE_q <= START_ZEILE_d;
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (SYNC_PIX_clk) begin
-      if SYNC_PIX_clk'event and SYNC_PIX_clk='1' then
+   PROCESS (SYNC_PIX_clk) BEGIN
+      if SYNC_PIX_clk'EVENT and SYNC_PIX_clk='1' THEN
 	 SYNC_PIX_q <= SYNC_PIX_d;
-      end if;
-   end process;
+      END IF;
+   END PROCESS;
 
-   process (SYNC_PIX1_clk) begin
-      if SYNC_PIX1_clk'event and SYNC_PIX1_clk='1' then
+   PROCESS (SYNC_PIX1_clk) BEGIN
+      if SYNC_PIX1_clk'EVENT and SYNC_PIX1_clk='1' THEN
 	 SYNC_PIX1_q <= SYNC_PIX1_d;
-      end if;
-   end process;
+      END IF;
+   END PROCESS;
 
-   process (SYNC_PIX2_clk) begin
-      if SYNC_PIX2_clk'event and SYNC_PIX2_clk='1' then
+   PROCESS (SYNC_PIX2_clk) BEGIN
+      if SYNC_PIX2_clk'EVENT and SYNC_PIX2_clk='1' THEN
 	 SYNC_PIX2_q <= SYNC_PIX2_d;
-      end if;
-   end process;
+      END IF;
+   END PROCESS;
 
-   process (ATARI_HH0_clk_ctrl) begin
-      if ATARI_HH0_clk_ctrl'event and ATARI_HH0_clk_ctrl='1' then
-	 if ATARI_HH24_ena_ctrl='1' then
+   PROCESS (ATARI_HH0_clk_ctrl) BEGIN
+      if ATARI_HH0_clk_ctrl'EVENT and ATARI_HH0_clk_ctrl='1' THEN
+	 if ATARI_HH24_ena_ctrl='1' THEN
 	    (ATARI_HH_q(31), ATARI_HH_q(30), ATARI_HH_q(29), ATARI_HH_q(28),
 		  ATARI_HH_q(27), ATARI_HH_q(26), ATARI_HH_q(25),
 		  ATARI_HH_q(24)) <= ATARI_HH_d(31 DOWNTO 24);
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (ATARI_HH0_clk_ctrl) begin
-      if ATARI_HH0_clk_ctrl'event and ATARI_HH0_clk_ctrl='1' then
-	 if ATARI_HH16_ena_ctrl='1' then
+   PROCESS (ATARI_HH0_clk_ctrl) BEGIN
+      if ATARI_HH0_clk_ctrl'EVENT and ATARI_HH0_clk_ctrl='1' THEN
+	 if ATARI_HH16_ena_ctrl='1' THEN
 	    (ATARI_HH_q(23), ATARI_HH_q(22), ATARI_HH_q(21), ATARI_HH_q(20),
 		  ATARI_HH_q(19), ATARI_HH_q(18), ATARI_HH_q(17),
 		  ATARI_HH_q(16)) <= ATARI_HH_d(23 DOWNTO 16);
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (ATARI_HH0_clk_ctrl) begin
-      if ATARI_HH0_clk_ctrl'event and ATARI_HH0_clk_ctrl='1' then
-	 if ATARI_HH8_ena_ctrl='1' then
+   PROCESS (ATARI_HH0_clk_ctrl) BEGIN
+      if ATARI_HH0_clk_ctrl'EVENT and ATARI_HH0_clk_ctrl='1' THEN
+	 if ATARI_HH8_ena_ctrl='1' THEN
 	    (ATARI_HH_q(15), ATARI_HH_q(14), ATARI_HH_q(13), ATARI_HH_q(12),
 		  ATARI_HH_q(11), ATARI_HH_q(10), ATARI_HH_q(9), ATARI_HH_q(8))
 		  <= ATARI_HH_d(15 DOWNTO 8);
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (ATARI_HH0_clk_ctrl) begin
-      if ATARI_HH0_clk_ctrl'event and ATARI_HH0_clk_ctrl='1' then
-	 if ATARI_HH0_ena_ctrl='1' then
+   PROCESS (ATARI_HH0_clk_ctrl) BEGIN
+      if ATARI_HH0_clk_ctrl'EVENT and ATARI_HH0_clk_ctrl='1' THEN
+	 if ATARI_HH0_ena_ctrl='1' THEN
 	    (ATARI_HH_q(7), ATARI_HH_q(6), ATARI_HH_q(5), ATARI_HH_q(4),
 		  ATARI_HH_q(3), ATARI_HH_q(2), ATARI_HH_q(1), ATARI_HH_q(0))
 		  <= ATARI_HH_d(7 DOWNTO 0);
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (ATARI_VH0_clk_ctrl) begin
-      if ATARI_VH0_clk_ctrl'event and ATARI_VH0_clk_ctrl='1' then
-	 if ATARI_VH24_ena_ctrl='1' then
+   PROCESS (ATARI_VH0_clk_ctrl) BEGIN
+      if ATARI_VH0_clk_ctrl'EVENT and ATARI_VH0_clk_ctrl='1' THEN
+	 if ATARI_VH24_ena_ctrl='1' THEN
 	    (ATARI_VH_q(31), ATARI_VH_q(30), ATARI_VH_q(29), ATARI_VH_q(28),
 		  ATARI_VH_q(27), ATARI_VH_q(26), ATARI_VH_q(25),
 		  ATARI_VH_q(24)) <= ATARI_VH_d(31 DOWNTO 24);
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (ATARI_VH0_clk_ctrl) begin
-      if ATARI_VH0_clk_ctrl'event and ATARI_VH0_clk_ctrl='1' then
-	 if ATARI_VH16_ena_ctrl='1' then
+   PROCESS (ATARI_VH0_clk_ctrl) BEGIN
+      if ATARI_VH0_clk_ctrl'EVENT and ATARI_VH0_clk_ctrl='1' THEN
+	 if ATARI_VH16_ena_ctrl='1' THEN
 	    (ATARI_VH_q(23), ATARI_VH_q(22), ATARI_VH_q(21), ATARI_VH_q(20),
 		  ATARI_VH_q(19), ATARI_VH_q(18), ATARI_VH_q(17),
 		  ATARI_VH_q(16)) <= ATARI_VH_d(23 DOWNTO 16);
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (ATARI_VH0_clk_ctrl) begin
-      if ATARI_VH0_clk_ctrl'event and ATARI_VH0_clk_ctrl='1' then
-	 if ATARI_VH8_ena_ctrl='1' then
+   PROCESS (ATARI_VH0_clk_ctrl) BEGIN
+      if ATARI_VH0_clk_ctrl'EVENT and ATARI_VH0_clk_ctrl='1' THEN
+	 if ATARI_VH8_ena_ctrl='1' THEN
 	    (ATARI_VH_q(15), ATARI_VH_q(14), ATARI_VH_q(13), ATARI_VH_q(12),
 		  ATARI_VH_q(11), ATARI_VH_q(10), ATARI_VH_q(9), ATARI_VH_q(8))
 		  <= ATARI_VH_d(15 DOWNTO 8);
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (ATARI_VH0_clk_ctrl) begin
-      if ATARI_VH0_clk_ctrl'event and ATARI_VH0_clk_ctrl='1' then
-	 if ATARI_VH0_ena_ctrl='1' then
+   PROCESS (ATARI_VH0_clk_ctrl) BEGIN
+      if ATARI_VH0_clk_ctrl'EVENT and ATARI_VH0_clk_ctrl='1' THEN
+	 if ATARI_VH0_ena_ctrl='1' THEN
 	    (ATARI_VH_q(7), ATARI_VH_q(6), ATARI_VH_q(5), ATARI_VH_q(4),
 		  ATARI_VH_q(3), ATARI_VH_q(2), ATARI_VH_q(1), ATARI_VH_q(0))
 		  <= ATARI_VH_d(7 DOWNTO 0);
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (ATARI_HL0_clk_ctrl) begin
-      if ATARI_HL0_clk_ctrl'event and ATARI_HL0_clk_ctrl='1' then
-	 if ATARI_HL24_ena_ctrl='1' then
+   PROCESS (ATARI_HL0_clk_ctrl) BEGIN
+      if ATARI_HL0_clk_ctrl'EVENT and ATARI_HL0_clk_ctrl='1' THEN
+	 if ATARI_HL24_ena_ctrl='1' THEN
 	    (ATARI_HL_q(31), ATARI_HL_q(30), ATARI_HL_q(29), ATARI_HL_q(28),
 		  ATARI_HL_q(27), ATARI_HL_q(26), ATARI_HL_q(25),
 		  ATARI_HL_q(24)) <= ATARI_HL_d(31 DOWNTO 24);
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (ATARI_HL0_clk_ctrl) begin
-      if ATARI_HL0_clk_ctrl'event and ATARI_HL0_clk_ctrl='1' then
-	 if ATARI_HL16_ena_ctrl='1' then
+   PROCESS (ATARI_HL0_clk_ctrl) BEGIN
+      if ATARI_HL0_clk_ctrl'EVENT and ATARI_HL0_clk_ctrl='1' THEN
+	 if ATARI_HL16_ena_ctrl='1' THEN
 	    (ATARI_HL_q(23), ATARI_HL_q(22), ATARI_HL_q(21), ATARI_HL_q(20),
 		  ATARI_HL_q(19), ATARI_HL_q(18), ATARI_HL_q(17),
 		  ATARI_HL_q(16)) <= ATARI_HL_d(23 DOWNTO 16);
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (ATARI_HL0_clk_ctrl) begin
-      if ATARI_HL0_clk_ctrl'event and ATARI_HL0_clk_ctrl='1' then
-	 if ATARI_HL8_ena_ctrl='1' then
+   PROCESS (ATARI_HL0_clk_ctrl) BEGIN
+      if ATARI_HL0_clk_ctrl'EVENT and ATARI_HL0_clk_ctrl='1' THEN
+	 if ATARI_HL8_ena_ctrl='1' THEN
 	    (ATARI_HL_q(15), ATARI_HL_q(14), ATARI_HL_q(13), ATARI_HL_q(12),
 		  ATARI_HL_q(11), ATARI_HL_q(10), ATARI_HL_q(9), ATARI_HL_q(8))
 		  <= ATARI_HL_d(15 DOWNTO 8);
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (ATARI_HL0_clk_ctrl) begin
-      if ATARI_HL0_clk_ctrl'event and ATARI_HL0_clk_ctrl='1' then
-	 if ATARI_HL0_ena_ctrl='1' then
+   PROCESS (ATARI_HL0_clk_ctrl) BEGIN
+      if ATARI_HL0_clk_ctrl'EVENT and ATARI_HL0_clk_ctrl='1' THEN
+	 if ATARI_HL0_ena_ctrl='1' THEN
 	    (ATARI_HL_q(7), ATARI_HL_q(6), ATARI_HL_q(5), ATARI_HL_q(4),
 		  ATARI_HL_q(3), ATARI_HL_q(2), ATARI_HL_q(1), ATARI_HL_q(0))
 		  <= ATARI_HL_d(7 DOWNTO 0);
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (ATARI_VL0_clk_ctrl) begin
-      if ATARI_VL0_clk_ctrl'event and ATARI_VL0_clk_ctrl='1' then
-	 if ATARI_VL24_ena_ctrl='1' then
+   PROCESS (ATARI_VL0_clk_ctrl) BEGIN
+      if ATARI_VL0_clk_ctrl'EVENT and ATARI_VL0_clk_ctrl='1' THEN
+	 if ATARI_VL24_ena_ctrl='1' THEN
 	    (ATARI_VL_q(31), ATARI_VL_q(30), ATARI_VL_q(29), ATARI_VL_q(28),
 		  ATARI_VL_q(27), ATARI_VL_q(26), ATARI_VL_q(25),
 		  ATARI_VL_q(24)) <= ATARI_VL_d(31 DOWNTO 24);
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (ATARI_VL0_clk_ctrl) begin
-      if ATARI_VL0_clk_ctrl'event and ATARI_VL0_clk_ctrl='1' then
-	 if ATARI_VL16_ena_ctrl='1' then
+   PROCESS (ATARI_VL0_clk_ctrl) BEGIN
+      if ATARI_VL0_clk_ctrl'EVENT and ATARI_VL0_clk_ctrl='1' THEN
+	 if ATARI_VL16_ena_ctrl='1' THEN
 	    (ATARI_VL_q(23), ATARI_VL_q(22), ATARI_VL_q(21), ATARI_VL_q(20),
 		  ATARI_VL_q(19), ATARI_VL_q(18), ATARI_VL_q(17),
 		  ATARI_VL_q(16)) <= ATARI_VL_d(23 DOWNTO 16);
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (ATARI_VL0_clk_ctrl) begin
-      if ATARI_VL0_clk_ctrl'event and ATARI_VL0_clk_ctrl='1' then
-	 if ATARI_VL8_ena_ctrl='1' then
+   PROCESS (ATARI_VL0_clk_ctrl) BEGIN
+      if ATARI_VL0_clk_ctrl'EVENT and ATARI_VL0_clk_ctrl='1' THEN
+	 if ATARI_VL8_ena_ctrl='1' THEN
 	    (ATARI_VL_q(15), ATARI_VL_q(14), ATARI_VL_q(13), ATARI_VL_q(12),
 		  ATARI_VL_q(11), ATARI_VL_q(10), ATARI_VL_q(9), ATARI_VL_q(8))
 		  <= ATARI_VL_d(15 DOWNTO 8);
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (ATARI_VL0_clk_ctrl) begin
-      if ATARI_VL0_clk_ctrl'event and ATARI_VL0_clk_ctrl='1' then
-	 if ATARI_VL0_ena_ctrl='1' then
+   PROCESS (ATARI_VL0_clk_ctrl) BEGIN
+      if ATARI_VL0_clk_ctrl'EVENT and ATARI_VL0_clk_ctrl='1' THEN
+	 if ATARI_VL0_ena_ctrl='1' THEN
 	    (ATARI_VL_q(7), ATARI_VL_q(6), ATARI_VL_q(5), ATARI_VL_q(4),
 		  ATARI_VL_q(3), ATARI_VL_q(2), ATARI_VL_q(1), ATARI_VL_q(0))
 		  <= ATARI_VL_d(7 DOWNTO 0);
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (HHT0_clk_ctrl) begin
-      if HHT0_clk_ctrl'event and HHT0_clk_ctrl='1' then
-	 if HHT8_ena_ctrl='1' then
+   PROCESS (HHT0_clk_ctrl) BEGIN
+      if HHT0_clk_ctrl'EVENT and HHT0_clk_ctrl='1' THEN
+	 if HHT8_ena_ctrl='1' THEN
 	    (HHT_q(11), HHT_q(10), HHT_q(9), HHT_q(8)) <= HHT_d(11 DOWNTO 8);
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (HHT0_clk_ctrl) begin
-      if HHT0_clk_ctrl'event and HHT0_clk_ctrl='1' then
-	 if HHT0_ena_ctrl='1' then
+   PROCESS (HHT0_clk_ctrl) BEGIN
+      if HHT0_clk_ctrl'EVENT and HHT0_clk_ctrl='1' THEN
+	 if HHT0_ena_ctrl='1' THEN
 	    (HHT_q(7), HHT_q(6), HHT_q(5), HHT_q(4), HHT_q(3), HHT_q(2),
 		  HHT_q(1), HHT_q(0)) <= HHT_d(7 DOWNTO 0);
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (HBE0_clk_ctrl) begin
-      if HBE0_clk_ctrl'event and HBE0_clk_ctrl='1' then
-	 if HBE8_ena_ctrl='1' then
+   PROCESS (HBE0_clk_ctrl) BEGIN
+      if HBE0_clk_ctrl'EVENT and HBE0_clk_ctrl='1' THEN
+	 if HBE8_ena_ctrl='1' THEN
 	    (HBE_q(11), HBE_q(10), HBE_q(9), HBE_q(8)) <= HBE_d(11 DOWNTO 8);
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (HBE0_clk_ctrl) begin
-      if HBE0_clk_ctrl'event and HBE0_clk_ctrl='1' then
-	 if HBE0_ena_ctrl='1' then
+   PROCESS (HBE0_clk_ctrl) BEGIN
+      if HBE0_clk_ctrl'EVENT and HBE0_clk_ctrl='1' THEN
+	 if HBE0_ena_ctrl='1' THEN
 	    (HBE_q(7), HBE_q(6), HBE_q(5), HBE_q(4), HBE_q(3), HBE_q(2),
 		  HBE_q(1), HBE_q(0)) <= HBE_d(7 DOWNTO 0);
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (HDB0_clk_ctrl) begin
-      if HDB0_clk_ctrl'event and HDB0_clk_ctrl='1' then
-	 if HDB8_ena_ctrl='1' then
+   PROCESS (HDB0_clk_ctrl) BEGIN
+      if HDB0_clk_ctrl'EVENT and HDB0_clk_ctrl='1' THEN
+	 if HDB8_ena_ctrl='1' THEN
 	    (HDB_q(11), HDB_q(10), HDB_q(9), HDB_q(8)) <= HDB_d(11 DOWNTO 8);
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (HDB0_clk_ctrl) begin
-      if HDB0_clk_ctrl'event and HDB0_clk_ctrl='1' then
-	 if HDB0_ena_ctrl='1' then
+   PROCESS (HDB0_clk_ctrl) BEGIN
+      if HDB0_clk_ctrl'EVENT and HDB0_clk_ctrl='1' THEN
+	 if HDB0_ena_ctrl='1' THEN
 	    (HDB_q(7), HDB_q(6), HDB_q(5), HDB_q(4), HDB_q(3), HDB_q(2),
 		  HDB_q(1), HDB_q(0)) <= HDB_d(7 DOWNTO 0);
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (HDE0_clk_ctrl) begin
-      if HDE0_clk_ctrl'event and HDE0_clk_ctrl='1' then
-	 if HDE8_ena_ctrl='1' then
+   PROCESS (HDE0_clk_ctrl) BEGIN
+      if HDE0_clk_ctrl'EVENT and HDE0_clk_ctrl='1' THEN
+	 if HDE8_ena_ctrl='1' THEN
 	    (HDE_q(11), HDE_q(10), HDE_q(9), HDE_q(8)) <= HDE_d(11 DOWNTO 8);
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (HDE0_clk_ctrl) begin
-      if HDE0_clk_ctrl'event and HDE0_clk_ctrl='1' then
-	 if HDE0_ena_ctrl='1' then
+   PROCESS (HDE0_clk_ctrl) BEGIN
+      if HDE0_clk_ctrl'EVENT and HDE0_clk_ctrl='1' THEN
+	 if HDE0_ena_ctrl='1' THEN
 	    (HDE_q(7), HDE_q(6), HDE_q(5), HDE_q(4), HDE_q(3), HDE_q(2),
 		  HDE_q(1), HDE_q(0)) <= HDE_d(7 DOWNTO 0);
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (HBB0_clk_ctrl) begin
-      if HBB0_clk_ctrl'event and HBB0_clk_ctrl='1' then
-	 if HBB8_ena_ctrl='1' then
+   PROCESS (HBB0_clk_ctrl) BEGIN
+      if HBB0_clk_ctrl'EVENT and HBB0_clk_ctrl='1' THEN
+	 if HBB8_ena_ctrl='1' THEN
 	    (HBB_q(11), HBB_q(10), HBB_q(9), HBB_q(8)) <= HBB_d(11 DOWNTO 8);
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (HBB0_clk_ctrl) begin
-      if HBB0_clk_ctrl'event and HBB0_clk_ctrl='1' then
-	 if HBB0_ena_ctrl='1' then
+   PROCESS (HBB0_clk_ctrl) BEGIN
+      if HBB0_clk_ctrl'EVENT and HBB0_clk_ctrl='1' THEN
+	 if HBB0_ena_ctrl='1' THEN
 	    (HBB_q(7), HBB_q(6), HBB_q(5), HBB_q(4), HBB_q(3), HBB_q(2),
 		  HBB_q(1), HBB_q(0)) <= HBB_d(7 DOWNTO 0);
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (HSS0_clk_ctrl) begin
-      if HSS0_clk_ctrl'event and HSS0_clk_ctrl='1' then
-	 if HSS8_ena_ctrl='1' then
+   PROCESS (HSS0_clk_ctrl) BEGIN
+      if HSS0_clk_ctrl'EVENT and HSS0_clk_ctrl='1' THEN
+	 if HSS8_ena_ctrl='1' THEN
 	    (HSS_q(11), HSS_q(10), HSS_q(9), HSS_q(8)) <= HSS_d(11 DOWNTO 8);
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (HSS0_clk_ctrl) begin
-      if HSS0_clk_ctrl'event and HSS0_clk_ctrl='1' then
-	 if HSS0_ena_ctrl='1' then
+   PROCESS (HSS0_clk_ctrl) BEGIN
+      if HSS0_clk_ctrl'EVENT and HSS0_clk_ctrl='1' THEN
+	 if HSS0_ena_ctrl='1' THEN
 	    (HSS_q(7), HSS_q(6), HSS_q(5), HSS_q(4), HSS_q(3), HSS_q(2),
 		  HSS_q(1), HSS_q(0)) <= HSS_d(7 DOWNTO 0);
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (DOP_ZEI_clk) begin
-      if DOP_ZEI_clk'event and DOP_ZEI_clk='1' then
+   PROCESS (DOP_ZEI_clk) BEGIN
+      if DOP_ZEI_clk'EVENT and DOP_ZEI_clk='1' THEN
 	 DOP_ZEI_q <= DOP_ZEI_d;
-      end if;
-   end process;
+      END IF;
+   END PROCESS;
 
-   process (VBE0_clk_ctrl) begin
-      if VBE0_clk_ctrl'event and VBE0_clk_ctrl='1' then
-	 if VBE8_ena_ctrl='1' then
+   PROCESS (VBE0_clk_ctrl) BEGIN
+      if VBE0_clk_ctrl'EVENT and VBE0_clk_ctrl='1' THEN
+	 if VBE8_ena_ctrl='1' THEN
 	    (VBE_q(10), VBE_q(9), VBE_q(8)) <= VBE_d(10 DOWNTO 8);
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (VBE0_clk_ctrl) begin
-      if VBE0_clk_ctrl'event and VBE0_clk_ctrl='1' then
-	 if VBE0_ena_ctrl='1' then
+   PROCESS (VBE0_clk_ctrl) BEGIN
+      if VBE0_clk_ctrl'EVENT and VBE0_clk_ctrl='1' THEN
+	 if VBE0_ena_ctrl='1' THEN
 	    (VBE_q(7), VBE_q(6), VBE_q(5), VBE_q(4), VBE_q(3), VBE_q(2),
 		  VBE_q(1), VBE_q(0)) <= VBE_d(7 DOWNTO 0);
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (VDB0_clk_ctrl) begin
-      if VDB0_clk_ctrl'event and VDB0_clk_ctrl='1' then
-	 if VDB8_ena_ctrl='1' then
+   PROCESS (VDB0_clk_ctrl) BEGIN
+      if VDB0_clk_ctrl'EVENT and VDB0_clk_ctrl='1' THEN
+	 if VDB8_ena_ctrl='1' THEN
 	    (VDB_q(10), VDB_q(9), VDB_q(8)) <= VDB_d(10 DOWNTO 8);
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (VDB0_clk_ctrl) begin
-      if VDB0_clk_ctrl'event and VDB0_clk_ctrl='1' then
-	 if VDB0_ena_ctrl='1' then
+   PROCESS (VDB0_clk_ctrl) BEGIN
+      if VDB0_clk_ctrl'EVENT and VDB0_clk_ctrl='1' THEN
+	 if VDB0_ena_ctrl='1' THEN
 	    (VDB_q(7), VDB_q(6), VDB_q(5), VDB_q(4), VDB_q(3), VDB_q(2),
 		  VDB_q(1), VDB_q(0)) <= VDB_d(7 DOWNTO 0);
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (VDE0_clk_ctrl) begin
-      if VDE0_clk_ctrl'event and VDE0_clk_ctrl='1' then
-	 if VDE8_ena_ctrl='1' then
+   PROCESS (VDE0_clk_ctrl) BEGIN
+      if VDE0_clk_ctrl'EVENT and VDE0_clk_ctrl='1' THEN
+	 if VDE8_ena_ctrl='1' THEN
 	    (VDE_q(10), VDE_q(9), VDE_q(8)) <= VDE_d(10 DOWNTO 8);
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (VDE0_clk_ctrl) begin
-      if VDE0_clk_ctrl'event and VDE0_clk_ctrl='1' then
-	 if VDE0_ena_ctrl='1' then
+   PROCESS (VDE0_clk_ctrl) BEGIN
+      if VDE0_clk_ctrl'EVENT and VDE0_clk_ctrl='1' THEN
+	 if VDE0_ena_ctrl='1' THEN
 	    (VDE_q(7), VDE_q(6), VDE_q(5), VDE_q(4), VDE_q(3), VDE_q(2),
 		  VDE_q(1), VDE_q(0)) <= VDE_d(7 DOWNTO 0);
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (VBB0_clk_ctrl) begin
-      if VBB0_clk_ctrl'event and VBB0_clk_ctrl='1' then
-	 if VBB8_ena_ctrl='1' then
+   PROCESS (VBB0_clk_ctrl) BEGIN
+      if VBB0_clk_ctrl'EVENT and VBB0_clk_ctrl='1' THEN
+	 if VBB8_ena_ctrl='1' THEN
 	    (VBB_q(10), VBB_q(9), VBB_q(8)) <= VBB_d(10 DOWNTO 8);
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (VBB0_clk_ctrl) begin
-      if VBB0_clk_ctrl'event and VBB0_clk_ctrl='1' then
-	 if VBB0_ena_ctrl='1' then
+   PROCESS (VBB0_clk_ctrl) BEGIN
+      if VBB0_clk_ctrl'EVENT and VBB0_clk_ctrl='1' THEN
+	 if VBB0_ena_ctrl='1' THEN
 	    (VBB_q(7), VBB_q(6), VBB_q(5), VBB_q(4), VBB_q(3), VBB_q(2),
 		  VBB_q(1), VBB_q(0)) <= VBB_d(7 DOWNTO 0);
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (VSS0_clk_ctrl) begin
-      if VSS0_clk_ctrl'event and VSS0_clk_ctrl='1' then
-	 if VSS8_ena_ctrl='1' then
+   PROCESS (VSS0_clk_ctrl) BEGIN
+      if VSS0_clk_ctrl'EVENT and VSS0_clk_ctrl='1' THEN
+	 if VSS8_ena_ctrl='1' THEN
 	    (VSS_q(10), VSS_q(9), VSS_q(8)) <= VSS_d(10 DOWNTO 8);
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (VSS0_clk_ctrl) begin
-      if VSS0_clk_ctrl'event and VSS0_clk_ctrl='1' then
-	 if VSS0_ena_ctrl='1' then
+   PROCESS (VSS0_clk_ctrl) BEGIN
+      if VSS0_clk_ctrl'EVENT and VSS0_clk_ctrl='1' THEN
+	 if VSS0_ena_ctrl='1' THEN
 	    (VSS_q(7), VSS_q(6), VSS_q(5), VSS_q(4), VSS_q(3), VSS_q(2),
 		  VSS_q(1), VSS_q(0)) <= VSS_d(7 DOWNTO 0);
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (VFT0_clk_ctrl) begin
-      if VFT0_clk_ctrl'event and VFT0_clk_ctrl='1' then
-	 if VFT8_ena_ctrl='1' then
+   PROCESS (VFT0_clk_ctrl) BEGIN
+      if VFT0_clk_ctrl'EVENT and VFT0_clk_ctrl='1' THEN
+	 if VFT8_ena_ctrl='1' THEN
 	    (VFT_q(10), VFT_q(9), VFT_q(8)) <= VFT_d(10 DOWNTO 8);
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (VFT0_clk_ctrl) begin
-      if VFT0_clk_ctrl'event and VFT0_clk_ctrl='1' then
-	 if VFT0_ena_ctrl='1' then
+   PROCESS (VFT0_clk_ctrl) BEGIN
+      if VFT0_clk_ctrl'EVENT and VFT0_clk_ctrl='1' THEN
+	 if VFT0_ena_ctrl='1' THEN
 	    (VFT_q(7), VFT_q(6), VFT_q(5), VFT_q(4), VFT_q(3), VFT_q(2),
 		  VFT_q(1), VFT_q(0)) <= VFT_d(7 DOWNTO 0);
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (VCO0_clk_ctrl) begin
-      if VCO0_clk_ctrl'event and VCO0_clk_ctrl='1' then
-	 if VCO_ena(8)='1' then
+   PROCESS (VCO0_clk_ctrl) BEGIN
+      if VCO0_clk_ctrl'EVENT and VCO0_clk_ctrl='1' THEN
+	 if VCO_ena(8)='1' THEN
 	    VCO_q(8) <= VCO_d(8);
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (VCO0_clk_ctrl) begin
-      if VCO0_clk_ctrl'event and VCO0_clk_ctrl='1' then
-	 if VCO0_ena_ctrl='1' then
+   PROCESS (VCO0_clk_ctrl) BEGIN
+      if VCO0_clk_ctrl'EVENT and VCO0_clk_ctrl='1' THEN
+	 if VCO0_ena_ctrl='1' THEN
 	    (VCO_q(7), VCO_q(6), VCO_q(5), VCO_q(4), VCO_q(3), VCO_q(2),
 		  VCO_q(1), VCO_q(0)) <= VCO_d(7 DOWNTO 0);
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
-   process (VCNTRL0_clk_ctrl) begin
-      if VCNTRL0_clk_ctrl'event and VCNTRL0_clk_ctrl='1' then
-	 if VCNTRL0_ena_ctrl='1' then
+   PROCESS (VCNTRL0_clk_ctrl) BEGIN
+      if VCNTRL0_clk_ctrl'EVENT and VCNTRL0_clk_ctrl='1' THEN
+	 if VCNTRL0_ena_ctrl='1' THEN
 	    VCNTRL_q <= VCNTRL_d;
-	 end if;
-      end if;
-   end process;
+	 END IF;
+      END IF;
+   END PROCESS;
 
 -- Start of original equations
 
@@ -1268,8 +1272,7 @@ begin
 
 --  ACP CLUT --
 --  0-3FF/1024
-   ACP_CLUT_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 10) =
-	 "000000000000000000");
+   ACP_CLUT_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 10) = "000000000000000000");
    ACP_CLUT_RD <= ACP_CLUT_CS and (not nFB_OE);
    ACP_CLUT_WR <= FB_B and sizeIt(ACP_CLUT_CS,4) and sizeIt(not nFB_WR,4);
    CLUT_TA_clk <= MAIN_CLK;
diff --git a/FPGA_Quartus_13.1/firebee1.qsf b/FPGA_Quartus_13.1/firebee1.qsf
index a73de2d..b587e1e 100644
--- a/FPGA_Quartus_13.1/firebee1.qsf
+++ b/FPGA_Quartus_13.1/firebee1.qsf
@@ -39,390 +39,390 @@
 
 # Project-Wide Assignments
 # ========================
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29  SEPTEMBER 03, 2009"
-set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29  SEPTEMBER 03, 2009"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
 
 # Pin & Location Assignments
 # ==========================
-set_location_assignment PIN_G2 -to MAIN_CLK
-set_location_assignment PIN_Y3 -to FB_AD[0]
-set_location_assignment PIN_Y6 -to FB_AD[1]
-set_location_assignment PIN_AA3 -to FB_AD[2]
-set_location_assignment PIN_AB3 -to FB_AD[3]
-set_location_assignment PIN_W6 -to FB_AD[4]
-set_location_assignment PIN_V7 -to FB_AD[5]
-set_location_assignment PIN_AA4 -to FB_AD[6]
-set_location_assignment PIN_AB4 -to FB_AD[7]
-set_location_assignment PIN_AA5 -to FB_AD[8]
-set_location_assignment PIN_AB5 -to FB_AD[9]
-set_location_assignment PIN_W7 -to FB_AD[10]
-set_location_assignment PIN_Y7 -to FB_AD[11]
-set_location_assignment PIN_U9 -to FB_AD[12]
-set_location_assignment PIN_V8 -to FB_AD[13]
-set_location_assignment PIN_W8 -to FB_AD[14]
-set_location_assignment PIN_AA7 -to FB_AD[15]
-set_location_assignment PIN_AB7 -to FB_AD[16]
-set_location_assignment PIN_Y8 -to FB_AD[17]
-set_location_assignment PIN_V9 -to FB_AD[18]
-set_location_assignment PIN_V10 -to FB_AD[19]
-set_location_assignment PIN_T10 -to FB_AD[20]
-set_location_assignment PIN_U10 -to FB_AD[21]
-set_location_assignment PIN_AA8 -to FB_AD[22]
-set_location_assignment PIN_AB8 -to FB_AD[23]
-set_location_assignment PIN_T11 -to FB_AD[24]
-set_location_assignment PIN_AA9 -to FB_AD[25]
-set_location_assignment PIN_AB9 -to FB_AD[26]
-set_location_assignment PIN_U11 -to FB_AD[27]
-set_location_assignment PIN_V11 -to FB_AD[28]
-set_location_assignment PIN_W10 -to FB_AD[29]
-set_location_assignment PIN_Y10 -to FB_AD[30]
-set_location_assignment PIN_AA10 -to FB_AD[31]
-set_location_assignment PIN_R7 -to FB_ALE
-set_location_assignment PIN_N19 -to LED_FPGA_OK
-set_location_assignment PIN_AB10 -to CLK24M576
-set_location_assignment PIN_J1 -to CLKUSB
-set_location_assignment PIN_T4 -to CLK25M
-set_location_assignment PIN_U8 -to FB_SIZE0
-set_location_assignment PIN_Y4 -to FB_SIZE1
-set_location_assignment PIN_T3 -to nFB_BURST
-set_location_assignment PIN_T8 -to nFB_CS1
-set_location_assignment PIN_T9 -to nFB_CS2
-set_location_assignment PIN_V6 -to nFB_CS3
-set_location_assignment PIN_R6 -to nFB_OE
-set_location_assignment PIN_T5 -to nFB_WR
-set_location_assignment PIN_R5 -to TIN0
-set_location_assignment PIN_T21 -to nMASTER
-set_location_assignment PIN_E11 -to nDREQ1
-set_location_assignment PIN_A12 -to nDACK1
-set_location_assignment PIN_B12 -to nDACK0
-set_location_assignment PIN_T22 -to TOUT0
-set_location_assignment PIN_AB17 -to DDR_CLK
-set_location_assignment PIN_AA17 -to nDDR_CLK
-set_location_assignment PIN_AB18 -to nVCAS
-set_location_assignment PIN_T18 -to nVCS
-set_location_assignment PIN_W17 -to nVRAS
-set_location_assignment PIN_Y17 -to nVWE
-set_location_assignment PIN_W20 -to VA[0]
-set_location_assignment PIN_W22 -to VA[1]
-set_location_assignment PIN_W21 -to VA[2]
-set_location_assignment PIN_Y22 -to VA[3]
-set_location_assignment PIN_AA22 -to VA[4]
-set_location_assignment PIN_Y21 -to VA[5]
-set_location_assignment PIN_AA21 -to VA[6]
-set_location_assignment PIN_AA20 -to VA[7]
-set_location_assignment PIN_AB20 -to VA[8]
-set_location_assignment PIN_AB19 -to VA[9]
-set_location_assignment PIN_V21 -to VA[10]
-set_location_assignment PIN_U19 -to VA[11]
-set_location_assignment PIN_AA18 -to VA[12]
-set_location_assignment PIN_U15 -to VCKE
-set_location_assignment PIN_M22 -to VD[0]
-set_location_assignment PIN_M21 -to VD[1]
-set_location_assignment PIN_P22 -to VD[2]
-set_location_assignment PIN_R20 -to VD[3]
-set_location_assignment PIN_P21 -to VD[4]
-set_location_assignment PIN_R17 -to VD[5]
-set_location_assignment PIN_R19 -to VD[6]
-set_location_assignment PIN_U21 -to VD[7]
-set_location_assignment PIN_V22 -to VD[8]
-set_location_assignment PIN_R18 -to VD[9]
-set_location_assignment PIN_P17 -to VD[10]
-set_location_assignment PIN_R21 -to VD[11]
-set_location_assignment PIN_N17 -to VD[12]
-set_location_assignment PIN_P20 -to VD[13]
-set_location_assignment PIN_R22 -to VD[14]
-set_location_assignment PIN_N20 -to VD[15]
-set_location_assignment PIN_T12 -to VD[16]
-set_location_assignment PIN_Y13 -to VD[17]
-set_location_assignment PIN_AA13 -to VD[18]
-set_location_assignment PIN_V14 -to VD[19]
-set_location_assignment PIN_U13 -to VD[20]
-set_location_assignment PIN_V15 -to VD[21]
-set_location_assignment PIN_W14 -to VD[22]
-set_location_assignment PIN_AB16 -to VD[23]
-set_location_assignment PIN_AB15 -to VD[24]
-set_location_assignment PIN_AA14 -to VD[25]
-set_location_assignment PIN_AB14 -to VD[26]
-set_location_assignment PIN_V13 -to VD[27]
-set_location_assignment PIN_W13 -to VD[28]
-set_location_assignment PIN_AB13 -to VD[29]
-set_location_assignment PIN_V12 -to VD[30]
-set_location_assignment PIN_U12 -to VD[31]
-set_location_assignment PIN_AA16 -to VDM[0]
-set_location_assignment PIN_V16 -to VDM[1]
-set_location_assignment PIN_U20 -to VDM[2]
-set_location_assignment PIN_T17 -to VDM[3]
-set_location_assignment PIN_AA15 -to VDQS[0]
-set_location_assignment PIN_W15 -to VDQS[1]
-set_location_assignment PIN_U22 -to VDQS[2]
-set_location_assignment PIN_T16 -to VDQS[3]
-set_location_assignment PIN_V1 -to nPD_VGA
-set_location_assignment PIN_G18 -to VB[0]
-set_location_assignment PIN_H17 -to VB[1]
-set_location_assignment PIN_C22 -to VB[2]
-set_location_assignment PIN_C21 -to VB[3]
-set_location_assignment PIN_B22 -to VB[4]
-set_location_assignment PIN_B21 -to VB[5]
-set_location_assignment PIN_C20 -to VB[6]
-set_location_assignment PIN_D20 -to VB[7]
-set_location_assignment PIN_H19 -to VG[0]
-set_location_assignment PIN_E22 -to VG[1]
-set_location_assignment PIN_E21 -to VG[2]
-set_location_assignment PIN_H18 -to VG[3]
-set_location_assignment PIN_J17 -to VG[4]
-set_location_assignment PIN_H16 -to VG[5]
-set_location_assignment PIN_D22 -to VG[6]
-set_location_assignment PIN_D21 -to VG[7]
-set_location_assignment PIN_J22 -to VR[0]
-set_location_assignment PIN_J21 -to VR[1]
-set_location_assignment PIN_H22 -to VR[2]
-set_location_assignment PIN_H21 -to VR[3]
-set_location_assignment PIN_K17 -to VR[4]
-set_location_assignment PIN_K18 -to VR[5]
-set_location_assignment PIN_J18 -to VR[6]
-set_location_assignment PIN_F22 -to VR[7]
-set_location_assignment PIN_M6 -to ACSI_A1
-set_location_assignment PIN_B1 -to ACSI_D[0]
-set_location_assignment PIN_G5 -to ACSI_D[1]
-set_location_assignment PIN_E3 -to ACSI_D[2]
-set_location_assignment PIN_C2 -to ACSI_D[3]
-set_location_assignment PIN_C1 -to ACSI_D[4]
-set_location_assignment PIN_D2 -to ACSI_D[5]
-set_location_assignment PIN_H7 -to ACSI_D[6]
-set_location_assignment PIN_H6 -to ACSI_D[7]
-set_location_assignment PIN_L6 -to ACSI_DIR
-set_location_assignment PIN_N1 -to AMKB_TX
-set_location_assignment PIN_F15 -to DSA_D
-set_location_assignment PIN_D15 -to DTR
-set_location_assignment PIN_A11 -to DVI_INT
-set_location_assignment PIN_G21 -to E0_INT
-set_location_assignment PIN_M5 -to IDE_RES
-set_location_assignment PIN_A8 -to IO[0]
-set_location_assignment PIN_A7 -to IO[1]
-set_location_assignment PIN_B7 -to IO[2]
-set_location_assignment PIN_A6 -to IO[3]
-set_location_assignment PIN_B6 -to IO[4]
-set_location_assignment PIN_E9 -to IO[5]
-set_location_assignment PIN_C8 -to IO[6]
-set_location_assignment PIN_C7 -to IO[7]
-set_location_assignment PIN_G10 -to IO[8]
-set_location_assignment PIN_A15 -to IO[9]
-set_location_assignment PIN_B15 -to IO[10]
-set_location_assignment PIN_C13 -to IO[11]
-set_location_assignment PIN_D13 -to IO[12]
-set_location_assignment PIN_E13 -to IO[13]
-set_location_assignment PIN_A14 -to IO[14]
-set_location_assignment PIN_B14 -to IO[15]
-set_location_assignment PIN_A13 -to IO[16]
-set_location_assignment PIN_B13 -to IO[17]
-set_location_assignment PIN_F7 -to LP_D[0]
-set_location_assignment PIN_C4 -to LP_D[1]
-set_location_assignment PIN_C3 -to LP_D[2]
-set_location_assignment PIN_E7 -to LP_D[3]
-set_location_assignment PIN_D6 -to LP_D[4]
-set_location_assignment PIN_B3 -to LP_D[5]
-set_location_assignment PIN_A3 -to LP_D[6]
-set_location_assignment PIN_G8 -to LP_D[7]
-set_location_assignment PIN_E6 -to LP_STR
-set_location_assignment PIN_H5 -to MIDI_OLR
-set_location_assignment PIN_B2 -to MIDI_TLR
-set_location_assignment PIN_M4 -to nACSI_ACK
-set_location_assignment PIN_M2 -to nACSI_CS
-set_location_assignment PIN_M1 -to nACSI_RESET
-set_location_assignment PIN_W2 -to nCF_CS0
-set_location_assignment PIN_W1 -to nCF_CS1
-set_location_assignment PIN_T7 -to nFB_TA
-set_location_assignment PIN_R2 -to nIDE_CS0
-set_location_assignment PIN_R1 -to nIDE_CS1
-set_location_assignment PIN_P1 -to nIDE_RD
-set_location_assignment PIN_P2 -to nIDE_WR
-set_location_assignment PIN_F21 -to nIRQ[2]
-set_location_assignment PIN_H20 -to nIRQ[3]
-set_location_assignment PIN_F20 -to nIRQ[4]
-set_location_assignment PIN_P5 -to nIRQ[5]
-set_location_assignment PIN_P7 -to nIRQ[6]
-set_location_assignment PIN_N7 -to nIRQ[7]
-set_location_assignment PIN_AA1 -to nPCI_INTA
-set_location_assignment PIN_V4 -to nPCI_INTB
-set_location_assignment PIN_V3 -to nPCI_INTC
-set_location_assignment PIN_P6 -to nPCI_INTD
-set_location_assignment PIN_P3 -to nROM3
-set_location_assignment PIN_U2 -to nROM4
-set_location_assignment PIN_N5 -to nRP_LDS
-set_location_assignment PIN_P4 -to nRP_UDS
-set_location_assignment PIN_N2 -to nSCSI_ACK
-set_location_assignment PIN_M3 -to nSCSI_ATN
-set_location_assignment PIN_N8 -to nSCSI_BUSY
-set_location_assignment PIN_N6 -to nSCSI_RST
-set_location_assignment PIN_M8 -to nSCSI_SEL
-set_location_assignment PIN_B20 -to nSDSEL
-set_location_assignment PIN_B4 -to nSRBHE
-set_location_assignment PIN_A4 -to nSRBLE
-set_location_assignment PIN_B8 -to nSRCS
-set_location_assignment PIN_F11 -to nSROE
-set_location_assignment PIN_F8 -to nSRWE
-set_location_assignment PIN_G14 -to nWR
-set_location_assignment PIN_D17 -to nWR_GATE
-set_location_assignment PIN_AA2 -to PIC_INT
-set_location_assignment PIN_B18 -to RTS
-set_location_assignment PIN_J6 -to SCSI_D[0]
-set_location_assignment PIN_E1 -to SCSI_D[1]
-set_location_assignment PIN_F2 -to SCSI_D[2]
-set_location_assignment PIN_F1 -to SCSI_D[3]
-set_location_assignment PIN_G4 -to SCSI_D[4]
-set_location_assignment PIN_G3 -to SCSI_D[5]
-set_location_assignment PIN_L8 -to SCSI_D[6]
-set_location_assignment PIN_K8 -to SCSI_D[7]
-set_location_assignment PIN_J7 -to SCSI_DIR
-set_location_assignment PIN_M7 -to SCSI_PAR
-set_location_assignment PIN_F13 -to SD_CD_DATA3
-set_location_assignment PIN_C15 -to SD_CLK
-set_location_assignment PIN_E14 -to SD_CMD_D1
-set_location_assignment PIN_B5 -to SRD[0]
-set_location_assignment PIN_A5 -to SRD[1]
-set_location_assignment PIN_C6 -to SRD[2]
-set_location_assignment PIN_G11 -to SRD[3]
-set_location_assignment PIN_C10 -to SRD[4]
-set_location_assignment PIN_F9 -to SRD[5]
-set_location_assignment PIN_E10 -to SRD[6]
-set_location_assignment PIN_H11 -to SRD[7]
-set_location_assignment PIN_B9 -to SRD[8]
-set_location_assignment PIN_A10 -to SRD[9]
-set_location_assignment PIN_A9 -to SRD[10]
-set_location_assignment PIN_B10 -to SRD[11]
-set_location_assignment PIN_D10 -to SRD[12]
-set_location_assignment PIN_F10 -to SRD[13]
-set_location_assignment PIN_G9 -to SRD[14]
-set_location_assignment PIN_H10 -to SRD[15]
-set_location_assignment PIN_A18 -to TxD
-set_location_assignment PIN_A17 -to YM_QA
-set_location_assignment PIN_G13 -to YM_QB
-set_location_assignment PIN_E15 -to YM_QC
-set_location_assignment PIN_T1 -to WP_CF_CARD
-set_location_assignment PIN_C19 -to TRACK00
-set_location_assignment PIN_M19 -to SD_WP
-set_location_assignment PIN_B17 -to SD_DATA2
-set_location_assignment PIN_A16 -to SD_DATA1
-set_location_assignment PIN_B16 -to SD_DATA0
-set_location_assignment PIN_M20 -to SD_CARD_DEDECT
-set_location_assignment PIN_H15 -to RxD
-set_location_assignment PIN_B19 -to RI
-set_location_assignment PIN_L7 -to PIC_AMKB_RX
-set_location_assignment PIN_D19 -to nWP
-set_location_assignment PIN_H2 -to nSCSI_MSG
-set_location_assignment PIN_J3 -to nSCSI_I_O
-set_location_assignment PIN_U1 -to nSCSI_DRQ
-set_location_assignment PIN_H1 -to nSCSI_C_D
-set_location_assignment PIN_A20 -to nRD_DATA
-set_location_assignment PIN_C17 -to nDCHG
-set_location_assignment PIN_J4 -to nACSI_INT
-set_location_assignment PIN_K7 -to nACSI_DRQ
-set_location_assignment PIN_G7 -to LP_BUSY
-set_location_assignment PIN_Y1 -to IDE_RDY
-set_location_assignment PIN_G22 -to IDE_INT
-set_location_assignment PIN_F16 -to HD_DD
-set_location_assignment PIN_A19 -to DCD
-set_location_assignment PIN_H14 -to CTS
-set_location_assignment PIN_Y2 -to AMKB_RX
-set_location_assignment PIN_E16 -to nINDEX
-set_location_assignment PIN_W19 -to BA[0]
-set_location_assignment PIN_AA19 -to BA[1]
-set_location_assignment PIN_K21 -to HSYNC_PAD
-set_location_assignment PIN_K19 -to VSYNC_PAD
-set_location_assignment PIN_G17 -to nBLANK_PAD
-set_location_assignment PIN_F19 -to PIXEL_CLK_PAD
-set_location_assignment PIN_F17 -to nSYNC
-set_location_assignment PIN_G15 -to nSTEP_DIR
-set_location_assignment PIN_F14 -to nSTEP
-set_location_assignment PIN_G16 -to nMOT_ON
+set_location_assignment PIN_G2 -to MAIN_CLK
+set_location_assignment PIN_Y3 -to FB_AD[0]
+set_location_assignment PIN_Y6 -to FB_AD[1]
+set_location_assignment PIN_AA3 -to FB_AD[2]
+set_location_assignment PIN_AB3 -to FB_AD[3]
+set_location_assignment PIN_W6 -to FB_AD[4]
+set_location_assignment PIN_V7 -to FB_AD[5]
+set_location_assignment PIN_AA4 -to FB_AD[6]
+set_location_assignment PIN_AB4 -to FB_AD[7]
+set_location_assignment PIN_AA5 -to FB_AD[8]
+set_location_assignment PIN_AB5 -to FB_AD[9]
+set_location_assignment PIN_W7 -to FB_AD[10]
+set_location_assignment PIN_Y7 -to FB_AD[11]
+set_location_assignment PIN_U9 -to FB_AD[12]
+set_location_assignment PIN_V8 -to FB_AD[13]
+set_location_assignment PIN_W8 -to FB_AD[14]
+set_location_assignment PIN_AA7 -to FB_AD[15]
+set_location_assignment PIN_AB7 -to FB_AD[16]
+set_location_assignment PIN_Y8 -to FB_AD[17]
+set_location_assignment PIN_V9 -to FB_AD[18]
+set_location_assignment PIN_V10 -to FB_AD[19]
+set_location_assignment PIN_T10 -to FB_AD[20]
+set_location_assignment PIN_U10 -to FB_AD[21]
+set_location_assignment PIN_AA8 -to FB_AD[22]
+set_location_assignment PIN_AB8 -to FB_AD[23]
+set_location_assignment PIN_T11 -to FB_AD[24]
+set_location_assignment PIN_AA9 -to FB_AD[25]
+set_location_assignment PIN_AB9 -to FB_AD[26]
+set_location_assignment PIN_U11 -to FB_AD[27]
+set_location_assignment PIN_V11 -to FB_AD[28]
+set_location_assignment PIN_W10 -to FB_AD[29]
+set_location_assignment PIN_Y10 -to FB_AD[30]
+set_location_assignment PIN_AA10 -to FB_AD[31]
+set_location_assignment PIN_R7 -to FB_ALE
+set_location_assignment PIN_N19 -to LED_FPGA_OK
+set_location_assignment PIN_AB10 -to CLK24M576
+set_location_assignment PIN_J1 -to CLKUSB
+set_location_assignment PIN_T4 -to CLK25M
+set_location_assignment PIN_U8 -to FB_SIZE0
+set_location_assignment PIN_Y4 -to FB_SIZE1
+set_location_assignment PIN_T3 -to nFB_BURST
+set_location_assignment PIN_T8 -to nFB_CS1
+set_location_assignment PIN_T9 -to nFB_CS2
+set_location_assignment PIN_V6 -to nFB_CS3
+set_location_assignment PIN_R6 -to nFB_OE
+set_location_assignment PIN_T5 -to nFB_WR
+set_location_assignment PIN_R5 -to TIN0
+set_location_assignment PIN_T21 -to nMASTER
+set_location_assignment PIN_E11 -to nDREQ1
+set_location_assignment PIN_A12 -to nDACK1
+set_location_assignment PIN_B12 -to nDACK0
+set_location_assignment PIN_T22 -to TOUT0
+set_location_assignment PIN_AB17 -to DDR_CLK
+set_location_assignment PIN_AA17 -to nDDR_CLK
+set_location_assignment PIN_AB18 -to nVCAS
+set_location_assignment PIN_T18 -to nVCS
+set_location_assignment PIN_W17 -to nVRAS
+set_location_assignment PIN_Y17 -to nVWE
+set_location_assignment PIN_W20 -to VA[0]
+set_location_assignment PIN_W22 -to VA[1]
+set_location_assignment PIN_W21 -to VA[2]
+set_location_assignment PIN_Y22 -to VA[3]
+set_location_assignment PIN_AA22 -to VA[4]
+set_location_assignment PIN_Y21 -to VA[5]
+set_location_assignment PIN_AA21 -to VA[6]
+set_location_assignment PIN_AA20 -to VA[7]
+set_location_assignment PIN_AB20 -to VA[8]
+set_location_assignment PIN_AB19 -to VA[9]
+set_location_assignment PIN_V21 -to VA[10]
+set_location_assignment PIN_U19 -to VA[11]
+set_location_assignment PIN_AA18 -to VA[12]
+set_location_assignment PIN_U15 -to VCKE
+set_location_assignment PIN_M22 -to VD[0]
+set_location_assignment PIN_M21 -to VD[1]
+set_location_assignment PIN_P22 -to VD[2]
+set_location_assignment PIN_R20 -to VD[3]
+set_location_assignment PIN_P21 -to VD[4]
+set_location_assignment PIN_R17 -to VD[5]
+set_location_assignment PIN_R19 -to VD[6]
+set_location_assignment PIN_U21 -to VD[7]
+set_location_assignment PIN_V22 -to VD[8]
+set_location_assignment PIN_R18 -to VD[9]
+set_location_assignment PIN_P17 -to VD[10]
+set_location_assignment PIN_R21 -to VD[11]
+set_location_assignment PIN_N17 -to VD[12]
+set_location_assignment PIN_P20 -to VD[13]
+set_location_assignment PIN_R22 -to VD[14]
+set_location_assignment PIN_N20 -to VD[15]
+set_location_assignment PIN_T12 -to VD[16]
+set_location_assignment PIN_Y13 -to VD[17]
+set_location_assignment PIN_AA13 -to VD[18]
+set_location_assignment PIN_V14 -to VD[19]
+set_location_assignment PIN_U13 -to VD[20]
+set_location_assignment PIN_V15 -to VD[21]
+set_location_assignment PIN_W14 -to VD[22]
+set_location_assignment PIN_AB16 -to VD[23]
+set_location_assignment PIN_AB15 -to VD[24]
+set_location_assignment PIN_AA14 -to VD[25]
+set_location_assignment PIN_AB14 -to VD[26]
+set_location_assignment PIN_V13 -to VD[27]
+set_location_assignment PIN_W13 -to VD[28]
+set_location_assignment PIN_AB13 -to VD[29]
+set_location_assignment PIN_V12 -to VD[30]
+set_location_assignment PIN_U12 -to VD[31]
+set_location_assignment PIN_AA16 -to VDM[0]
+set_location_assignment PIN_V16 -to VDM[1]
+set_location_assignment PIN_U20 -to VDM[2]
+set_location_assignment PIN_T17 -to VDM[3]
+set_location_assignment PIN_AA15 -to VDQS[0]
+set_location_assignment PIN_W15 -to VDQS[1]
+set_location_assignment PIN_U22 -to VDQS[2]
+set_location_assignment PIN_T16 -to VDQS[3]
+set_location_assignment PIN_V1 -to nPD_VGA
+set_location_assignment PIN_G18 -to VB[0]
+set_location_assignment PIN_H17 -to VB[1]
+set_location_assignment PIN_C22 -to VB[2]
+set_location_assignment PIN_C21 -to VB[3]
+set_location_assignment PIN_B22 -to VB[4]
+set_location_assignment PIN_B21 -to VB[5]
+set_location_assignment PIN_C20 -to VB[6]
+set_location_assignment PIN_D20 -to VB[7]
+set_location_assignment PIN_H19 -to VG[0]
+set_location_assignment PIN_E22 -to VG[1]
+set_location_assignment PIN_E21 -to VG[2]
+set_location_assignment PIN_H18 -to VG[3]
+set_location_assignment PIN_J17 -to VG[4]
+set_location_assignment PIN_H16 -to VG[5]
+set_location_assignment PIN_D22 -to VG[6]
+set_location_assignment PIN_D21 -to VG[7]
+set_location_assignment PIN_J22 -to VR[0]
+set_location_assignment PIN_J21 -to VR[1]
+set_location_assignment PIN_H22 -to VR[2]
+set_location_assignment PIN_H21 -to VR[3]
+set_location_assignment PIN_K17 -to VR[4]
+set_location_assignment PIN_K18 -to VR[5]
+set_location_assignment PIN_J18 -to VR[6]
+set_location_assignment PIN_F22 -to VR[7]
+set_location_assignment PIN_M6 -to ACSI_A1
+set_location_assignment PIN_B1 -to ACSI_D[0]
+set_location_assignment PIN_G5 -to ACSI_D[1]
+set_location_assignment PIN_E3 -to ACSI_D[2]
+set_location_assignment PIN_C2 -to ACSI_D[3]
+set_location_assignment PIN_C1 -to ACSI_D[4]
+set_location_assignment PIN_D2 -to ACSI_D[5]
+set_location_assignment PIN_H7 -to ACSI_D[6]
+set_location_assignment PIN_H6 -to ACSI_D[7]
+set_location_assignment PIN_L6 -to ACSI_DIR
+set_location_assignment PIN_N1 -to AMKB_TX
+set_location_assignment PIN_F15 -to DSA_D
+set_location_assignment PIN_D15 -to DTR
+set_location_assignment PIN_A11 -to DVI_INT
+set_location_assignment PIN_G21 -to E0_INT
+set_location_assignment PIN_M5 -to IDE_RES
+set_location_assignment PIN_A8 -to IO[0]
+set_location_assignment PIN_A7 -to IO[1]
+set_location_assignment PIN_B7 -to IO[2]
+set_location_assignment PIN_A6 -to IO[3]
+set_location_assignment PIN_B6 -to IO[4]
+set_location_assignment PIN_E9 -to IO[5]
+set_location_assignment PIN_C8 -to IO[6]
+set_location_assignment PIN_C7 -to IO[7]
+set_location_assignment PIN_G10 -to IO[8]
+set_location_assignment PIN_A15 -to IO[9]
+set_location_assignment PIN_B15 -to IO[10]
+set_location_assignment PIN_C13 -to IO[11]
+set_location_assignment PIN_D13 -to IO[12]
+set_location_assignment PIN_E13 -to IO[13]
+set_location_assignment PIN_A14 -to IO[14]
+set_location_assignment PIN_B14 -to IO[15]
+set_location_assignment PIN_A13 -to IO[16]
+set_location_assignment PIN_B13 -to IO[17]
+set_location_assignment PIN_F7 -to LP_D[0]
+set_location_assignment PIN_C4 -to LP_D[1]
+set_location_assignment PIN_C3 -to LP_D[2]
+set_location_assignment PIN_E7 -to LP_D[3]
+set_location_assignment PIN_D6 -to LP_D[4]
+set_location_assignment PIN_B3 -to LP_D[5]
+set_location_assignment PIN_A3 -to LP_D[6]
+set_location_assignment PIN_G8 -to LP_D[7]
+set_location_assignment PIN_E6 -to LP_STR
+set_location_assignment PIN_H5 -to MIDI_OLR
+set_location_assignment PIN_B2 -to MIDI_TLR
+set_location_assignment PIN_M4 -to nACSI_ACK
+set_location_assignment PIN_M2 -to nACSI_CS
+set_location_assignment PIN_M1 -to nACSI_RESET
+set_location_assignment PIN_W2 -to nCF_CS0
+set_location_assignment PIN_W1 -to nCF_CS1
+set_location_assignment PIN_T7 -to nFB_TA
+set_location_assignment PIN_R2 -to nIDE_CS0
+set_location_assignment PIN_R1 -to nIDE_CS1
+set_location_assignment PIN_P1 -to nIDE_RD
+set_location_assignment PIN_P2 -to nIDE_WR
+set_location_assignment PIN_F21 -to nIRQ[2]
+set_location_assignment PIN_H20 -to nIRQ[3]
+set_location_assignment PIN_F20 -to nIRQ[4]
+set_location_assignment PIN_P5 -to nIRQ[5]
+set_location_assignment PIN_P7 -to nIRQ[6]
+set_location_assignment PIN_N7 -to nIRQ[7]
+set_location_assignment PIN_AA1 -to nPCI_INTA
+set_location_assignment PIN_V4 -to nPCI_INTB
+set_location_assignment PIN_V3 -to nPCI_INTC
+set_location_assignment PIN_P6 -to nPCI_INTD
+set_location_assignment PIN_P3 -to nROM3
+set_location_assignment PIN_U2 -to nROM4
+set_location_assignment PIN_N5 -to nRP_LDS
+set_location_assignment PIN_P4 -to nRP_UDS
+set_location_assignment PIN_N2 -to nSCSI_ACK
+set_location_assignment PIN_M3 -to nSCSI_ATN
+set_location_assignment PIN_N8 -to nSCSI_BUSY
+set_location_assignment PIN_N6 -to nSCSI_RST
+set_location_assignment PIN_M8 -to nSCSI_SEL
+set_location_assignment PIN_B20 -to nSDSEL
+set_location_assignment PIN_B4 -to nSRBHE
+set_location_assignment PIN_A4 -to nSRBLE
+set_location_assignment PIN_B8 -to nSRCS
+set_location_assignment PIN_F11 -to nSROE
+set_location_assignment PIN_F8 -to nSRWE
+set_location_assignment PIN_G14 -to nWR
+set_location_assignment PIN_D17 -to nWR_GATE
+set_location_assignment PIN_AA2 -to PIC_INT
+set_location_assignment PIN_B18 -to RTS
+set_location_assignment PIN_J6 -to SCSI_D[0]
+set_location_assignment PIN_E1 -to SCSI_D[1]
+set_location_assignment PIN_F2 -to SCSI_D[2]
+set_location_assignment PIN_F1 -to SCSI_D[3]
+set_location_assignment PIN_G4 -to SCSI_D[4]
+set_location_assignment PIN_G3 -to SCSI_D[5]
+set_location_assignment PIN_L8 -to SCSI_D[6]
+set_location_assignment PIN_K8 -to SCSI_D[7]
+set_location_assignment PIN_J7 -to SCSI_DIR
+set_location_assignment PIN_M7 -to SCSI_PAR
+set_location_assignment PIN_F13 -to SD_CD_DATA3
+set_location_assignment PIN_C15 -to SD_CLK
+set_location_assignment PIN_E14 -to SD_CMD_D1
+set_location_assignment PIN_B5 -to SRD[0]
+set_location_assignment PIN_A5 -to SRD[1]
+set_location_assignment PIN_C6 -to SRD[2]
+set_location_assignment PIN_G11 -to SRD[3]
+set_location_assignment PIN_C10 -to SRD[4]
+set_location_assignment PIN_F9 -to SRD[5]
+set_location_assignment PIN_E10 -to SRD[6]
+set_location_assignment PIN_H11 -to SRD[7]
+set_location_assignment PIN_B9 -to SRD[8]
+set_location_assignment PIN_A10 -to SRD[9]
+set_location_assignment PIN_A9 -to SRD[10]
+set_location_assignment PIN_B10 -to SRD[11]
+set_location_assignment PIN_D10 -to SRD[12]
+set_location_assignment PIN_F10 -to SRD[13]
+set_location_assignment PIN_G9 -to SRD[14]
+set_location_assignment PIN_H10 -to SRD[15]
+set_location_assignment PIN_A18 -to TxD
+set_location_assignment PIN_A17 -to YM_QA
+set_location_assignment PIN_G13 -to YM_QB
+set_location_assignment PIN_E15 -to YM_QC
+set_location_assignment PIN_T1 -to WP_CF_CARD
+set_location_assignment PIN_C19 -to TRACK00
+set_location_assignment PIN_M19 -to SD_WP
+set_location_assignment PIN_B17 -to SD_DATA2
+set_location_assignment PIN_A16 -to SD_DATA1
+set_location_assignment PIN_B16 -to SD_DATA0
+set_location_assignment PIN_M20 -to SD_CARD_DEDECT
+set_location_assignment PIN_H15 -to RxD
+set_location_assignment PIN_B19 -to RI
+set_location_assignment PIN_L7 -to PIC_AMKB_RX
+set_location_assignment PIN_D19 -to nWP
+set_location_assignment PIN_H2 -to nSCSI_MSG
+set_location_assignment PIN_J3 -to nSCSI_I_O
+set_location_assignment PIN_U1 -to nSCSI_DRQ
+set_location_assignment PIN_H1 -to nSCSI_C_D
+set_location_assignment PIN_A20 -to nRD_DATA
+set_location_assignment PIN_C17 -to nDCHG
+set_location_assignment PIN_J4 -to nACSI_INT
+set_location_assignment PIN_K7 -to nACSI_DRQ
+set_location_assignment PIN_G7 -to LP_BUSY
+set_location_assignment PIN_Y1 -to IDE_RDY
+set_location_assignment PIN_G22 -to IDE_INT
+set_location_assignment PIN_F16 -to HD_DD
+set_location_assignment PIN_A19 -to DCD
+set_location_assignment PIN_H14 -to CTS
+set_location_assignment PIN_Y2 -to AMKB_RX
+set_location_assignment PIN_E16 -to nINDEX
+set_location_assignment PIN_W19 -to BA[0]
+set_location_assignment PIN_AA19 -to BA[1]
+set_location_assignment PIN_K21 -to HSYNC_PAD
+set_location_assignment PIN_K19 -to VSYNC_PAD
+set_location_assignment PIN_G17 -to nBLANK_PAD
+set_location_assignment PIN_F19 -to PIXEL_CLK_PAD
+set_location_assignment PIN_F17 -to nSYNC
+set_location_assignment PIN_G15 -to nSTEP_DIR
+set_location_assignment PIN_F14 -to nSTEP
+set_location_assignment PIN_G16 -to nMOT_ON
 
 # Classic Timing Assignments
 # ==========================
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
-set_global_assignment -name TPD_REQUIREMENT "1 ns"
-set_global_assignment -name TSU_REQUIREMENT "1 ns"
-set_global_assignment -name TCO_REQUIREMENT "1 ns"
-set_global_assignment -name TH_REQUIREMENT "1 ns"
-set_global_assignment -name FMAX_REQUIREMENT "30 ns"
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
+set_global_assignment -name TPD_REQUIREMENT "1 ns"
+set_global_assignment -name TSU_REQUIREMENT "1 ns"
+set_global_assignment -name TCO_REQUIREMENT "1 ns"
+set_global_assignment -name TH_REQUIREMENT "1 ns"
+set_global_assignment -name FMAX_REQUIREMENT "30 ns"
 
 # Analysis & Synthesis Assignments
 # ================================
-set_global_assignment -name FAMILY CycloneIII
-set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
-set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
-set_global_assignment -name SAFE_STATE_MACHINE OFF
-set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT"
+set_global_assignment -name FAMILY CycloneIII
+set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name SAFE_STATE_MACHINE OFF
+set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT"
 
 # Fitter Assignments
 # ==================
-set_global_assignment -name DEVICE EP3C40F484C6
-set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON
-set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON
-set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
-set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
-set_global_assignment -name FITTER_EFFORT "AUTO FIT"
-set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
-set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
-set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
-set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
-set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK
-set_instance_assignment -name IO_STANDARD "2.5 V" -to VA
-set_instance_assignment -name IO_STANDARD "2.5 V" -to VD
-set_instance_assignment -name IO_STANDARD "2.5 V" -to VDM
-set_instance_assignment -name IO_STANDARD "2.5 V" -to VDQS
-set_instance_assignment -name IO_STANDARD "2.5 V" -to nVWE
-set_instance_assignment -name IO_STANDARD "2.5 V" -to nVRAS
-set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCS
-set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCAS
-set_instance_assignment -name IO_STANDARD "2.5 V" -to nDDR_CLK
-set_instance_assignment -name IO_STANDARD "2.5 V" -to VCKE
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_FPGA_OK
-set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "0 ns"
-set_instance_assignment -name IO_STANDARD "2.5 V" -to BA
-set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC_PAD
-set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PIXEL_CLK_PAD
-set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VB
-set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VG
-set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VR
-set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC_PAD
-set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to nBLANK_PAD
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSYNC
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[2]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[3]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX
+set_global_assignment -name DEVICE EP3C40F484C6
+set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON
+set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name FITTER_EFFORT "AUTO FIT"
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
+set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK
+set_instance_assignment -name IO_STANDARD "2.5 V" -to VA
+set_instance_assignment -name IO_STANDARD "2.5 V" -to VD
+set_instance_assignment -name IO_STANDARD "2.5 V" -to VDM
+set_instance_assignment -name IO_STANDARD "2.5 V" -to VDQS
+set_instance_assignment -name IO_STANDARD "2.5 V" -to nVWE
+set_instance_assignment -name IO_STANDARD "2.5 V" -to nVRAS
+set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCS
+set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCAS
+set_instance_assignment -name IO_STANDARD "2.5 V" -to nDDR_CLK
+set_instance_assignment -name IO_STANDARD "2.5 V" -to VCKE
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_FPGA_OK
+set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "0 ns"
+set_instance_assignment -name IO_STANDARD "2.5 V" -to BA
+set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC_PAD
+set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PIXEL_CLK_PAD
+set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VB
+set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VG
+set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VR
+set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC_PAD
+set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to nBLANK_PAD
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSYNC
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[2]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[3]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX
 
 # Assembler Assignments
 # =====================
-set_global_assignment -name GENERATE_TTF_FILE OFF
-set_global_assignment -name GENERATE_RBF_FILE ON
-set_global_assignment -name GENERATE_HEX_FILE OFF
-set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0XE0700000
+set_global_assignment -name GENERATE_TTF_FILE OFF
+set_global_assignment -name GENERATE_RBF_FILE ON
+set_global_assignment -name GENERATE_HEX_FILE OFF
+set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0XE0700000
 
 # Simulator Assignments
 # =====================
-set_global_assignment -name END_TIME "2 us"
-set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF
-set_global_assignment -name SETUP_HOLD_DETECTION OFF
-set_global_assignment -name GLITCH_DETECTION OFF
-set_global_assignment -name CHECK_OUTPUTS OFF
-set_global_assignment -name SIMULATION_MODE TIMING
-set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE firebee1.vwf
+set_global_assignment -name END_TIME "2 us"
+set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF
+set_global_assignment -name SETUP_HOLD_DETECTION OFF
+set_global_assignment -name GLITCH_DETECTION OFF
+set_global_assignment -name CHECK_OUTPUTS OFF
+set_global_assignment -name SIMULATION_MODE TIMING
+set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE firebee1.vwf
 
 # start EDA_TOOL_SETTINGS(eda_blast_fpga)
 # ---------------------------------------
 
 	# Analysis & Synthesis Assignments
 	# ================================
-set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
 
 # end EDA_TOOL_SETTINGS(eda_blast_fpga)
 # -------------------------------------
@@ -432,7 +432,7 @@ set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id e
 
 	# Classic Timing Assignments
 	# ==========================
-set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast
+set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast
 
 # end CLOCK(fast)
 # ---------------
@@ -442,21 +442,21 @@ set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast
 
 	# Assignment Group Assignments
 	# ============================
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[0] -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[1] -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[2] -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[3] -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK" -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[0]" -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[1]" -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[2]" -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[3]" -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[0] -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[1] -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[2] -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[3] -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK" -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[0]" -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[1]" -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[2]" -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[3]" -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -section_id fast
 
 # end ASSIGNMENT_GROUP(fast)
 # --------------------------
@@ -466,76 +466,76 @@ set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_
 
 	# Classic Timing Assignments
 	# ==========================
-set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK
-set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[0]
-set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[1]
-set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[2]
-set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[3]
-set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK"
-set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[0]"
-set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[1]"
-set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[2]"
-set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[3]"
-set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK"
-set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]"
-set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]"
-set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]"
-set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]"
-set_instance_assignment -name INPUT_MAX_DELAY "4 ns" -from * -to FB_ALE
-set_instance_assignment -name MAX_DELAY "5 ns" -from VD -to FB_AD
-set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to VA
-set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to nVRAS
-set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA
+set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK
+set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[0]
+set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[1]
+set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[2]
+set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[3]
+set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK"
+set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[0]"
+set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[1]"
+set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[2]"
+set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[3]"
+set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK"
+set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]"
+set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]"
+set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]"
+set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]"
+set_instance_assignment -name INPUT_MAX_DELAY "4 ns" -from * -to FB_ALE
+set_instance_assignment -name MAX_DELAY "5 ns" -from VD -to FB_AD
+set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to VA
+set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to nVRAS
+set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA
 
 	# Fitter Assignments
 	# ==================
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK
-set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE
-set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to FB_AD
-set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA
-set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK
-set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA
-set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD
-set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM
-set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS
-set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVWE
-set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVRAS
-set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCAS
-set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nDDR_CLK
-set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC_PAD
-set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to PIXEL_CLK_PAD
-set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VB
-set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG
-set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR
-set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD
-set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nPD_VGA
-set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SRD
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to IO
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRWE
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRCS
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBLE
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBHE
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AMKB_TX
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to FB_AD
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVWE
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVRAS
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCAS
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nDDR_CLK
+set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC_PAD
+set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to PIXEL_CLK_PAD
+set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VB
+set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG
+set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR
+set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD
+set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nPD_VGA
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SRD
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to IO
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRWE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRCS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBLE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBHE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AMKB_TX
 
 	# Simulator Assignments
 	# =====================
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to FB_AD
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_DRQ
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_INT
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CARD_DEDECT
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_WP
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA2
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA1
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA0
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CMD_D1
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CLK
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to FB_AD
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_DRQ
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_INT
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CARD_DEDECT
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_WP
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA2
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA1
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA0
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CMD_D1
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CLK
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3
 
 	# start LOGICLOCK_REGION(Root Region)
 	# -----------------------------------
@@ -557,301 +557,301 @@ set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3
 
 # end ENTITY(firebee1)
 # --------------------
-set_location_assignment PIN_E5 -to LPDIR
-set_location_assignment PIN_B11 -to nRSTO_MCF
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to E0_INT
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to DVI_INT
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTA
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTB
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTC
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTD
-set_location_assignment PIN_AB12 -to CLK33MDIR
-set_location_assignment PIN_E12 -to MIDI_IN_PIN
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MIDI_IN_PIN
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MIDI_IN_PIN
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MIDI_IN_PIN
-set_instance_assignment -name PCI_IO ON -to nPCI_INTA
-set_instance_assignment -name PCI_IO ON -to nPCI_INTB
-set_instance_assignment -name PCI_IO ON -to nPCI_INTC
-set_instance_assignment -name PCI_IO ON -to nPCI_INTD
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_DRQ
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_INT
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTA
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTB
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTC
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTD
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_WP
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_CARD_DEDECT
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK1
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TOUT0
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MAIN_CLK
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to CLK33MDIR
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nRSTO_MCF
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK0
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[2]
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[3]
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TIN0
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TIN0
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[6]
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[5]
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[4]
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[4]
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[5]
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[6]
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[3]
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[2]
-set_global_assignment -name POWER_USE_TA_VALUE 35
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DSA_D
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nMOT_ON
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP_DIR
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR_GATE
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSDSEL
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_PAR
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_DIR
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_SEL
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_RST
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_BUSY
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ATN
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ACK
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_A1
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_CS
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_DIR
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_ACK
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_RESET
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LPDIR
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_STR
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_D
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_D
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LPDIR
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_STR
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to SRD
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[0]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[8]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[7]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[6]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[5]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[4]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[3]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[2]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[1]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBHE
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRWE
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRCS
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBLE
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_RX
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
-set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
-set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
-set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name SMART_RECOMPILE ON
+set_location_assignment PIN_E5 -to LPDIR
+set_location_assignment PIN_B11 -to nRSTO_MCF
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to E0_INT
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to DVI_INT
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTA
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTB
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTC
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTD
+set_location_assignment PIN_AB12 -to CLK33MDIR
+set_location_assignment PIN_E12 -to MIDI_IN_PIN
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MIDI_IN_PIN
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MIDI_IN_PIN
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MIDI_IN_PIN
+set_instance_assignment -name PCI_IO ON -to nPCI_INTA
+set_instance_assignment -name PCI_IO ON -to nPCI_INTB
+set_instance_assignment -name PCI_IO ON -to nPCI_INTC
+set_instance_assignment -name PCI_IO ON -to nPCI_INTD
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_DRQ
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_INT
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTA
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTB
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTC
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTD
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_WP
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_CARD_DEDECT
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK1
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TOUT0
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MAIN_CLK
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to CLK33MDIR
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nRSTO_MCF
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK0
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[2]
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[3]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TIN0
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TIN0
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[6]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[5]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[4]
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[4]
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[5]
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[6]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[3]
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[2]
+set_global_assignment -name POWER_USE_TA_VALUE 35
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DSA_D
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nMOT_ON
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP_DIR
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR_GATE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSDSEL
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_PAR
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_DIR
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_SEL
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_RST
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_BUSY
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ATN
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ACK
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_A1
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_CS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_DIR
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_ACK
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_RESET
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LPDIR
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_STR
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_D
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_D
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LPDIR
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_STR
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to SRD
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[0]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[8]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[7]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[6]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[5]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[4]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[3]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[2]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[1]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBHE
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRWE
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRCS
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBLE
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_RX
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name SMART_RECOMPILE ON
 set_global_assignment -name TOP_LEVEL_ENTITY firebee1
-set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED
-set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED
-set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED
-set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE SPEED
-set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE SPEED
-set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE SPEED
-set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE SPEED
-set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001
-set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
-set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
-set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis
-set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
-set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
-set_global_assignment -name SAVE_DISK_SPACE OFF
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
-set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to MAIN_CLK
-set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to DDR_CLK
-set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to nDDR_CLK
-set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
-set_global_assignment -name VHDL_FILE Video/video_mod_mux_clutctr.vhd
-set_global_assignment -name VHDL_FILE Video/DDR_CTR.vhd
-set_global_assignment -name SOURCE_FILE altpll_reconfig1.cmp
-set_global_assignment -name VHDL_FILE Interrupt_Handler/interrupt_handler.vhd
-set_global_assignment -name SOURCE_FILE altpll4.cmp
-set_global_assignment -name SDC_FILE firebee1.sdc
-set_global_assignment -name VHDL_FILE firebee1.vhd
-set_global_assignment -name VHDL_FILE Video/video.vhd
-set_global_assignment -name VHDL_FILE Video/mux41.vhd
-set_global_assignment -name VHDL_FILE Video/mux41_5.vhd
-set_global_assignment -name VHDL_FILE Video/mux41_4.vhd
-set_global_assignment -name VHDL_FILE Video/mux41_3.vhd
-set_global_assignment -name VHDL_FILE Video/mux41_2.vhd
-set_global_assignment -name VHDL_FILE Video/mux41_1.vhd
-set_global_assignment -name VHDL_FILE Video/mux41_0.vhd
-set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp
-set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp
-set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp
-set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp
-set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp
-set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp
-set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp
-set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp
-set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp
-set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp
-set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp
-set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp
-set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd
-set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp
-set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp
-set_global_assignment -name VHDL_FILE Video/altdpram0.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp
-set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp
-set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp
-set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp
-set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip
-set_global_assignment -name QIP_FILE Video/altdpram0.qip
-set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip
-set_global_assignment -name QIP_FILE Video/altdpram1.qip
-set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip
-set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip
-set_global_assignment -name QIP_FILE Video/lpm_constant0.qip
-set_global_assignment -name QIP_FILE Video/lpm_constant1.qip
-set_global_assignment -name QIP_FILE Video/lpm_mux0.qip
-set_global_assignment -name QIP_FILE Video/lpm_mux1.qip
-set_global_assignment -name QIP_FILE Video/lpm_mux2.qip
-set_global_assignment -name QIP_FILE Video/lpm_constant2.qip
-set_global_assignment -name QIP_FILE Video/altdpram2.qip
-set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip
-set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip
-set_global_assignment -name QIP_FILE Video/altddio_out0.qip
-set_global_assignment -name QIP_FILE Video/lpm_mux5.qip
-set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip
-set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip
-set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip
-set_global_assignment -name QIP_FILE Video/altddio_out1.qip
-set_global_assignment -name QIP_FILE Video/altddio_out2.qip
-set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip
-set_global_assignment -name QIP_FILE Video/lpm_mux6.qip
-set_global_assignment -name QIP_FILE Video/lpm_mux3.qip
-set_global_assignment -name QIP_FILE Video/lpm_mux4.qip
-set_global_assignment -name QIP_FILE Video/lpm_constant3.qip
-set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip
-set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip
-set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip
-set_global_assignment -name QIP_FILE Video/lpm_latch1.qip
-set_global_assignment -name QIP_FILE Video/lpm_constant4.qip
-set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip
-set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift0.qip
-set_global_assignment -name SOURCE_FILE Video/BLITTER/blitter.tdf.ALT
-set_global_assignment -name QIP_FILE Video/lpm_compare1.qip
-set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp
-set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp
-set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd
-set_global_assignment -name QIP_FILE Video/lpm_ff4.qip
-set_global_assignment -name QIP_FILE Video/lpm_ff5.qip
-set_global_assignment -name QIP_FILE Video/lpm_ff6.qip
-set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp
-set_global_assignment -name QIP_FILE Video/BLITTER/altsyncram0.qip
-set_global_assignment -name VHDL_FILE DSP/DSP.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd
-set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd
-set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd
-set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip
-set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd
-set_global_assignment -name VHDL_FILE lpm_latch0.vhd
-set_global_assignment -name SOURCE_FILE lpm_latch0.cmp
-set_global_assignment -name QIP_FILE altpll1.qip
-set_global_assignment -name QIP_FILE altpll2.qip
-set_global_assignment -name QIP_FILE altpll3.qip
-set_global_assignment -name SOURCE_FILE altpll0.cmp
-set_global_assignment -name SOURCE_FILE altpll2.cmp
-set_global_assignment -name VHDL_FILE altpll2.vhd
-set_global_assignment -name SOURCE_FILE altpll3.cmp
-set_global_assignment -name VHDL_FILE altpll3.vhd
-set_global_assignment -name SOURCE_FILE lpm_counter0.cmp
-set_global_assignment -name VHDL_FILE altpll1.vhd
-set_global_assignment -name SOURCE_FILE altpll1.cmp
-set_global_assignment -name QIP_FILE altpll0.qip
-set_global_assignment -name QIP_FILE lpm_counter0.qip
-set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip
-set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip
-set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip
-set_global_assignment -name QIP_FILE altddio_out3.qip
-set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt
-set_global_assignment -name QIP_FILE altpll4.qip
-set_global_assignment -name QIP_FILE lpm_mux0.qip
-set_global_assignment -name QIP_FILE lpm_shiftreg0.qip
-set_global_assignment -name QIP_FILE lpm_counter1.qip
-set_global_assignment -name QIP_FILE altiobuf_bidir0.qip
+set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001
+set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
+set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis
+set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
+set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
+set_global_assignment -name SAVE_DISK_SPACE OFF
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
+set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to MAIN_CLK
+set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to DDR_CLK
+set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to nDDR_CLK
+set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
+set_global_assignment -name VHDL_FILE Video/video_mod_mux_clutctr.vhd
+set_global_assignment -name VHDL_FILE Video/DDR_CTR.vhd
+set_global_assignment -name SOURCE_FILE altpll_reconfig1.cmp
+set_global_assignment -name VHDL_FILE Interrupt_Handler/interrupt_handler.vhd
+set_global_assignment -name SOURCE_FILE altpll4.cmp
+set_global_assignment -name SDC_FILE firebee1.sdc
+set_global_assignment -name VHDL_FILE firebee1.vhd
+set_global_assignment -name VHDL_FILE Video/video.vhd
+set_global_assignment -name VHDL_FILE Video/mux41.vhd
+set_global_assignment -name VHDL_FILE Video/mux41_5.vhd
+set_global_assignment -name VHDL_FILE Video/mux41_4.vhd
+set_global_assignment -name VHDL_FILE Video/mux41_3.vhd
+set_global_assignment -name VHDL_FILE Video/mux41_2.vhd
+set_global_assignment -name VHDL_FILE Video/mux41_1.vhd
+set_global_assignment -name VHDL_FILE Video/mux41_0.vhd
+set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp
+set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp
+set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp
+set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp
+set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp
+set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp
+set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp
+set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp
+set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp
+set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp
+set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp
+set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp
+set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd
+set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp
+set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp
+set_global_assignment -name VHDL_FILE Video/altdpram0.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp
+set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp
+set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp
+set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp
+set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip
+set_global_assignment -name QIP_FILE Video/altdpram0.qip
+set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip
+set_global_assignment -name QIP_FILE Video/altdpram1.qip
+set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip
+set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip
+set_global_assignment -name QIP_FILE Video/lpm_constant0.qip
+set_global_assignment -name QIP_FILE Video/lpm_constant1.qip
+set_global_assignment -name QIP_FILE Video/lpm_mux0.qip
+set_global_assignment -name QIP_FILE Video/lpm_mux1.qip
+set_global_assignment -name QIP_FILE Video/lpm_mux2.qip
+set_global_assignment -name QIP_FILE Video/lpm_constant2.qip
+set_global_assignment -name QIP_FILE Video/altdpram2.qip
+set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip
+set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip
+set_global_assignment -name QIP_FILE Video/altddio_out0.qip
+set_global_assignment -name QIP_FILE Video/lpm_mux5.qip
+set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip
+set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip
+set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip
+set_global_assignment -name QIP_FILE Video/altddio_out1.qip
+set_global_assignment -name QIP_FILE Video/altddio_out2.qip
+set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip
+set_global_assignment -name QIP_FILE Video/lpm_mux6.qip
+set_global_assignment -name QIP_FILE Video/lpm_mux3.qip
+set_global_assignment -name QIP_FILE Video/lpm_mux4.qip
+set_global_assignment -name QIP_FILE Video/lpm_constant3.qip
+set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip
+set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip
+set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip
+set_global_assignment -name QIP_FILE Video/lpm_latch1.qip
+set_global_assignment -name QIP_FILE Video/lpm_constant4.qip
+set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip
+set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift0.qip
+set_global_assignment -name SOURCE_FILE Video/BLITTER/blitter.tdf.ALT
+set_global_assignment -name QIP_FILE Video/lpm_compare1.qip
+set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp
+set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp
+set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd
+set_global_assignment -name QIP_FILE Video/lpm_ff4.qip
+set_global_assignment -name QIP_FILE Video/lpm_ff5.qip
+set_global_assignment -name QIP_FILE Video/lpm_ff6.qip
+set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp
+set_global_assignment -name QIP_FILE Video/BLITTER/altsyncram0.qip
+set_global_assignment -name VHDL_FILE DSP/DSP.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd
+set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd
+set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd
+set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip
+set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd
+set_global_assignment -name VHDL_FILE lpm_latch0.vhd
+set_global_assignment -name SOURCE_FILE lpm_latch0.cmp
+set_global_assignment -name QIP_FILE altpll1.qip
+set_global_assignment -name QIP_FILE altpll2.qip
+set_global_assignment -name QIP_FILE altpll3.qip
+set_global_assignment -name SOURCE_FILE altpll0.cmp
+set_global_assignment -name SOURCE_FILE altpll2.cmp
+set_global_assignment -name VHDL_FILE altpll2.vhd
+set_global_assignment -name SOURCE_FILE altpll3.cmp
+set_global_assignment -name VHDL_FILE altpll3.vhd
+set_global_assignment -name SOURCE_FILE lpm_counter0.cmp
+set_global_assignment -name VHDL_FILE altpll1.vhd
+set_global_assignment -name SOURCE_FILE altpll1.cmp
+set_global_assignment -name QIP_FILE altpll0.qip
+set_global_assignment -name QIP_FILE lpm_counter0.qip
+set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip
+set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip
+set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip
+set_global_assignment -name QIP_FILE altddio_out3.qip
+set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt
+set_global_assignment -name QIP_FILE altpll4.qip
+set_global_assignment -name QIP_FILE lpm_mux0.qip
+set_global_assignment -name QIP_FILE lpm_shiftreg0.qip
+set_global_assignment -name QIP_FILE lpm_counter1.qip
+set_global_assignment -name QIP_FILE altiobuf_bidir0.qip
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/FPGA_Quartus_13.1/firebee1.qws b/FPGA_Quartus_13.1/firebee1.qws
index 2de15470570a5aec89d087b29e9c63673535dafc..e98d7ce0a0ea514a0aa58f4ef02b0141b7afe8a5 100644
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