diff --git a/FPGA_Quartus_13.1/DSP/DSP.vhd b/FPGA_Quartus_13.1/DSP/DSP.vhd index 5dc95de..22ae2ee 100644 --- a/FPGA_Quartus_13.1/DSP/DSP.vhd +++ b/FPGA_Quartus_13.1/DSP/DSP.vhd @@ -1,18 +1,18 @@ --- WARNING: Do NOT edit the input and output ports in this file in a text +-- WARNING: Do NOT edit the input AND output ports in this file in a text -- editor if you plan to continue editing the block that represents it in -- the Block Editor! File corruption is VERY likely to occur. -- Copyright (C) 1991-2008 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any +-- AND other software AND tools, AND its AMPP partner logic +-- functions, AND any output files from any of the foregoing +-- (including device programming or simulation files), AND any -- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License +-- to the terms AND conditions of the Altera Program License -- Subscription Agreement, Altera MegaCore Function License -- Agreement, or other applicable license agreement, including, -- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by +-- programming logic devices manufactured by Altera AND sold by -- Altera or its authorized distributors. Please refer to the -- applicable agreement for further details. @@ -30,28 +30,28 @@ ENTITY dsp IS -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! PORT ( - CLK33M : IN STD_LOGIC; - MAIN_CLK : IN STD_LOGIC; - nFB_OE : IN STD_LOGIC; - nFB_WR : IN STD_LOGIC; - nFB_CS1 : IN STD_LOGIC; - nFB_CS2 : IN STD_LOGIC; - FB_SIZE0 : IN STD_LOGIC; - FB_SIZE1 : IN STD_LOGIC; - nFB_BURST : IN STD_LOGIC; - FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0); - nRSTO : IN STD_LOGIC; - nFB_CS3 : IN STD_LOGIC; - nSRCS : INOUT STD_LOGIC; - nSRBLE : OUT STD_LOGIC; - nSRBHE : OUT STD_LOGIC; - nSRWE : OUT STD_LOGIC; - nSROE : OUT STD_LOGIC; - DSP_INT : OUT STD_LOGIC; - DSP_TA : OUT STD_LOGIC; - FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0); - IO : INOUT STD_LOGIC_VECTOR(17 downto 0); - SRD : INOUT STD_LOGIC_VECTOR(15 downto 0) + CLK33M : IN std_logic; + MAIN_CLK : IN std_logic; + nFB_OE : IN std_logic; + nFB_WR : IN std_logic; + nFB_CS1 : IN std_logic; + nFB_CS2 : IN std_logic; + FB_SIZE0 : IN std_logic; + FB_SIZE1 : IN std_logic; + nFB_BURST : IN std_logic; + FB_ADR : IN std_logic_vector(31 DOWNTO 0); + nRSTO : IN std_logic; + nFB_CS3 : IN std_logic; + nSRCS : INOUT std_logic; + nSRBLE : OUT std_logic; + nSRBHE : OUT std_logic; + nSRWE : OUT std_logic; + nSROE : OUT std_logic; + DSP_INT : OUT std_logic; + DSP_TA : OUT std_logic; + FB_AD : INOUT std_logic_vector(31 DOWNTO 0); + IO : INOUT std_logic_vector(17 DOWNTO 0); + SRD : INOUT std_logic_vector(15 DOWNTO 0) ); -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! @@ -60,20 +60,18 @@ END dsp; -- Architecture Body -ARCHITECTURE rtl OF DSP IS +ARCHITECTURE rtl OF dsp IS BEGIN - nSRCS <= '0' when nFB_CS2 = '0' and FB_ADR(27 downto 24) = x"4" else '1'; --nFB_CS3; - nSRBHE <= '0' when FB_ADR(0 downto 0) = "0" else '1'; - nSRBLE <= '1' when FB_ADR(0 downto 0) = "0" and FB_SIZE1 = '0' and FB_SIZE0 = '1' else '0'; - nSRWE <= '0' when nFB_WR = '0' and nSRCS = '0' and MAIN_CLK = '0' else '1'; - nSROE <= '0' when nFB_OE = '0' and nSRCS = '0' else '1'; + nSRCS <= '0' WHEN nFB_CS2 = '0' AND FB_ADR(27 DOWNTO 24) = x"4" ELSE '1'; --nFB_CS3; + nSRBHE <= '0' WHEN FB_ADR(0 DOWNTO 0) = "0" ELSE '1'; + nSRBLE <= '1' WHEN FB_ADR(0 DOWNTO 0) = "0" AND FB_SIZE1 = '0' AND FB_SIZE0 = '1' ELSE '0'; + nSRWE <= '0' WHEN nFB_WR = '0' AND nSRCS = '0' AND MAIN_CLK = '0' ELSE '1'; + nSROE <= '0' WHEN nFB_OE = '0' AND nSRCS = '0' ELSE '1'; DSP_INT <= '0'; DSP_TA <= '0'; - IO(17 downto 0) <= FB_ADR(18 downto 1); - SRD(15 downto 0) <= FB_AD(31 downto 16) when nFB_WR = '0' and nSRCS = '0' else "ZZZZZZZZZZZZZZZZ"; - FB_AD(31 downto 16) <= SRD(15 downto 0) when nFB_OE = '0' and nSRCS = '0' else "ZZZZZZZZZZZZZZZZ"; - - + IO(17 DOWNTO 0) <= FB_ADR(18 DOWNTO 1); + SRD(15 DOWNTO 0) <= FB_AD(31 DOWNTO 16) WHEN nFB_WR = '0' AND nSRCS = '0' ELSE "ZZZZZZZZZZZZZZZZ"; + FB_AD(31 DOWNTO 16) <= SRD(15 DOWNTO 0) WHEN nFB_OE = '0' AND nSRCS = '0' ELSE "ZZZZZZZZZZZZZZZZ"; END rtl; diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd index d05719b..523161b 100644 --- a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd @@ -20,12 +20,12 @@ -- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008) -- Created on Tue Sep 08 16:24:20 2009 -library work; -use work.FalconIO_SDCard_IDE_CF_pkg.all; +LIBRARY work; + USE work.FalconIO_SDCard_IDE_CF_pkg.ALL; -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; +LIBRARY ieee; + USE ieee.std_logic_1164.ALL; + USE ieee.std_logic_unsigned.ALL; -- Entity Declaration @@ -148,7 +148,7 @@ END falconio_sdcard_ide_cf; -- Architecture Body - ARCHITECTURE rtl OF falconio_sdcard_ide_cf IS +ARCHITECTURE rtl OF falconio_sdcard_ide_cf IS -- system SIGNAL SYS_CLK : std_logic; SIGNAL RESETn : std_logic; diff --git a/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.tdf b/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.tdf index 5131b0f..b569002 100644 --- a/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.tdf +++ b/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.tdf @@ -17,64 +17,64 @@ INCLUDE "lpm_bustri_BYT.inc"; SUBDESIGN interrupt_handler ( -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! - MAIN_CLK : INPUT; - nFB_WR : INPUT; - nFB_CS1 : INPUT; - nFB_CS2 : INPUT; - FB_SIZE0 : INPUT; - FB_SIZE1 : INPUT; - FB_ADR[31..0] : INPUT; - PIC_INT : INPUT; - E0_INT : INPUT; - DVI_INT : INPUT; - nPCI_INTA : INPUT; - nPCI_INTB : INPUT; - nPCI_INTC : INPUT; - nPCI_INTD : INPUT; - nMFP_INT : INPUT; - nFB_OE : INPUT; - DSP_INT : INPUT; - VSYNC : INPUT; - HSYNC : INPUT; - DMA_DRQ : INPUT; - nIRQ[7..2] : OUTPUT; - INT_HANDLER_TA : OUTPUT; - ACP_CONF[31..0] : OUTPUT; - TIN0 : OUTPUT; - FB_AD[31..0] : BIDIR; + MAIN_CLK : INPUT; + nFB_WR : INPUT; + nFB_CS1 : INPUT; + nFB_CS2 : INPUT; + FB_SIZE0 : INPUT; + FB_SIZE1 : INPUT; + FB_ADR[31..0] : INPUT; + PIC_INT : INPUT; + E0_INT : INPUT; + DVI_INT : INPUT; + nPCI_INTA : INPUT; + nPCI_INTB : INPUT; + nPCI_INTC : INPUT; + nPCI_INTD : INPUT; + nMFP_INT : INPUT; + nFB_OE : INPUT; + DSP_INT : INPUT; + VSYNC : INPUT; + HSYNC : INPUT; + DMA_DRQ : INPUT; + nIRQ[7..2] : OUTPUT; + INT_HANDLER_TA : OUTPUT; + ACP_CONF[31..0] : OUTPUT; + TIN0 : OUTPUT; + FB_AD[31..0] : BIDIR; -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! ) VARIABLE - FB_B[3..0] :NODE; - INT_CTR[31..0] :DFFE; - INT_CTR_CS :NODE; - INT_LATCH[31..0] :DFF; - INT_LATCH_CS :NODE; - INT_CLEAR[31..0] :DFF; - INT_CLEAR_CS :NODE; - INT_IN[31..0] :NODE; - INT_ENA[31..0] :DFFE; - INT_ENA_CS :NODE; - ACP_CONF[31..0] :DFFE; - ACP_CONF_CS :NODE; - PSEUDO_BUS_ERROR :NODE; - UHR_AS :NODE; - UHR_DS :NODE; - RTC_ADR[5..0] :DFFE; - ACHTELSEKUNDEN[2..0] :DFFE; - WERTE[7..0][63..0] :DFFE; -- WERTE REGISTER 0-63 - PIC_INT_SYNC[2..0] :DFF; - INC_SEC :NODE; - INC_MIN :NODE; - INC_STD :NODE; - INC_TAG :NODE; + FB_B[3..0] :NODE; + INT_CTR[31..0] :DFFE; + INT_CTR_CS :NODE; + INT_LATCH[31..0] :DFF; + INT_LATCH_CS :NODE; + INT_CLEAR[31..0] :DFF; + INT_CLEAR_CS :NODE; + INT_IN[31..0] :NODE; + INT_ENA[31..0] :DFFE; + INT_ENA_CS :NODE; + ACP_CONF[31..0] :DFFE; + ACP_CONF_CS :NODE; + PSEUDO_BUS_ERROR :NODE; + UHR_AS :NODE; + UHR_DS :NODE; + RTC_ADR[5..0] :DFFE; + ACHTELSEKUNDEN[2..0] :DFFE; + WERTE[7..0][63..0] :DFFE; -- WERTE REGISTER 0-63 + PIC_INT_SYNC[2..0] :DFF; + INC_SEC :NODE; + INC_MIN :NODE; + INC_STD :NODE; + INC_TAG :NODE; ANZAHL_TAGE_DES_MONATS[7..0]:NODE; - WINTERZEIT :NODE; - SOMMERZEIT :NODE; - INC_MONAT :NODE; - INC_JAHR :NODE; - UPDATE_ON :NODE; + WINTERZEIT :NODE; + SOMMERZEIT :NODE; + INC_MONAT :NODE; + INC_JAHR :NODE; + UPDATE_ON :NODE; BEGIN -- BYT SELECT @@ -99,6 +99,7 @@ BEGIN INT_CTR[23..16].ENA = INT_CTR_CS & FB_B1 & !nFB_WR; INT_CTR[15..8].ENA = INT_CTR_CS & FB_B2 & !nFB_WR; INT_CTR[7..0].ENA = INT_CTR_CS & FB_B3 & !nFB_WR; + -- INTERRUPT ENABLE REGISTER BIT31=INT7,30=INT6,29=INT5,28=INT4,27=INT3,26=INT2 INT_ENA[].CLK = MAIN_CLK; INT_ENA_CS = !nFB_CS2 & FB_ADR[27..2]==H"4001"; -- $10004/4 @@ -107,6 +108,7 @@ BEGIN INT_ENA[23..16].ENA = INT_ENA_CS & FB_B1 & !nFB_WR; INT_ENA[15..8].ENA = INT_ENA_CS & FB_B2 & !nFB_WR; INT_ENA[7..0].ENA = INT_ENA_CS & FB_B3 & !nFB_WR; + -- INTERRUPT CLEAR REGISTER WRITE ONLY 1=INTERRUPT CLEAR INT_CLEAR[].CLK = MAIN_CLK; INT_CLEAR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4002"; -- $10008/4 @@ -114,8 +116,10 @@ BEGIN INT_CLEAR[23..16] = FB_AD[23..16] & INT_CLEAR_CS & FB_B1 & !nFB_WR; INT_CLEAR[15..8] = FB_AD[15..8] & INT_CLEAR_CS & FB_B2 & !nFB_WR; INT_CLEAR[7..0] = FB_AD[7..0] & INT_CLEAR_CS & FB_B3 & !nFB_WR; + -- INTERRUPT LATCH REGISTER READ ONLY INT_LATCH_CS = !nFB_CS2 & FB_ADR[27..2]==H"4003"; -- $1000C/4 + -- INTERRUPT !nIRQ2 = HSYNC & INT_ENA[26]; !nIRQ3 = INT_CTR0 & INT_ENA[27]; @@ -139,6 +143,7 @@ PSEUDO_BUS_ERROR = !nFB_CS1 & (FB_ADR[19..4]==H"F8C8" -- SCC # FB_ADR[19..4]==H"F890" -- DMA SOUND # FB_ADR[19..4]==H"F891" -- DMA SOUND # FB_ADR[19..4]==H"F892"); -- DMA SOUND + -- IF VIDEO ADR CHANGE TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR HIGH 0xFFFF8201/2 @@ -176,6 +181,7 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR H INT_IN29 = INT_LATCH[]!=H"00000000"; INT_IN30 = !nMFP_INT; INT_IN31 = DMA_DRQ; + --*************************************************************************************** -- ACP CONFIG REGISTER: BIT 31-> 0=CF 1=IDE ACP_CONF[].CLK = MAIN_CLK; @@ -337,28 +343,34 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR H WERTE[1][11] = VCC; -- IMMER 24H FORMAT WERTE[0][11] = VCC; -- IMMER SOMMERZEITKORREKTUR WERTE[7][13] = VCC; -- IMMER RICHTIG + -- SOMMER WINTERZEIT: BIT 0 IM REGISTER D IST DIE INFORMATION OB SOMMERZEIT IST (BRAUCHT MAN F�R R�CKSCHALTUNG) SOMMERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==4 & WERTE[][7]>23; --LETZTER SONNTAG IM APRIL WERTE[0][13] = SOMMERZEIT; WERTE[0][13].ENA = INC_STD & (SOMMERZEIT # WINTERZEIT); WINTERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==10 & WERTE[][7]>24 & WERTE[0][13]; --LETZTER SONNTAG IM OKTOBER + -- ACHTELSEKUNDEN ACHTELSEKUNDEN[].CLK = MAIN_CLK; ACHTELSEKUNDEN[] = ACHTELSEKUNDEN[]+1; ACHTELSEKUNDEN[].ENA = PIC_INT_SYNC[2] & UPDATE_ON; + -- SEKUNDEN INC_SEC = ACHTELSEKUNDEN[]==7 & PIC_INT_SYNC[2] & UPDATE_ON; WERTE[][0] = (WERTE[][0]+1) & WERTE[][0]!=59 & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR); -- SEKUNDEN Z�HLEN BIS 59 WERTE[][0].ENA = INC_SEC & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR); + -- MINUTEN INC_MIN = INC_SEC & WERTE[][0]==59; -- WERTE[][2] = (WERTE[][2]+1) & WERTE[][2]!=59 & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR); -- MINUTEN Z�HLEN BIS 59 WERTE[][2].ENA = INC_MIN & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR); -- + -- STUNDEN INC_STD = INC_MIN & WERTE[][2]==59; WERTE[][4] = (WERTE[][4]+1+(1 & SOMMERZEIT)) & WERTE[][4]!=23 & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR); -- STUNDEN Z�HLEN BIS 23 WERTE[][4].ENA = INC_STD & !(WINTERZEIT & WERTE[0][12]) & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR); -- EINE STUNDE AUSLASSEN WENN WINTERZEITUMSCHALTUNG UND NOCH SOMMERZEIT -- WOCHENTAG UND TAG + INC_TAG = INC_STD & WERTE[][2]==23; WERTE[][6] = (WERTE[][6]+1) & WERTE[][6]!=7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR) -- WOCHENTAG Z�HLEN BIS 7 # 1 & WERTE[][6]==7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER @@ -370,15 +382,18 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR H WERTE[][7] = (WERTE[][7]+1) & WERTE[][7]!=ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR) -- TAG Z�HLEN BIS MONATSENDE # 1 & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER WERTE[][7].ENA = INC_TAG & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR); -- + -- MONATE INC_MONAT = INC_TAG & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[]; -- WERTE[][8] = (WERTE[][8]+1) & WERTE[][8]!=12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR) -- MONATE Z�HLEN BIS 12 # 1 & WERTE[][8]==12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER WERTE[][8].ENA = INC_MONAT & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR); + -- JAHR INC_JAHR = INC_MONAT & WERTE[][8]==12; -- WERTE[][9] = (WERTE[][9]+1) & WERTE[][9]!=99 & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR); -- JAHRE Z�HLEN BIS 99 WERTE[][9].ENA = INC_JAHR & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR); + -- TRISTATE OUTPUT FB_AD[31..24] = lpm_bustri_BYT( @@ -460,6 +475,7 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR H # INT_CLEAR_CS & INT_IN[23..16] # ACP_CONF_CS & ACP_CONF[23..16] ,(UHR_DS # UHR_AS # INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE); + FB_AD[15..8] = lpm_bustri_BYT( INT_CTR_CS & INT_CTR[15..8] # INT_ENA_CS & INT_ENA[15..8] @@ -467,6 +483,7 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR H # INT_CLEAR_CS & INT_IN[15..8] # ACP_CONF_CS & ACP_CONF[15..8] ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE); + FB_AD[7..0] = lpm_bustri_BYT( INT_CTR_CS & INT_CTR[7..0] # INT_ENA_CS & INT_ENA[7..0] diff --git a/FPGA_Quartus_13.1/firebee1.qsf b/FPGA_Quartus_13.1/firebee1.qsf index 522c2fc..6f21306 100644 --- a/FPGA_Quartus_13.1/firebee1.qsf +++ b/FPGA_Quartus_13.1/firebee1.qsf @@ -372,9 +372,9 @@ set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" set_global_assignment -name FITTER_EFFORT "AUTO FIT" set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON -set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK @@ -743,4 +743,6 @@ set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip set_global_assignment -name QIP_FILE altddio_out3.qip set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt +set_global_assignment -name SAVE_DISK_SPACE OFF +set_global_assignment -name SMART_RECOMPILE ON set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/FPGA_Quartus_13.1/firebee1.sdc b/FPGA_Quartus_13.1/firebee1.sdc index 7e9fe9a..c1b6396 100644 --- a/FPGA_Quartus_13.1/firebee1.sdc +++ b/FPGA_Quartus_13.1/firebee1.sdc @@ -19,7 +19,7 @@ ## PROGRAM "Quartus II" ## VERSION "Version 13.1.4 Build 182 03/12/2014 SJ Web Edition" -## DATE "Sun Sep 20 18:14:49 2015" +## DATE "Sun Sep 20 18:51:37 2015" ## ## DEVICE "EP3C40F484C6" @@ -58,8 +58,8 @@ derive_pll_clocks # Set Clock Uncertainty #************************************************************** -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {MAIN_CLK}] 0.050 -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {MAIN_CLK}] 0.050 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {MAIN_CLK}] 0.080 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {MAIN_CLK}] 0.080 #************************************************************** @@ -90,6 +90,8 @@ set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_genera set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}] set_false_path -from [get_clocks {i_video_clock_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] set_false_path -from [get_clocks {i_video_clock_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}] +set_false_path -from [get_clocks {i_video_clock_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] + set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_id9:dffpipe17|dffe18a*}] set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_hd9:dffpipe12|dffe13a*}] set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_kd9:dffpipe15|dffe16a*}] @@ -103,7 +105,8 @@ set_false_path -from [get_keepers {Video:i_video|video_mod_mux_clutctr:i_video_m #************************************************************** set_multicycle_path -setup -start -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] 8 -set_multicycle_path -hold -end -from [get_clocks {MAIN_CLK}] -to [get_keepers {Video:i_video|DDR_CTR:i_ddr_ctr|MCS[0]}] 2 +set_multicycle_path -setup -end -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] 4 +#set_multicycle_path -hold -end -from [get_clocks {MAIN_CLK}] -to [get_keepers {Video:i_video|DDR_CTR:i_ddr_ctr|MCS[0]}] 2 set_multicycle_path -setup -end -from [get_keepers {Video:i_video|video_mod_mux_clutctr:i_video_mod_mux_clutctr|VDL_VMD[2]}] -to [get_keepers {Video:i_video|video_mod_mux_clutctr:i_video_mod_mux_clutctr|DPO_OFF}] 8