Firebee/FPGA_Config
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This commit is contained in:
Markus Fröschle
2016-01-14 07:17:08 +00:00
parent 69c107ef32
commit b7a34c8abf
2 changed files with 915 additions and 883 deletions
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326
FPGA_Quartus_13.1/Video/DDR_CTR.vhd
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@@ -313,181 +313,213 @@ ARCHITECTURE rtl OF ddr_ctr IS
BEGIN BEGIN
-- Sub Module Section -- Sub Module Section
u0: lpm_bustri_BYT port map (data=>u0_data, enabledt=>u0_enabledt, u0: lpm_bustri_BYT
tridata=>u0_tridata); port map
(
data=>u0_data,
enabledt=>u0_enabledt,
tridata=>u0_tridata
);
-- Register Section -- Register Section
SR_FIFO_WRE <= SR_FIFO_WRE_q; SR_FIFO_WRE <= SR_FIFO_WRE_q;
PROCESS (SR_FIFO_WRE_clk) BEGIN PROCESS (SR_FIFO_WRE_clk)
IF SR_FIFO_WRE_clk'event and SR_FIFO_WRE_clk='1' THEN BEGIN
SR_FIFO_WRE_q <= SR_FIFO_WRE_d; IF SR_FIFO_WRE_clk'event and SR_FIFO_WRE_clk='1' THEN
END IF; SR_FIFO_WRE_q <= SR_FIFO_WRE_d;
END PROCESS; END IF;
END PROCESS;
SR_DDR_WR <= SR_DDR_WR_q; SR_DDR_WR <= SR_DDR_WR_q;
PROCESS (SR_DDR_WR_clk) BEGIN PROCESS (SR_DDR_WR_clk)
IF SR_DDR_WR_clk'event and SR_DDR_WR_clk='1' THEN BEGIN
SR_DDR_WR_q <= SR_DDR_WR_d; IF SR_DDR_WR_clk'event and SR_DDR_WR_clk='1' THEN
END IF; SR_DDR_WR_q <= SR_DDR_WR_d;
END PROCESS; END IF;
END PROCESS;
SR_DDRWR_D_SEL <= SR_DDRWR_D_SEL_q; SR_DDRWR_D_SEL <= SR_DDRWR_D_SEL_q;
PROCESS (SR_DDRWR_D_SEL_clk) BEGIN PROCESS (SR_DDRWR_D_SEL_clk)
IF SR_DDRWR_D_SEL_clk'event and SR_DDRWR_D_SEL_clk='1' THEN BEGIN
SR_DDRWR_D_SEL_q <= SR_DDRWR_D_SEL_d; IF SR_DDRWR_D_SEL_clk'event and SR_DDRWR_D_SEL_clk='1' THEN
END IF; SR_DDRWR_D_SEL_q <= SR_DDRWR_D_SEL_d;
END PROCESS; END IF;
END PROCESS;
SR_VDMP <= SR_VDMP_q; SR_VDMP <= SR_VDMP_q;
PROCESS (SR_VDMP0_clk_ctrl) BEGIN PROCESS (SR_VDMP0_clk_ctrl)
IF SR_VDMP0_clk_ctrl'event and SR_VDMP0_clk_ctrl='1' THEN BEGIN
SR_VDMP_q <= SR_VDMP_d; IF SR_VDMP0_clk_ctrl'event and SR_VDMP0_clk_ctrl='1' THEN
END IF; SR_VDMP_q <= SR_VDMP_d;
END PROCESS; END IF;
END PROCESS;
PROCESS (FB_REGDDR_0_clk_ctrl) BEGIN PROCESS (FB_REGDDR_0_clk_ctrl)
IF FB_REGDDR_0_clk_ctrl'event and FB_REGDDR_0_clk_ctrl='1' THEN BEGIN
FB_REGDDR_q <= FB_REGDDR_d; IF FB_REGDDR_0_clk_ctrl'event and FB_REGDDR_0_clk_ctrl='1' THEN
END IF; FB_REGDDR_q <= FB_REGDDR_d;
END PROCESS; END IF;
END PROCESS;
PROCESS (DDR_SM_0_clk_ctrl) BEGIN PROCESS (DDR_SM_0_clk_ctrl)
IF DDR_SM_0_clk_ctrl'event and DDR_SM_0_clk_ctrl='1' THEN BEGIN
DDR_SM_q <= DDR_SM_d; IF DDR_SM_0_clk_ctrl'event and DDR_SM_0_clk_ctrl='1' THEN
END IF; DDR_SM_q <= DDR_SM_d;
END PROCESS; END IF;
END PROCESS;
PROCESS (VA_P0_clk_ctrl) BEGIN PROCESS (VA_P0_clk_ctrl)
IF VA_P0_clk_ctrl'event and VA_P0_clk_ctrl='1' THEN BEGIN
VA_P_q <= VA_P_d; IF VA_P0_clk_ctrl'event and VA_P0_clk_ctrl='1' THEN
END IF; VA_P_q <= VA_P_d;
END PROCESS; END IF;
END PROCESS;
PROCESS (BA_P0_clk_ctrl) BEGIN PROCESS (BA_P0_clk_ctrl)
IF BA_P0_clk_ctrl'event and BA_P0_clk_ctrl='1' THEN BEGIN
BA_P_q <= BA_P_d; IF BA_P0_clk_ctrl'event and BA_P0_clk_ctrl='1' THEN
END IF; BA_P_q <= BA_P_d;
END PROCESS; END IF;
END PROCESS;
PROCESS (VA_S0_clk_ctrl) BEGIN PROCESS (VA_S0_clk_ctrl)
IF VA_S0_clk_ctrl'event and VA_S0_clk_ctrl='1' THEN BEGIN
VA_S_q <= VA_S_d; IF VA_S0_clk_ctrl'event and VA_S0_clk_ctrl='1' THEN
END IF; VA_S_q <= VA_S_d;
END PROCESS; END IF;
END PROCESS;
PROCESS (BA_S0_clk_ctrl) BEGIN PROCESS (BA_S0_clk_ctrl)
IF BA_S0_clk_ctrl'event and BA_S0_clk_ctrl='1' THEN BEGIN
BA_S_q <= BA_S_d; IF BA_S0_clk_ctrl'event and BA_S0_clk_ctrl='1' THEN
END IF; BA_S_q <= BA_S_d;
END PROCESS; END IF;
END PROCESS;
PROCESS (MCS0_clk_ctrl) BEGIN PROCESS (MCS0_clk_ctrl)
IF MCS0_clk_ctrl'event and MCS0_clk_ctrl='1' THEN BEGIN
MCS_q <= MCS_d; IF MCS0_clk_ctrl'event and MCS0_clk_ctrl='1' THEN
END IF; MCS_q <= MCS_d;
END PROCESS; END IF;
END PROCESS;
PROCESS (CPU_DDR_SYNC_clk) BEGIN PROCESS (CPU_DDR_SYNC_clk)
IF CPU_DDR_SYNC_clk'event and CPU_DDR_SYNC_clk='1' THEN BEGIN
CPU_DDR_SYNC_q <= CPU_DDR_SYNC_d; IF CPU_DDR_SYNC_clk'event and CPU_DDR_SYNC_clk='1' THEN
END IF; CPU_DDR_SYNC_q <= CPU_DDR_SYNC_d;
END PROCESS; END IF;
END PROCESS;
PROCESS (DDR_CS_clk) BEGIN PROCESS (DDR_CS_clk)
IF DDR_CS_clk'event and DDR_CS_clk='1' THEN BEGIN
IF DDR_CS_ena='1' THEN IF DDR_CS_clk'event and DDR_CS_clk='1' THEN
DDR_CS_q <= DDR_CS_d; IF DDR_CS_ena='1' THEN
END IF; DDR_CS_q <= DDR_CS_d;
END IF; END IF;
END PROCESS; END IF;
END PROCESS;
PROCESS (CPU_REQ_clk) BEGIN PROCESS (CPU_REQ_clk)
IF CPU_REQ_clk'event and CPU_REQ_clk='1' THEN BEGIN
CPU_REQ_q <= CPU_REQ_d; IF CPU_REQ_clk'event and CPU_REQ_clk='1' THEN
END IF; CPU_REQ_q <= CPU_REQ_d;
END PROCESS; END IF;
END PROCESS;
PROCESS (CPU_AC_clk) BEGIN PROCESS (CPU_AC_clk)
IF CPU_AC_clk'event and CPU_AC_clk='1' THEN BEGIN
CPU_AC_q <= CPU_AC_d; IF CPU_AC_clk'event and CPU_AC_clk='1' THEN
END IF; CPU_AC_q <= CPU_AC_d;
END PROCESS; END IF;
END PROCESS;
PROCESS (BUS_CYC_clk) BEGIN PROCESS (BUS_CYC_clk)
IF BUS_CYC_clk'event and BUS_CYC_clk='1' THEN BEGIN
BUS_CYC_q <= BUS_CYC_d; IF BUS_CYC_clk'event and BUS_CYC_clk='1' THEN
END IF; BUS_CYC_q <= BUS_CYC_d;
END PROCESS; END IF;
END PROCESS;
PROCESS (BLITTER_REQ_clk) BEGIN PROCESS (BLITTER_REQ_clk)
IF BLITTER_REQ_clk'event and BLITTER_REQ_clk='1' THEN BEGIN
BLITTER_REQ_q <= BLITTER_REQ_d; IF BLITTER_REQ_clk'event and BLITTER_REQ_clk='1' THEN
END IF; BLITTER_REQ_q <= BLITTER_REQ_d;
END PROCESS; END IF;
END PROCESS;
PROCESS (BLITTER_AC_clk) BEGIN PROCESS (BLITTER_AC_clk)
IF BLITTER_AC_clk'event and BLITTER_AC_clk='1' THEN BEGIN
BLITTER_AC_q <= BLITTER_AC_d; IF BLITTER_AC_clk'event and BLITTER_AC_clk='1' THEN
END IF; BLITTER_AC_q <= BLITTER_AC_d;
END PROCESS; END IF;
END PROCESS;
PROCESS (FIFO_REQ_clk) BEGIN PROCESS (FIFO_REQ_clk)
IF FIFO_REQ_clk'event and FIFO_REQ_clk='1' THEN BEGIN
FIFO_REQ_q <= FIFO_REQ_d; IF FIFO_REQ_clk'event and FIFO_REQ_clk='1' THEN
END IF; FIFO_REQ_q <= FIFO_REQ_d;
END PROCESS; END IF;
END PROCESS;
PROCESS (FIFO_AC_clk) BEGIN PROCESS (FIFO_AC_clk)
IF FIFO_AC_clk'event and FIFO_AC_clk='1' THEN BEGIN
FIFO_AC_q <= FIFO_AC_d; IF FIFO_AC_clk'event and FIFO_AC_clk='1' THEN
END IF; FIFO_AC_q <= FIFO_AC_d;
END PROCESS; END IF;
END PROCESS;
PROCESS (CLR_FIFO_SYNC_clk) BEGIN PROCESS (CLR_FIFO_SYNC_clk)
IF CLR_FIFO_SYNC_clk'event and CLR_FIFO_SYNC_clk='1' THEN BEGIN
CLR_FIFO_SYNC_q <= CLR_FIFO_SYNC_d; IF CLR_FIFO_SYNC_clk'event and CLR_FIFO_SYNC_clk='1' THEN
END IF; CLR_FIFO_SYNC_q <= CLR_FIFO_SYNC_d;
END PROCESS; END IF;
END PROCESS;
PROCESS (CLEAR_FIFO_CNT_clk) BEGIN PROCESS (CLEAR_FIFO_CNT_clk)
IF CLEAR_FIFO_CNT_clk'event and CLEAR_FIFO_CNT_clk='1' THEN BEGIN
CLEAR_FIFO_CNT_q <= CLEAR_FIFO_CNT_d; IF CLEAR_FIFO_CNT_clk'event and CLEAR_FIFO_CNT_clk='1' THEN
END IF; CLEAR_FIFO_CNT_q <= CLEAR_FIFO_CNT_d;
END PROCESS; END IF;
END PROCESS;
PROCESS (STOP_clk) BEGIN PROCESS (STOP_clk)
IF STOP_clk'event and STOP_clk='1' THEN BEGIN
STOP_q <= STOP_d; IF STOP_clk'event and STOP_clk='1' THEN
END IF; STOP_q <= STOP_d;
END PROCESS; END IF;
END PROCESS;
PROCESS (FIFO_BANK_OK_clk) BEGIN PROCESS (FIFO_BANK_OK_clk)
IF FIFO_BANK_OK_clk'event and FIFO_BANK_OK_clk='1' THEN BEGIN
FIFO_BANK_OK_q <= FIFO_BANK_OK_d; IF FIFO_BANK_OK_clk'event and FIFO_BANK_OK_clk='1' THEN
END IF; FIFO_BANK_OK_q <= FIFO_BANK_OK_d;
END PROCESS; END IF;
END PROCESS;
PROCESS (DDR_REFRESH_CNT0_clk_ctrl) BEGIN PROCESS (DDR_REFRESH_CNT0_clk_ctrl)
IF DDR_REFRESH_CNT0_clk_ctrl'event and DDR_REFRESH_CNT0_clk_ctrl='1' THEN BEGIN
DDR_REFRESH_CNT_q <= DDR_REFRESH_CNT_d; IF DDR_REFRESH_CNT0_clk_ctrl'event and DDR_REFRESH_CNT0_clk_ctrl='1' THEN
END IF; DDR_REFRESH_CNT_q <= DDR_REFRESH_CNT_d;
END PROCESS; END IF;
END PROCESS;
PROCESS (DDR_REFRESH_REQ_clk) BEGIN PROCESS (DDR_REFRESH_REQ_clk)
IF DDR_REFRESH_REQ_clk'event and DDR_REFRESH_REQ_clk='1' THEN BEGIN
DDR_REFRESH_REQ_q <= DDR_REFRESH_REQ_d; IF DDR_REFRESH_REQ_clk'event and DDR_REFRESH_REQ_clk='1' THEN
END IF; DDR_REFRESH_REQ_q <= DDR_REFRESH_REQ_d;
END PROCESS; END IF;
END PROCESS;
PROCESS (DDR_REFRESH_SIG0_clk_ctrl) BEGIN PROCESS (DDR_REFRESH_SIG0_clk_ctrl)
IF DDR_REFRESH_SIG0_clk_ctrl'event and DDR_REFRESH_SIG0_clk_ctrl='1' THEN BEGIN
IF DDR_REFRESH_SIG0_ena_ctrl='1' THEN IF DDR_REFRESH_SIG0_clk_ctrl'event and DDR_REFRESH_SIG0_clk_ctrl='1' THEN
DDR_REFRESH_SIG_q <= DDR_REFRESH_SIG_d; IF DDR_REFRESH_SIG0_ena_ctrl='1' THEN
END IF; DDR_REFRESH_SIG_q <= DDR_REFRESH_SIG_d;
END IF; END IF;
END PROCESS; END IF;
END PROCESS;
PROCESS (REFRESH_TIME_clk) BEGIN PROCESS (REFRESH_TIME_clk) BEGIN
IF REFRESH_TIME_clk'event and REFRESH_TIME_clk='1' THEN IF REFRESH_TIME_clk'event and REFRESH_TIME_clk='1' THEN

1472
FPGA_Quartus_13.1/firebee1.qsf
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