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reactivated delay chain

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This commit is contained in:
Markus Fröschle
2016-01-13 15:04:24 +00:00
parent fd5abf8b4a
commit 97a48bf636
3 changed files with 200 additions and 174 deletions
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6
FPGA_Quartus_13.1/Video/video.vhd
View File

@@ -1929,7 +1929,7 @@ BEGIN
PORT MAP PORT MAP
( (
wren_a => ST_CLUT_WR(1), wren_a => ST_CLUT_WR(1),
wren_b => SYNTHESIZED_WIRE_55, wren_b => '0',
clock_a => MAIN_CLK, clock_a => MAIN_CLK,
clock_b => pixel_clk_i, clock_b => pixel_clk_i,
address_a => FB_ADR(4 DOWNTO 1), address_a => FB_ADR(4 DOWNTO 1),
@@ -1945,7 +1945,7 @@ BEGIN
PORT MAP PORT MAP
( (
wren_a => ST_CLUT_WR(1), wren_a => ST_CLUT_WR(1),
wren_b => SYNTHESIZED_WIRE_56, wren_b => '0',
clock_a => MAIN_CLK, clock_a => MAIN_CLK,
clock_b => pixel_clk_i, clock_b => pixel_clk_i,
address_a => FB_ADR(4 DOWNTO 1), address_a => FB_ADR(4 DOWNTO 1),
@@ -1961,7 +1961,7 @@ BEGIN
PORT MAP PORT MAP
( (
wren_a => ST_CLUT_WR(0), wren_a => ST_CLUT_WR(0),
wren_b => SYNTHESIZED_WIRE_57, wren_b => '0',
clock_a => MAIN_CLK, clock_a => MAIN_CLK,
clock_b => pixel_clk_i, clock_b => pixel_clk_i,
address_a => FB_ADR(4 DOWNTO 1), address_a => FB_ADR(4 DOWNTO 1),

58
FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd
View File

@@ -265,20 +265,44 @@ ARCHITECTURE rtl OF video_mod_mux_clutctr IS
SIGNAL u0_tridata : std_logic_vector(15 DOWNTO 0); SIGNAL u0_tridata : std_logic_vector(15 DOWNTO 0);
SIGNAL u1_data : std_logic_vector(15 DOWNTO 0); SIGNAL u1_data : std_logic_vector(15 DOWNTO 0);
SIGNAL u1_tridata : std_logic_vector(15 DOWNTO 0); SIGNAL u1_tridata : std_logic_vector(15 DOWNTO 0);
SIGNAL ST_SHIFT_MODE0_clk_ctrl, ST_SHIFT_MODE0_ena_ctrl, SIGNAL ST_SHIFT_MODE0_clk_ctrl : std_logic;
FALCON_SHIFT_MODE0_clk_ctrl, FALCON_SHIFT_MODE8_ena_ctrl, SIGNAL ST_SHIFT_MODE0_ena_ctrl : std_logic;
FALCON_SHIFT_MODE0_ena_ctrl, ACP_VCTR0_clk_ctrl, ACP_VCTR24_ena_ctrl, SIGNAL FALCON_SHIFT_MODE0_clk_ctrl : std_logic;
ACP_VCTR16_ena_ctrl, ACP_VCTR8_ena_ctrl, ACP_VCTR0_ena_ctrl, SIGNAL FALCON_SHIFT_MODE8_ena_ctrl : std_logic;
ATARI_HH0_clk_ctrl, ATARI_HH24_ena_ctrl, ATARI_HH16_ena_ctrl, SIGNAL FALCON_SHIFT_MODE0_ena_ctrl : std_logic;
ATARI_HH8_ena_ctrl, ATARI_HH0_ena_ctrl, ATARI_VH0_clk_ctrl, SIGNAL ACP_VCTR0_clk_ctrl : std_logic;
ATARI_VH24_ena_ctrl, ATARI_VH16_ena_ctrl, ATARI_VH8_ena_ctrl, SIGNAL ACP_VCTR24_ena_ctrl : std_logic;
ATARI_VH0_ena_ctrl, ATARI_HL0_clk_ctrl, ATARI_HL24_ena_ctrl, SIGNAL ACP_VCTR16_ena_ctrl : std_logic;
ATARI_HL16_ena_ctrl, ATARI_HL8_ena_ctrl, ATARI_HL0_ena_ctrl, SIGNAL ACP_VCTR8_ena_ctrl : std_logic;
ATARI_VL0_clk_ctrl, ATARI_VL24_ena_ctrl, ATARI_VL16_ena_ctrl, SIGNAL ACP_VCTR0_ena_ctrl : std_logic;
ATARI_VL8_ena_ctrl, ATARI_VL0_ena_ctrl, VR_DOUT0_clk_ctrl, SIGNAL ATARI_HH0_clk_ctrl : std_logic;
VR_DOUT0_ena_ctrl, VR_FRQ0_clk_ctrl, VR_FRQ0_ena_ctrl, SIGNAL ATARI_HH24_ena_ctrl : std_logic;
ACP_VCTR6_ena_ctrl, CCSEL0_clk_ctrl, BORDER_COLOR0_clk_ctrl, SIGNAL ATARI_HH16_ena_ctrl : std_logic;
BORDER_COLOR16_ena_ctrl, BORDER_COLOR8_ena_ctrl, SIGNAL ATARI_HH8_ena_ctrl : std_logic;
SIGNAL ATARI_HH0_ena_ctrl : std_logic;
SIGNAL ATARI_VH0_clk_ctrl : std_logic;
SIGNAL ATARI_VH24_ena_ctrl : std_logic;
SIGNAL ATARI_VH16_ena_ctrl : std_logic;
SIGNAL ATARI_VH8_ena_ctrl : std_logic;
SIGNAL ATARI_VH0_ena_ctrl : std_logic;
SIGNAL ATARI_HL0_clk_ctrl : std_logic;
SIGNAL ATARI_HL24_ena_ctrl : std_logic;
SIGNAL ATARI_HL16_ena_ctrl : std_logic;
SIGNAL ATARI_HL8_ena_ctrl : std_logic;
SIGNAL ATARI_HL0_ena_ctrl : std_logic;
SIGNAL ATARI_VL0_clk_ctrl : std_logic;
SIGNAL ATARI_VL24_ena_ctrl : std_logic;
SIGNAL ATARI_VL16_ena_ctrl : std_logic;
SIGNAL ATARI_VL8_ena_ctrl : std_logic;
SIGNAL ATARI_VL0_ena_ctrl : std_logic;
SIGNAL VR_DOUT0_clk_ctrl : std_logic;
SIGNAL VR_DOUT0_ena_ctrl : std_logic;
SIGNAL VR_FRQ0_clk_ctrl : std_logic;
SIGNAL VR_FRQ0_ena_ctrl : std_logic;
SIGNAL ACP_VCTR6_ena_ctrl : std_logic;
SIGNAL CCSEL0_clk_ctrl : std_logic;
SIGNAL BORDER_COLOR0_clk_ctrl : std_logic;
SIGNAL BORDER_COLOR16_ena_ctrl, BORDER_COLOR8_ena_ctrl,
BORDER_COLOR0_ena_ctrl, SYS_CTR0_clk_ctrl, SYS_CTR0_ena_ctrl, BORDER_COLOR0_ena_ctrl, SYS_CTR0_clk_ctrl, SYS_CTR0_ena_ctrl,
LOF0_clk_ctrl, LOF8_ena_ctrl, LOF0_ena_ctrl, LWD0_clk_ctrl, LOF0_clk_ctrl, LOF8_ena_ctrl, LOF0_ena_ctrl, LWD0_clk_ctrl,
LWD8_ena_ctrl, LWD0_ena_ctrl, HHT0_clk_ctrl, HHT8_ena_ctrl, LWD8_ena_ctrl, LWD0_ena_ctrl, HHT0_clk_ctrl, HHT8_ena_ctrl,
@@ -1950,7 +1974,8 @@ begin
nBLANK_clk <= PIXEL_CLK; nBLANK_clk <= PIXEL_CLK;
-- nBLANK = VERZ[0][8]; -- nBLANK = VERZ[0][8];
nBLANK_d <= DISP_ON_q; nblank_d <= verz0_q(8);
-- nBLANK_d <= DISP_ON_q;
HSYNC_clk <= PIXEL_CLK; HSYNC_clk <= PIXEL_CLK;
-- HSYNC = VERZ[1][9]; -- HSYNC = VERZ[1][9];
@@ -1978,7 +2003,8 @@ begin
RAND_d(6) <= RAND_q(5); RAND_d(6) <= RAND_q(5);
-- RAND_ON = RAND[6]; -- RAND_ON = RAND[6];
RAND_ON <= DISP_ON_q and (not VDTRON_q) and ACP_VCTR_q(25); rand_on <= rand(6);
-- RAND_ON <= DISP_ON_q and (not VDTRON_q) and ACP_VCTR_q(25);
-- -------------------------------------------------------- -- --------------------------------------------------------
CLR_FIFO_clk <= PIXEL_CLK; CLR_FIFO_clk <= PIXEL_CLK;