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improved timing, added timing constraints, got rid of CLK_33M

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Design compiles and runs, but still has issues with different screen resolutions and video clocks
This commit is contained in:
Markus Fröschle
2015-09-23 09:49:05 +00:00
parent ad05ca8523
commit 7e2181fbc9
19 changed files with 1631 additions and 1519 deletions
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32
FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd
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@@ -150,21 +150,21 @@ END falconio_sdcard_ide_cf;
ARCHITECTURE rtl OF falconio_sdcard_ide_cf IS ARCHITECTURE rtl OF falconio_sdcard_ide_cf IS
-- system -- system
SIGNAL SYS_CLK : std_logic; SIGNAL SYS_CLK : std_logic;
SIGNAL RESETn : std_logic; SIGNAL RESETn : std_logic;
SIGNAL FB_B0 : std_logic; -- UPPER BYT BEI 16BIT BUS SIGNAL FB_B0 : std_logic; -- UPPER BYT BEI 16BIT BUS
SIGNAL FB_B1 : std_logic; -- LOWER BYT BEI 16BIT BUS SIGNAL FB_B1 : std_logic; -- LOWER BYT BEI 16BIT BUS
SIGNAL BYT : std_logic; -- WENN BYT -> 1 SIGNAL BYT : std_logic; -- WENN BYT -> 1
SIGNAL LONG : std_logic; -- WENN -> 1 SIGNAL LONG : std_logic; -- WENN -> 1
-- KEYBOARD MIDI -- KEYBOARD MIDI
SIGNAL ACIA_CS_I : std_logic; SIGNAL ACIA_CS_I : std_logic;
SIGNAL IRQ_KEYBDn : std_logic; SIGNAL IRQ_KEYBDn : std_logic;
SIGNAL IRQ_MIDIn : std_logic; SIGNAL IRQ_MIDIn : std_logic;
SIGNAL KEYB_RxD : std_logic; SIGNAL KEYB_RxD : std_logic;
SIGNAL AMKB_REG : std_logic_vector(4 DOWNTO 0); SIGNAL AMKB_REG : std_logic_vector(4 DOWNTO 0);
SIGNAL MIDI_OUT : std_logic; SIGNAL MIDI_OUT : std_logic;
SIGNAL DATA_OUT_ACIA_I : std_logic_vector(7 DOWNTO 0); SIGNAL DATA_OUT_ACIA_I : std_logic_vector(7 DOWNTO 0);
SIGNAL DATA_OUT_ACIA_II : std_logic_vector(7 DOWNTO 0); SIGNAL DATA_OUT_ACIA_II : std_logic_vector(7 DOWNTO 0);
-- MFP -- MFP
SIGNAL MFP_CS : std_logic; SIGNAL MFP_CS : std_logic;
SIGNAL MFP_INTACK : std_logic; SIGNAL MFP_INTACK : std_logic;
@@ -370,7 +370,7 @@ BEGIN
-- ACSI, SCSI UND FLOPPY WD1772 -- ACSI, SCSI UND FLOPPY WD1772
------------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------------
-- daten read fifo -- daten read fifo
RDF: dcfifo0 i_data_read_fifo: dcfifo0
PORT MAP( PORT MAP(
aclr => CLR_FIFO, aclr => CLR_FIFO,
data => RDF_DIN, data => RDF_DIN,
@@ -390,7 +390,7 @@ BEGIN
RDF_DIN <= CD_OUT_FDC WHEN DMA_MODUS(7) = '1' ELSE SCSI_DOUT; RDF_DIN <= CD_OUT_FDC WHEN DMA_MODUS(7) = '1' ELSE SCSI_DOUT;
-- daten write fifo -- daten write fifo
WRF: dcfifo1 i_data_write_fifo: dcfifo1
PORT MAP( PORT MAP(
aclr => CLR_FIFO, aclr => CLR_FIFO,
data => FB_AD(7 DOWNTO 0) & FB_AD(15 DOWNTO 8) & FB_AD(23 DOWNTO 16) & FB_AD(31 DOWNTO 24), data => FB_AD(7 DOWNTO 0) & FB_AD(15 DOWNTO 8) & FB_AD(23 DOWNTO 16) & FB_AD(31 DOWNTO 24),
@@ -527,7 +527,7 @@ BEGIN
END CASE; END CASE;
END PROCESS FCF_DECODER; END PROCESS FCF_DECODER;
I_FDC: WF1772IP_TOP_SOC i_fdc : WF1772IP_TOP_SOC
PORT MAP( PORT MAP(
CLK => FDC_CLK, CLK => FDC_CLK,
RESETn => nRSTO, RESETn => nRSTO,
@@ -731,7 +731,7 @@ BEGIN
CLR_FIFO <= DMA_MODUS(8) XOR DMA_DIR_OLD; CLR_FIFO <= DMA_MODUS(8) XOR DMA_DIR_OLD;
-- SCSI ---------------------------------------------------------------------------------- -- SCSI ----------------------------------------------------------------------------------
I_SCSI: WF5380_TOP_SOC i_scsi : WF5380_TOP_SOC
PORT MAP( PORT MAP(
CLK => FDC_CLK, CLK => FDC_CLK,
RESETn => nRSTO, RESETn => nRSTO,
@@ -810,7 +810,7 @@ BEGIN
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
-- ACIA KEYBOARD -- ACIA KEYBOARD
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
I_ACIA_KEYBOARD: WF6850IP_TOP_SOC i_acia_keyboard : WF6850IP_TOP_SOC
PORT MAP( PORT MAP(
CLK => MAIN_CLK, CLK => MAIN_CLK,
RESETn => nRSTO, RESETn => nRSTO,
@@ -867,7 +867,7 @@ BEGIN
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
-- ACIA MIDI -- ACIA MIDI
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
I_ACIA_MIDI: WF6850IP_TOP_SOC i_acia_midi : WF6850IP_TOP_SOC
PORT MAP( PORT MAP(
CLK => MAIN_CLK, CLK => MAIN_CLK,
RESETn => nRSTO, RESETn => nRSTO,
@@ -901,7 +901,7 @@ BEGIN
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
-- MFP -- MFP
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
I_MFP: WF68901IP_TOP_SOC i_mfp : WF68901IP_TOP_SOC
PORT MAP( PORT MAP(
-- System control: -- System control:
CLK => MAIN_CLK, CLK => MAIN_CLK,
@@ -978,7 +978,7 @@ BEGIN
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
-- Sound -- Sound
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
I_SOUND: WF2149IP_TOP_SOC i_sound : WF2149IP_TOP_SOC
PORT MAP( PORT MAP(
SYS_CLK => MAIN_CLK, SYS_CLK => MAIN_CLK,
RESETn => nRSTO, RESETn => nRSTO,

2
FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf
View File

@@ -552,7 +552,7 @@ BEGIN
-- VIDEO AUSGABE SETZEN -- VIDEO AUSGABE SETZEN
CLK17M.CLK = CLK33M; CLK17M.CLK = MAIN_CLK;
CLK17M = !CLK17M; CLK17M = !CLK17M;
CLK13M.CLK = CLK25M; CLK13M.CLK = CLK25M;
CLK13M = !CLK13M; CLK13M = !CLK13M;

200
FPGA_Quartus_13.1/altpll1.bsf
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@@ -1,100 +1,100 @@
/* /*
WARNING: Do NOT edit the input and output ports in this file in a text WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur. the Block Editor! File corruption is VERY likely to occur.
*/ */
/* /*
Copyright (C) 1991-2010 Altera Corporation Copyright (C) 1991-2014 Altera Corporation
Your use of Altera Corporation's design tools, logic functions Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing functions, and any output files from any of the foregoing
(including device programming or simulation files), and any (including device programming or simulation files), and any
associated documentation or information are expressly subject associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including, Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the Altera or its authorized distributors. Please refer to the
applicable agreement for further details. applicable agreement for further details.
*/ */
(header "symbol" (version "1.1")) (header "symbol" (version "1.2"))
(symbol (symbol
(rect 0 0 328 216) (rect 0 0 272 176)
(text "altpll1" (rect 144 1 191 20)(font "Arial" (font_size 10))) (text "altpll1" (rect 119 0 160 16)(font "Arial" (font_size 10)))
(text "inst" (rect 8 197 31 212)(font "Arial" )) (text "inst" (rect 8 161 26 172)(font "Arial" ))
(port (port
(pt 0 72) (pt 0 64)
(input) (input)
(text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8))) (text "inclk0" (rect 0 0 34 13)(font "Arial" (font_size 8)))
(text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8))) (text "inclk0" (rect 4 51 31 63)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 48 72)(line_width 1)) (line (pt 0 64)(pt 40 64))
) )
(port (port
(pt 328 72) (pt 272 64)
(output) (output)
(text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8))) (text "c0" (rect 0 0 15 13)(font "Arial" (font_size 8)))
(text "c0" (rect 311 56 325 72)(font "Arial" (font_size 8))) (text "c0" (rect 257 51 269 63)(font "Arial" (font_size 8)))
(line (pt 328 72)(pt 272 72)(line_width 1)) )
) (port
(port (pt 272 80)
(pt 328 96) (output)
(output) (text "c1" (rect 0 0 14 13)(font "Arial" (font_size 8)))
(text "c1" (rect 0 0 16 16)(font "Arial" (font_size 8))) (text "c1" (rect 257 67 267 79)(font "Arial" (font_size 8)))
(text "c1" (rect 311 80 325 96)(font "Arial" (font_size 8))) )
(line (pt 328 96)(pt 272 96)(line_width 1)) (port
) (pt 272 96)
(port (output)
(pt 328 120) (text "c2" (rect 0 0 15 13)(font "Arial" (font_size 8)))
(output) (text "c2" (rect 257 83 269 95)(font "Arial" (font_size 8)))
(text "c2" (rect 0 0 16 16)(font "Arial" (font_size 8))) )
(text "c2" (rect 311 104 325 120)(font "Arial" (font_size 8))) (port
(line (pt 328 120)(pt 272 120)(line_width 1)) (pt 272 112)
) (output)
(port (text "locked" (rect 0 0 37 13)(font "Arial" (font_size 8)))
(pt 328 144) (text "locked" (rect 237 99 268 111)(font "Arial" (font_size 8)))
(output) )
(text "locked" (rect 0 0 44 16)(font "Arial" (font_size 8))) (drawing
(text "locked" (rect 287 128 325 144)(font "Arial" (font_size 8))) (text "Cyclone III" (rect 214 162 474 334)(font "Arial" ))
(line (pt 328 144)(pt 272 144)(line_width 1)) (text "inclk0 frequency: 33.000 MHz" (rect 50 60 226 130)(font "Arial" ))
) (text "Operation Mode: Src Sync Comp" (rect 50 72 239 154)(font "Arial" ))
(drawing (text "Clk " (rect 51 91 117 192)(font "Arial" ))
(text "Cyclone III" (rect 253 198 301 212)(font "Arial" )) (text "Ratio" (rect 82 91 187 192)(font "Arial" ))
(text "inclk0 frequency: 33.000 MHz" (rect 58 67 201 81)(font "Arial" )) (text "Ph (dg)" (rect 119 91 269 192)(font "Arial" ))
(text "Operation Mode: Src Sync Comp" (rect 58 84 215 98)(font "Arial" )) (text "DC (%)" (rect 154 91 340 192)(font "Arial" ))
(text "Clk " (rect 59 111 76 125)(font "Arial" )) (text "c0" (rect 54 104 119 218)(font "Arial" ))
(text "Ratio" (rect 90 111 114 125)(font "Arial" )) (text "1/66" (rect 84 104 186 218)(font "Arial" ))
(text "Ph (dg)" (rect 128 111 163 125)(font "Arial" )) (text "0.00" (rect 125 104 269 218)(font "Arial" ))
(text "DC (%)" (rect 173 111 208 125)(font "Arial" )) (text "50.00" (rect 158 104 340 218)(font "Arial" ))
(text "c0" (rect 63 129 75 143)(font "Arial" )) (text "c1" (rect 54 117 118 244)(font "Arial" ))
(text "1/66" (rect 92 129 113 143)(font "Arial" )) (text "512/6875" (rect 74 117 187 244)(font "Arial" ))
(text "0.00" (rect 136 129 157 143)(font "Arial" )) (text "0.00" (rect 125 117 269 244)(font "Arial" ))
(text "50.00" (rect 178 129 205 143)(font "Arial" )) (text "50.00" (rect 158 117 340 244)(font "Arial" ))
(text "c1" (rect 63 147 75 161)(font "Arial" )) (text "c2" (rect 54 130 119 270)(font "Arial" ))
(text "67/900" (rect 85 147 118 161)(font "Arial" )) (text "1024/1375" (rect 71 130 185 270)(font "Arial" ))
(text "0.00" (rect 136 147 157 161)(font "Arial" )) (text "0.00" (rect 125 130 269 270)(font "Arial" ))
(text "50.00" (rect 178 147 205 161)(font "Arial" )) (text "50.00" (rect 158 130 340 270)(font "Arial" ))
(text "c2" (rect 63 165 75 179)(font "Arial" )) (line (pt 0 0)(pt 273 0))
(text "67/90" (rect 89 165 116 179)(font "Arial" )) (line (pt 273 0)(pt 273 177))
(text "0.00" (rect 136 165 157 179)(font "Arial" )) (line (pt 0 177)(pt 273 177))
(text "50.00" (rect 178 165 205 179)(font "Arial" )) (line (pt 0 0)(pt 0 177))
(line (pt 0 0)(pt 329 0)(line_width 1)) (line (pt 48 89)(pt 186 89))
(line (pt 329 0)(pt 329 217)(line_width 1)) (line (pt 48 101)(pt 186 101))
(line (pt 0 217)(pt 329 217)(line_width 1)) (line (pt 48 114)(pt 186 114))
(line (pt 0 0)(pt 0 217)(line_width 1)) (line (pt 48 127)(pt 186 127))
(line (pt 56 108)(pt 215 108)(line_width 1)) (line (pt 48 140)(pt 186 140))
(line (pt 56 125)(pt 215 125)(line_width 1)) (line (pt 48 89)(pt 48 140))
(line (pt 56 143)(pt 215 143)(line_width 1)) (line (pt 68 89)(pt 68 140)(line_width 3))
(line (pt 56 161)(pt 215 161)(line_width 1)) (line (pt 116 89)(pt 116 140)(line_width 3))
(line (pt 56 179)(pt 215 179)(line_width 1)) (line (pt 151 89)(pt 151 140)(line_width 3))
(line (pt 56 108)(pt 56 179)(line_width 1)) (line (pt 185 89)(pt 185 140))
(line (pt 82 108)(pt 82 179)(line_width 3)) (line (pt 40 48)(pt 223 48))
(line (pt 125 108)(pt 125 179)(line_width 3)) (line (pt 223 48)(pt 223 159))
(line (pt 170 108)(pt 170 179)(line_width 3)) (line (pt 40 159)(pt 223 159))
(line (pt 214 108)(pt 214 179)(line_width 1)) (line (pt 40 48)(pt 40 159))
(line (pt 48 56)(pt 272 56)(line_width 1)) (line (pt 271 64)(pt 223 64))
(line (pt 272 56)(pt 272 200)(line_width 1)) (line (pt 271 80)(pt 223 80))
(line (pt 48 200)(pt 272 200)(line_width 1)) (line (pt 271 96)(pt 223 96))
(line (pt 48 56)(pt 48 200)(line_width 1)) (line (pt 271 112)(pt 223 112))
) )
) )

50
FPGA_Quartus_13.1/altpll1.cmp
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@@ -1,25 +1,25 @@
--Copyright (C) 1991-2010 Altera Corporation --Copyright (C) 1991-2014 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions --Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic --and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing --functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any --(including device programming or simulation files), and any
--associated documentation or information are expressly subject --associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License --to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License --Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including, --Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of --without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by --programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the --Altera or its authorized distributors. Please refer to the
--applicable agreement for further details. --applicable agreement for further details.
component altpll1 component altpll1
PORT PORT
( (
inclk0 : IN STD_LOGIC := '0'; inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ; c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ; c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ; c2 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC locked : OUT STD_LOGIC
); );
end component; end component;

52
FPGA_Quartus_13.1/altpll1.inc
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@@ -1,26 +1,26 @@
--Copyright (C) 1991-2010 Altera Corporation --Copyright (C) 1991-2014 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions --Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic --and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing --functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any --(including device programming or simulation files), and any
--associated documentation or information are expressly subject --associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License --to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License --Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including, --Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of --without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by --programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the --Altera or its authorized distributors. Please refer to the
--applicable agreement for further details. --applicable agreement for further details.
FUNCTION altpll1 FUNCTION altpll1
( (
inclk0 inclk0
) )
RETURNS ( RETURNS (
c0, c0,
c1, c1,
c2, c2,
locked locked
); );

24
FPGA_Quartus_13.1/altpll1.ppf
View File

@@ -1,12 +1,12 @@
<?xml version="1.0" encoding="UTF-8" ?> <?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE pinplan> <!DOCTYPE pinplan>
<pinplan intended_family="Cyclone III" variation_name="altpll1" megafunction_name="ALTPLL" specifies="all_ports"> <pinplan intended_family="Cyclone III" variation_name="altpll1" megafunction_name="ALTPLL" specifies="all_ports">
<global> <global>
<pin name="inclk0" direction="input" scope="external" source="clock" /> <pin name="inclk0" direction="input" scope="external" source="clock" />
<pin name="c0" direction="output" scope="external" source="clock" /> <pin name="c0" direction="output" scope="external" source="clock" />
<pin name="c1" direction="output" scope="external" source="clock" /> <pin name="c1" direction="output" scope="external" source="clock" />
<pin name="c2" direction="output" scope="external" source="clock" /> <pin name="c2" direction="output" scope="external" source="clock" />
<pin name="locked" direction="output" scope="external" /> <pin name="locked" direction="output" scope="external" />
</global> </global>
</pinplan> </pinplan>

14
FPGA_Quartus_13.1/altpll1.qip
View File

@@ -1,7 +1,7 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL" set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "9.1" set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll1.vhd"] set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll1.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.bsf"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.inc"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.inc"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.cmp"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.cmp"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.ppf"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.ppf"]

846
FPGA_Quartus_13.1/altpll1.vhd
View File

@@ -1,423 +1,423 @@
-- megafunction wizard: %ALTPLL% -- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD -- GENERATION: STANDARD
-- VERSION: WM1.0 -- VERSION: WM1.0
-- MODULE: altpll -- MODULE: altpll
-- ============================================================ -- ============================================================
-- File Name: altpll1.vhd -- File Name: altpll1.vhd
-- Megafunction Name(s): -- Megafunction Name(s):
-- altpll -- altpll
-- --
-- Simulation Library Files(s): -- Simulation Library Files(s):
-- altera_mf -- altera_mf
-- ============================================================ -- ============================================================
-- ************************************************************ -- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- --
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition -- 13.1.4 Build 182 03/12/2014 SJ Web Edition
-- ************************************************************ -- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation --Copyright (C) 1991-2014 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions --Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic --and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing --functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any --(including device programming or simulation files), and any
--associated documentation or information are expressly subject --associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License --to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License --Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including, --Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of --without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by --programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the --Altera or its authorized distributors. Please refer to the
--applicable agreement for further details. --applicable agreement for further details.
LIBRARY ieee; LIBRARY ieee;
USE ieee.std_logic_1164.all; USE ieee.std_logic_1164.all;
LIBRARY altera_mf; LIBRARY altera_mf;
USE altera_mf.all; USE altera_mf.all;
ENTITY altpll1 IS ENTITY altpll1 IS
PORT PORT
( (
inclk0 : IN STD_LOGIC := '0'; inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ; c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ; c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ; c2 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC locked : OUT STD_LOGIC
); );
END altpll1; END altpll1;
ARCHITECTURE SYN OF altpll1 IS ARCHITECTURE SYN OF altpll1 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ; SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ; SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ; SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ; SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ; SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll COMPONENT altpll
GENERIC ( GENERIC (
bandwidth_type : STRING; bandwidth_type : STRING;
clk0_divide_by : NATURAL; clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL; clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL; clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING; clk0_phase_shift : STRING;
clk1_divide_by : NATURAL; clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL; clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL; clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING; clk1_phase_shift : STRING;
clk2_divide_by : NATURAL; clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL; clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL; clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING; clk2_phase_shift : STRING;
compensate_clock : STRING; compensate_clock : STRING;
inclk0_input_frequency : NATURAL; inclk0_input_frequency : NATURAL;
intended_device_family : STRING; intended_device_family : STRING;
lpm_type : STRING; lpm_type : STRING;
operation_mode : STRING; operation_mode : STRING;
pll_type : STRING; pll_type : STRING;
port_activeclock : STRING; port_activeclock : STRING;
port_areset : STRING; port_areset : STRING;
port_clkbad0 : STRING; port_clkbad0 : STRING;
port_clkbad1 : STRING; port_clkbad1 : STRING;
port_clkloss : STRING; port_clkloss : STRING;
port_clkswitch : STRING; port_clkswitch : STRING;
port_configupdate : STRING; port_configupdate : STRING;
port_fbin : STRING; port_fbin : STRING;
port_inclk0 : STRING; port_inclk0 : STRING;
port_inclk1 : STRING; port_inclk1 : STRING;
port_locked : STRING; port_locked : STRING;
port_pfdena : STRING; port_pfdena : STRING;
port_phasecounterselect : STRING; port_phasecounterselect : STRING;
port_phasedone : STRING; port_phasedone : STRING;
port_phasestep : STRING; port_phasestep : STRING;
port_phaseupdown : STRING; port_phaseupdown : STRING;
port_pllena : STRING; port_pllena : STRING;
port_scanaclr : STRING; port_scanaclr : STRING;
port_scanclk : STRING; port_scanclk : STRING;
port_scanclkena : STRING; port_scanclkena : STRING;
port_scandata : STRING; port_scandata : STRING;
port_scandataout : STRING; port_scandataout : STRING;
port_scandone : STRING; port_scandone : STRING;
port_scanread : STRING; port_scanread : STRING;
port_scanwrite : STRING; port_scanwrite : STRING;
port_clk0 : STRING; port_clk0 : STRING;
port_clk1 : STRING; port_clk1 : STRING;
port_clk2 : STRING; port_clk2 : STRING;
port_clk3 : STRING; port_clk3 : STRING;
port_clk4 : STRING; port_clk4 : STRING;
port_clk5 : STRING; port_clk5 : STRING;
port_clkena0 : STRING; port_clkena0 : STRING;
port_clkena1 : STRING; port_clkena1 : STRING;
port_clkena2 : STRING; port_clkena2 : STRING;
port_clkena3 : STRING; port_clkena3 : STRING;
port_clkena4 : STRING; port_clkena4 : STRING;
port_clkena5 : STRING; port_clkena5 : STRING;
port_extclk0 : STRING; port_extclk0 : STRING;
port_extclk1 : STRING; port_extclk1 : STRING;
port_extclk2 : STRING; port_extclk2 : STRING;
port_extclk3 : STRING; port_extclk3 : STRING;
self_reset_on_loss_lock : STRING; self_reset_on_loss_lock : STRING;
width_clock : NATURAL width_clock : NATURAL
); );
PORT ( PORT (
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
locked : OUT STD_LOGIC ; inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) locked : OUT STD_LOGIC
); );
END COMPONENT; END COMPONENT;
BEGIN BEGIN
sub_wire7_bv(0 DOWNTO 0) <= "0"; sub_wire7_bv(0 DOWNTO 0) <= "0";
sub_wire7 <= To_stdlogicvector(sub_wire7_bv); sub_wire7 <= To_stdlogicvector(sub_wire7_bv);
sub_wire3 <= sub_wire0(2); sub_wire4 <= sub_wire0(2);
sub_wire2 <= sub_wire0(1); sub_wire3 <= sub_wire0(0);
sub_wire1 <= sub_wire0(0); sub_wire1 <= sub_wire0(1);
c0 <= sub_wire1; c1 <= sub_wire1;
c1 <= sub_wire2; locked <= sub_wire2;
c2 <= sub_wire3; c0 <= sub_wire3;
locked <= sub_wire4; c2 <= sub_wire4;
sub_wire5 <= inclk0; sub_wire5 <= inclk0;
sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5;
altpll_component : altpll altpll_component : altpll
GENERIC MAP ( GENERIC MAP (
bandwidth_type => "AUTO", bandwidth_type => "AUTO",
clk0_divide_by => 66, clk0_divide_by => 66,
clk0_duty_cycle => 50, clk0_duty_cycle => 50,
clk0_multiply_by => 1, clk0_multiply_by => 1,
clk0_phase_shift => "0", clk0_phase_shift => "0",
clk1_divide_by => 900, clk1_divide_by => 6875,
clk1_duty_cycle => 50, clk1_duty_cycle => 50,
clk1_multiply_by => 67, clk1_multiply_by => 512,
clk1_phase_shift => "0", clk1_phase_shift => "0",
clk2_divide_by => 90, clk2_divide_by => 1375,
clk2_duty_cycle => 50, clk2_duty_cycle => 50,
clk2_multiply_by => 67, clk2_multiply_by => 1024,
clk2_phase_shift => "0", clk2_phase_shift => "0",
compensate_clock => "CLK0", compensate_clock => "CLK0",
inclk0_input_frequency => 30303, inclk0_input_frequency => 30303,
intended_device_family => "Cyclone III", intended_device_family => "Cyclone III",
lpm_type => "altpll", lpm_type => "altpll",
operation_mode => "SOURCE_SYNCHRONOUS", operation_mode => "SOURCE_SYNCHRONOUS",
pll_type => "AUTO", pll_type => "AUTO",
port_activeclock => "PORT_UNUSED", port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED", port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED", port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED", port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED", port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED", port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED", port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED", port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED", port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED", port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED", port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED", port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED", port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED", port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED", port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED", port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED", port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED", port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED", port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED", port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED", port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED", port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED", port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED", port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED", port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED", port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED", port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED", port_clk2 => "PORT_USED",
port_clk3 => "PORT_UNUSED", port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED", port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED", port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED", port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED", port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED", port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED", port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED", port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED", port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED", port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED", port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED", port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED", port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF", self_reset_on_loss_lock => "OFF",
width_clock => 5 width_clock => 5
) )
PORT MAP ( PORT MAP (
inclk => sub_wire6, inclk => sub_wire6,
clk => sub_wire0, clk => sub_wire0,
locked => sub_wire4 locked => sub_wire2
); );
END SYN; END SYN;
-- ============================================================ -- ============================================================
-- CNX file retrieval info -- CNX file retrieval info
-- ============================================================ -- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" -- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" -- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" -- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" -- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" -- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" -- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" -- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" -- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" -- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" -- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" -- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" -- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" -- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" -- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" -- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "90" -- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "90"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "900" -- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "900"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "90" -- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "90"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "0.500000" -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "0.500000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "2.456667" -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "2.457600"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "24.566668" -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "24.576000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" -- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" -- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" -- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" -- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.000" -- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" -- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" -- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" -- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" -- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" -- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" -- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" -- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" -- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000" -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" -- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" -- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" -- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" -- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "67" -- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "67"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "67" -- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "67"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "67" -- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "67"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0" -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "0.50000000" -- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "0.50000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "2.45760000" -- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "2.45760000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "24.57600000" -- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "24.57600000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" -- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" -- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" -- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" -- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" -- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" -- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" -- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" -- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" -- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" -- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" -- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" -- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" -- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" -- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" -- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" -- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll1.mif" -- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll1.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" -- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" -- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" -- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" -- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" -- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" -- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" -- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" -- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" -- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1" -- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" -- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" -- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" -- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" -- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" -- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" -- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1" -- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1" -- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" -- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" -- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" -- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" -- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" -- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "66" -- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "66"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" -- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "900" -- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "6875"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "67" -- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "512"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" -- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "90" -- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1375"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" -- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "67" -- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1024"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" -- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303" -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS" -- Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" -- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" -- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" -- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" -- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" -- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" -- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" -- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" -- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" -- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" -- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 -- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 -- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 -- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 -- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 -- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 -- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.ppf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.inc TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_inst.vhd FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_waveforms.html TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_wave*.jpg FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf -- Retrieval info: LIB_FILE: altera_mf

4
FPGA_Quartus_13.1/altpll3.bsf
View File

@@ -71,11 +71,11 @@ applicable agreement for further details.
(text "0.00" (rect 115 117 249 244)(font "Arial" )) (text "0.00" (rect 115 117 249 244)(font "Arial" ))
(text "50.00" (rect 148 117 320 244)(font "Arial" )) (text "50.00" (rect 148 117 320 244)(font "Arial" ))
(text "c2" (rect 54 130 119 270)(font "Arial" )) (text "c2" (rect 54 130 119 270)(font "Arial" ))
(text "109/144" (rect 71 130 175 270)(font "Arial" )) (text "227/300" (rect 71 130 176 270)(font "Arial" ))
(text "0.00" (rect 115 130 249 270)(font "Arial" )) (text "0.00" (rect 115 130 249 270)(font "Arial" ))
(text "50.00" (rect 148 130 320 270)(font "Arial" )) (text "50.00" (rect 148 130 320 270)(font "Arial" ))
(text "c3" (rect 54 143 119 296)(font "Arial" )) (text "c3" (rect 54 143 119 296)(font "Arial" ))
(text "16/11" (rect 77 143 176 296)(font "Arial" )) (text "227/156" (rect 71 143 176 296)(font "Arial" ))
(text "0.00" (rect 115 143 249 296)(font "Arial" )) (text "0.00" (rect 115 143 249 296)(font "Arial" ))
(text "50.00" (rect 148 143 320 296)(font "Arial" )) (text "50.00" (rect 148 143 320 296)(font "Arial" ))
(line (pt 0 0)(pt 257 0)) (line (pt 0 0)(pt 257 0))

38
FPGA_Quartus_13.1/altpll3.vhd
View File

@@ -164,13 +164,13 @@ BEGIN
clk1_duty_cycle => 50, clk1_duty_cycle => 50,
clk1_multiply_by => 16, clk1_multiply_by => 16,
clk1_phase_shift => "0", clk1_phase_shift => "0",
clk2_divide_by => 144, clk2_divide_by => 300,
clk2_duty_cycle => 50, clk2_duty_cycle => 50,
clk2_multiply_by => 109, clk2_multiply_by => 227,
clk2_phase_shift => "0", clk2_phase_shift => "0",
clk3_divide_by => 11, clk3_divide_by => 156,
clk3_duty_cycle => 50, clk3_duty_cycle => 50,
clk3_multiply_by => 16, clk3_multiply_by => 227,
clk3_phase_shift => "0", clk3_phase_shift => "0",
compensate_clock => "CLK1", compensate_clock => "CLK1",
inclk0_input_frequency => 30303, inclk0_input_frequency => 30303,
@@ -249,18 +249,18 @@ END SYN;
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c1" -- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c1"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" -- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "33" -- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "3744"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "33" -- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "33"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "144" -- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "300"
-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "33" -- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "156"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "2.000000" -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "2.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "16.000000" -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "16.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "24.979166" -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "24.969999"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "48.000000" -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "48.019230"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -289,16 +289,16 @@ END SYN;
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" -- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" -- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" -- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2" -- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "227"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "16" -- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "16"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "109" -- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "227"
-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "48" -- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "227"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0" -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "2.00000000" -- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "2.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "16.00000000" -- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "16.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "25.00000000" -- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "25.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "160.00000000" -- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "48.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
@@ -365,13 +365,13 @@ END SYN;
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "16" -- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "16"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" -- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "144" -- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "300"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" -- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "109" -- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "227"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" -- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "11" -- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "156"
-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" -- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "16" -- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "227"
-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" -- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK1" -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK1"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303" -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303"
@@ -440,6 +440,6 @@ END SYN;
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.bsf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_inst.vhd FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_waveforms.html TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_waveforms.html FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_wave*.jpg FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf -- Retrieval info: LIB_FILE: altera_mf

152
FPGA_Quartus_13.1/altpll4.bsf
View File

@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur. the Block Editor! File corruption is VERY likely to occur.
*/ */
/* /*
Copyright (C) 1991-2010 Altera Corporation Copyright (C) 1991-2014 Altera Corporation
Your use of Altera Corporation's design tools, logic functions Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing functions, and any output files from any of the foregoing
@@ -18,108 +18,108 @@ programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the Altera or its authorized distributors. Please refer to the
applicable agreement for further details. applicable agreement for further details.
*/ */
(header "symbol" (version "1.1")) (header "symbol" (version "1.2"))
(symbol (symbol
(rect 0 0 376 232) (rect 0 0 312 184)
(text "altpll4" (rect 168 1 215 20)(font "Arial" (font_size 10))) (text "altpll4" (rect 139 0 179 16)(font "Arial" (font_size 10)))
(text "inst" (rect 8 213 31 228)(font "Arial" )) (text "inst" (rect 8 168 25 180)(font "Arial" ))
(port (port
(pt 0 72) (pt 0 64)
(input) (input)
(text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8))) (text "inclk0" (rect 0 0 31 14)(font "Arial" (font_size 8)))
(text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8))) (text "inclk0" (rect 4 50 29 63)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 88 72)(line_width 1)) (line (pt 0 64)(pt 72 64))
)
(port
(pt 0 80)
(input)
(text "areset" (rect 0 0 36 14)(font "Arial" (font_size 8)))
(text "areset" (rect 4 66 33 79)(font "Arial" (font_size 8)))
(line (pt 0 80)(pt 72 80))
) )
(port (port
(pt 0 96) (pt 0 96)
(input) (input)
(text "areset" (rect 0 0 42 16)(font "Arial" (font_size 8))) (text "scanclk" (rect 0 0 43 14)(font "Arial" (font_size 8)))
(text "areset" (rect 4 80 40 96)(font "Arial" (font_size 8))) (text "scanclk" (rect 4 82 39 95)(font "Arial" (font_size 8)))
(line (pt 0 96)(pt 88 96)(line_width 1)) (line (pt 0 96)(pt 72 96))
) )
(port (port
(pt 0 120) (pt 0 112)
(input) (input)
(text "scanclk" (rect 0 0 53 16)(font "Arial" (font_size 8))) (text "scandata" (rect 0 0 53 14)(font "Arial" (font_size 8)))
(text "scanclk" (rect 4 104 49 120)(font "Arial" (font_size 8))) (text "scandata" (rect 4 98 47 111)(font "Arial" (font_size 8)))
(line (pt 0 120)(pt 88 120)(line_width 1)) (line (pt 0 112)(pt 72 112))
)
(port
(pt 0 128)
(input)
(text "scanclkena" (rect 0 0 64 14)(font "Arial" (font_size 8)))
(text "scanclkena" (rect 4 114 57 127)(font "Arial" (font_size 8)))
(line (pt 0 128)(pt 72 128))
) )
(port (port
(pt 0 144) (pt 0 144)
(input) (input)
(text "scandata" (rect 0 0 62 16)(font "Arial" (font_size 8))) (text "configupdate" (rect 0 0 74 14)(font "Arial" (font_size 8)))
(text "scandata" (rect 4 128 57 144)(font "Arial" (font_size 8))) (text "configupdate" (rect 4 130 65 143)(font "Arial" (font_size 8)))
(line (pt 0 144)(pt 88 144)(line_width 1)) (line (pt 0 144)(pt 72 144))
) )
(port (port
(pt 0 168) (pt 312 64)
(input)
(text "scanclkena" (rect 0 0 77 16)(font "Arial" (font_size 8)))
(text "scanclkena" (rect 4 152 70 168)(font "Arial" (font_size 8)))
(line (pt 0 168)(pt 88 168)(line_width 1))
)
(port
(pt 0 192)
(input)
(text "configupdate" (rect 0 0 86 16)(font "Arial" (font_size 8)))
(text "configupdate" (rect 4 176 77 192)(font "Arial" (font_size 8)))
(line (pt 0 192)(pt 88 192)(line_width 1))
)
(port
(pt 376 72)
(output) (output)
(text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8))) (text "c0" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "c0" (rect 359 56 373 72)(font "Arial" (font_size 8))) (text "c0" (rect 296 50 306 63)(font "Arial" (font_size 8)))
(line (pt 376 72)(pt 288 72)(line_width 1))
) )
(port (port
(pt 376 96) (pt 312 80)
(output) (output)
(text "scandataout" (rect 0 0 83 16)(font "Arial" (font_size 8))) (text "scandataout" (rect 0 0 70 14)(font "Arial" (font_size 8)))
(text "scandataout" (rect 302 80 373 96)(font "Arial" (font_size 8))) (text "scandataout" (rect 248 66 306 79)(font "Arial" (font_size 8)))
(line (pt 376 96)(pt 288 96)(line_width 1))
) )
(port (port
(pt 376 120) (pt 312 96)
(output) (output)
(text "scandone" (rect 0 0 66 16)(font "Arial" (font_size 8))) (text "scandone" (rect 0 0 56 14)(font "Arial" (font_size 8)))
(text "scandone" (rect 317 104 373 120)(font "Arial" (font_size 8))) (text "scandone" (rect 260 82 306 95)(font "Arial" (font_size 8)))
(line (pt 376 120)(pt 288 120)(line_width 1))
) )
(port (port
(pt 376 144) (pt 312 112)
(output) (output)
(text "locked" (rect 0 0 44 16)(font "Arial" (font_size 8))) (text "locked" (rect 0 0 36 14)(font "Arial" (font_size 8)))
(text "locked" (rect 335 128 373 144)(font "Arial" (font_size 8))) (text "locked" (rect 277 98 306 111)(font "Arial" (font_size 8)))
(line (pt 376 144)(pt 288 144)(line_width 1))
) )
(drawing (drawing
(text "Cyclone III" (rect 301 214 349 228)(font "Arial" )) (text "Cyclone III" (rect 250 169 545 349)(font "Arial" ))
(text "inclk0 frequency: 48.000 MHz" (rect 98 123 241 137)(font "Arial" )) (text "inclk0 frequency: 48.019 MHz" (rect 82 92 287 195)(font "Arial" ))
(text "Operation Mode: Normal" (rect 98 140 213 154)(font "Arial" )) (text "Operation Mode: Normal" (rect 82 105 263 221)(font "Arial" ))
(text "Clk " (rect 99 167 116 181)(font "Arial" )) (text "Clk " (rect 83 126 180 263)(font "Arial" ))
(text "Ratio" (rect 125 167 149 181)(font "Arial" )) (text "Ratio" (rect 104 126 228 263)(font "Arial" ))
(text "Ph (dg)" (rect 159 167 194 181)(font "Arial" )) (text "Ph (dg)" (rect 130 126 289 263)(font "Arial" ))
(text "DC (%)" (rect 204 167 239 181)(font "Arial" )) (text "DC (%)" (rect 164 126 358 263)(font "Arial" ))
(text "c0" (rect 103 185 115 199)(font "Arial" )) (text "c0" (rect 86 140 180 291)(font "Arial" ))
(text "2/1" (rect 131 185 146 199)(font "Arial" )) (text "2/1" (rect 109 140 228 291)(font "Arial" ))
(text "0.00" (rect 167 185 188 199)(font "Arial" )) (text "0.00" (rect 136 140 288 291)(font "Arial" ))
(text "50.00" (rect 209 185 236 199)(font "Arial" )) (text "50.00" (rect 168 140 357 291)(font "Arial" ))
(line (pt 0 0)(pt 377 0)(line_width 1)) (line (pt 0 0)(pt 313 0))
(line (pt 377 0)(pt 377 233)(line_width 1)) (line (pt 313 0)(pt 313 186))
(line (pt 0 233)(pt 377 233)(line_width 1)) (line (pt 0 186)(pt 313 186))
(line (pt 0 0)(pt 0 233)(line_width 1)) (line (pt 0 0)(pt 0 186))
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(line (pt 96 181)(pt 246 181)(line_width 1)) (line (pt 80 137)(pt 196 137))
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(line (pt 245 164)(pt 245 199)(line_width 1)) (line (pt 195 124)(pt 195 151))
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(line (pt 88 56)(pt 88 216)(line_width 1)) (line (pt 72 48)(pt 72 168))
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) )

2
FPGA_Quartus_13.1/altpll4.cmp
View File

@@ -1,4 +1,4 @@
--Copyright (C) 1991-2010 Altera Corporation --Copyright (C) 1991-2014 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions --Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic --and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing --functions, and any output files from any of the foregoing

2
FPGA_Quartus_13.1/altpll4.inc
View File

@@ -1,4 +1,4 @@
--Copyright (C) 1991-2010 Altera Corporation --Copyright (C) 1991-2014 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions --Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic --and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing --functions, and any output files from any of the foregoing

6
FPGA_Quartus_13.1/altpll4.mif
View File

@@ -1,4 +1,4 @@
-- Copyright (C) 1991-2010 Altera Corporation -- Copyright (C) 1991-2014 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions -- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic -- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing -- functions, and any output files from any of the foregoing
@@ -17,8 +17,8 @@
-- Device Part: - -- Device Part: -
-- Device Speed Grade: 8 -- Device Speed Grade: 8
-- PLL Scan Chain: Fast PLL (144 bits) -- PLL Scan Chain: Fast PLL (144 bits)
-- File Name: C:\FireBee\FPGA\altpll4.mif -- File Name: C:/Users/froesm1/Documents/Development/FPGA_quartus//altpll4.mif
-- Generated: Mon Dec 06 01:47:24 2010 -- Generated: Mon Sep 21 17:50:54 2015
WIDTH=1; WIDTH=1;
DEPTH=144; DEPTH=144;

2
FPGA_Quartus_13.1/altpll4.qip
View File

@@ -1,5 +1,5 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL" set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "9.1" set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.tdf"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.tdf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.bsf"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.inc"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.inc"]

46
FPGA_Quartus_13.1/altpll4.tdf
View File

@@ -14,11 +14,11 @@
-- ************************************************************ -- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- --
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition -- 13.1.4 Build 182 03/12/2014 SJ Web Edition
-- ************************************************************ -- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation --Copyright (C) 1991-2014 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions --Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic --and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing --functions, and any output files from any of the foregoing
@@ -59,7 +59,7 @@ VARIABLE
CLK0_MULTIPLY_BY = 2, CLK0_MULTIPLY_BY = 2,
CLK0_PHASE_SHIFT = "0", CLK0_PHASE_SHIFT = "0",
COMPENSATE_CLOCK = "CLK0", COMPENSATE_CLOCK = "CLK0",
INCLK0_INPUT_FREQUENCY = 20833, INCLK0_INPUT_FREQUENCY = 20824,
INTENDED_DEVICE_FAMILY = "Cyclone III", INTENDED_DEVICE_FAMILY = "Cyclone III",
LPM_TYPE = "altpll", LPM_TYPE = "altpll",
OPERATION_MODE = "NORMAL", OPERATION_MODE = "NORMAL",
@@ -113,16 +113,16 @@ VARIABLE
BEGIN BEGIN
c0 = altpll_component.clk[0..0]; c0 = altpll_component.clk[0..0];
scandone = altpll_component.scandone;
scandataout = altpll_component.scandataout; scandataout = altpll_component.scandataout;
scandone = altpll_component.scandone;
locked = altpll_component.locked; locked = altpll_component.locked;
altpll_component.scanclkena = scanclkena; altpll_component.areset = areset;
altpll_component.configupdate = configupdate;
altpll_component.inclk[0..0] = inclk0; altpll_component.inclk[0..0] = inclk0;
altpll_component.inclk[1..1] = GND; altpll_component.inclk[1..1] = GND;
altpll_component.scandata = scandata;
altpll_component.areset = areset;
altpll_component.scanclk = scanclk; altpll_component.scanclk = scanclk;
altpll_component.configupdate = configupdate; altpll_component.scanclkena = scanclkena;
altpll_component.scandata = scandata;
END; END;
@@ -148,7 +148,7 @@ END;
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" -- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "96.000000" -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "96.038460"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -156,7 +156,7 @@ END;
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" -- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" -- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" -- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.000" -- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.019"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" -- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" -- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" -- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
@@ -166,7 +166,7 @@ END;
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" -- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" -- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" -- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "336.000" -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" -- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
@@ -217,7 +217,7 @@ END;
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" -- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20833" -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20824"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" -- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
@@ -277,22 +277,22 @@ END;
-- Retrieval info: USED_PORT: scandata 0 0 0 0 INPUT GND "scandata" -- Retrieval info: USED_PORT: scandata 0 0 0 0 INPUT GND "scandata"
-- Retrieval info: USED_PORT: scandataout 0 0 0 0 OUTPUT VCC "scandataout" -- Retrieval info: USED_PORT: scandataout 0 0 0 0 OUTPUT VCC "scandataout"
-- Retrieval info: USED_PORT: scandone 0 0 0 0 OUTPUT VCC "scandone" -- Retrieval info: USED_PORT: scandone 0 0 0 0 OUTPUT VCC "scandone"
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: CONNECT: scandone 0 0 0 0 @scandone 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: @scandata 0 0 0 0 scandata 0 0 0 0
-- Retrieval info: CONNECT: @scanclkena 0 0 0 0 scanclkena 0 0 0 0
-- Retrieval info: CONNECT: @configupdate 0 0 0 0 configupdate 0 0 0 0
-- Retrieval info: CONNECT: scandataout 0 0 0 0 @scandataout 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 -- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @configupdate 0 0 0 0 configupdate 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0
-- Retrieval info: CONNECT: @scanclkena 0 0 0 0 scanclkena 0 0 0 0
-- Retrieval info: CONNECT: @scandata 0 0 0 0 scandata 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: CONNECT: scandataout 0 0 0 0 @scandataout 0 0 0 0
-- Retrieval info: CONNECT: scandone 0 0 0 0 @scandone 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.tdf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.tdf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.ppf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.inc TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4_inst.tdf FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4_inst.tdf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.mif TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.mif TRUE
-- Retrieval info: LIB_FILE: altera_mf -- Retrieval info: LIB_FILE: altera_mf

270
FPGA_Quartus_13.1/firebee1.bdf
View File

@@ -2373,7 +2373,7 @@ applicable agreement for further details.
(pt 144 40) (pt 144 40)
(output) (output)
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(text "q[17..0]" (rect 87 34 123 47)(font "Arial" (font_size 8))) (text "q[17..0]" (rect 87 34 130 47)(font "Arial" (font_size 8)))
(line (pt 144 40)(pt 128 40)(line_width 3)) (line (pt 144 40)(pt 128 40)(line_width 3))
) )
(drawing (drawing
@@ -2401,7 +2401,7 @@ applicable agreement for further details.
(pt 48 16) (pt 48 16)
(output) (output)
(text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible)) (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible))
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(line (pt 32 16)(pt 48 16)) (line (pt 32 16)(pt 48 16))
) )
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@@ -2446,7 +2446,7 @@ applicable agreement for further details.
(pt 64 40) (pt 64 40)
(output) (output)
(text "OUT" (rect 48 31 69 42)(font "Courier New" (bold))(invisible)) (text "OUT" (rect 48 31 69 42)(font "Courier New" (bold))(invisible))
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(line (pt 56 40)(pt 64 40)) (line (pt 56 40)(pt 64 40))
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@@ -2475,7 +2475,7 @@ applicable agreement for further details.
(pt 48 16) (pt 48 16)
(output) (output)
(text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible)) (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible))
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(line (pt 39 16)(pt 48 16)) (line (pt 39 16)(pt 48 16))
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@@ -2514,7 +2514,7 @@ applicable agreement for further details.
(pt 232 24) (pt 232 24)
(output) (output)
(text "dataout" (rect 0 0 43 13)(font "Arial" (font_size 8))) (text "dataout" (rect 0 0 43 13)(font "Arial" (font_size 8)))
(text "dataout" (rect 193 11 229 24)(font "Arial" (font_size 8))) (text "dataout" (rect 193 11 236 24)(font "Arial" (font_size 8)))
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@@ -2557,7 +2557,7 @@ applicable agreement for further details.
(pt 232 24) (pt 232 24)
(output) (output)
(text "dataout" (rect 0 0 43 13)(font "Arial" (font_size 8))) (text "dataout" (rect 0 0 43 13)(font "Arial" (font_size 8)))
(text "dataout" (rect 193 11 229 24)(font "Arial" (font_size 8))) (text "dataout" (rect 193 11 236 24)(font "Arial" (font_size 8)))
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@@ -2600,7 +2600,7 @@ applicable agreement for further details.
(pt 232 24) (pt 232 24)
(output) (output)
(text "dataout" (rect 0 0 43 13)(font "Arial" (font_size 8))) (text "dataout" (rect 0 0 43 13)(font "Arial" (font_size 8)))
(text "dataout" (rect 193 11 229 24)(font "Arial" (font_size 8))) (text "dataout" (rect 193 11 236 24)(font "Arial" (font_size 8)))
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@@ -2643,7 +2643,7 @@ applicable agreement for further details.
(pt 232 24) (pt 232 24)
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@@ -2706,7 +2706,7 @@ applicable agreement for further details.
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(line (pt 39 16)(pt 48 16)) (line (pt 39 16)(pt 48 16))
) )
(drawing (drawing
@@ -2731,7 +2731,7 @@ applicable agreement for further details.
(pt 48 16) (pt 48 16)
(output) (output)
(text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible)) (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 32 7 49 18)(font "Courier New" (bold))(invisible)) (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible))
(line (pt 39 16)(pt 48 16)) (line (pt 39 16)(pt 48 16))
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(drawing (drawing
@@ -2756,7 +2756,7 @@ applicable agreement for further details.
(pt 48 16) (pt 48 16)
(output) (output)
(text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible)) (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 32 7 49 18)(font "Courier New" (bold))(invisible)) (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible))
(line (pt 39 16)(pt 48 16)) (line (pt 39 16)(pt 48 16))
) )
(drawing (drawing
@@ -2781,7 +2781,7 @@ applicable agreement for further details.
(pt 48 16) (pt 48 16)
(output) (output)
(text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible)) (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 32 7 49 18)(font "Courier New" (bold))(invisible)) (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible))
(line (pt 39 16)(pt 48 16)) (line (pt 39 16)(pt 48 16))
) )
(drawing (drawing
@@ -2806,7 +2806,7 @@ applicable agreement for further details.
(pt 48 16) (pt 48 16)
(output) (output)
(text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible)) (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 32 7 49 18)(font "Courier New" (bold))(invisible)) (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible))
(line (pt 39 16)(pt 48 16)) (line (pt 39 16)(pt 48 16))
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(drawing (drawing
@@ -2831,7 +2831,7 @@ applicable agreement for further details.
(pt 48 16) (pt 48 16)
(output) (output)
(text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible)) (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 32 7 49 18)(font "Courier New" (bold))(invisible)) (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible))
(line (pt 39 16)(pt 48 16)) (line (pt 39 16)(pt 48 16))
) )
(drawing (drawing
@@ -2863,7 +2863,7 @@ applicable agreement for further details.
(pt 64 24) (pt 64 24)
(output) (output)
(text "OUT" (rect 48 15 69 26)(font "Courier New" (bold))(invisible)) (text "OUT" (rect 48 15 69 26)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 65 26)(font "Courier New" (bold))(invisible)) (text "OUT" (rect 48 15 69 26)(font "Courier New" (bold))(invisible))
(line (pt 42 24)(pt 64 24)) (line (pt 42 24)(pt 64 24))
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(drawing (drawing
@@ -2873,110 +2873,6 @@ applicable agreement for further details.
(arc (pt 31 37)(pt 30 12)(rect 18 12 43 37)) (arc (pt 31 37)(pt 30 12)(rect 18 12 43 37))
) )
) )
(symbol
(rect 608 496 984 728)
(text "altpll4" (rect 168 1 210 17)(font "Arial" (font_size 10)))
(text "i_video_clock_pll" (rect 8 213 92 224)(font "Arial" ))
(port
(pt 0 72)
(input)
(text "inclk0" (rect 0 0 34 13)(font "Arial" (font_size 8)))
(text "inclk0" (rect 4 56 38 69)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 88 72))
)
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(text "areset" (rect 4 80 40 93)(font "Arial" (font_size 8)))
(line (pt 0 96)(pt 88 96))
)
(port
(pt 0 120)
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(text "scanclk" (rect 0 0 44 13)(font "Arial" (font_size 8)))
(text "scanclk" (rect 4 104 48 117)(font "Arial" (font_size 8)))
(line (pt 0 120)(pt 88 120))
)
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(pt 0 144)
(input)
(text "scandata" (rect 0 0 53 13)(font "Arial" (font_size 8)))
(text "scandata" (rect 4 128 57 141)(font "Arial" (font_size 8)))
(line (pt 0 144)(pt 88 144))
)
(port
(pt 0 168)
(input)
(text "scanclkena" (rect 0 0 64 13)(font "Arial" (font_size 8)))
(text "scanclkena" (rect 4 152 68 165)(font "Arial" (font_size 8)))
(line (pt 0 168)(pt 88 168))
)
(port
(pt 0 192)
(input)
(text "configupdate" (rect 0 0 73 13)(font "Arial" (font_size 8)))
(text "configupdate" (rect 4 176 77 189)(font "Arial" (font_size 8)))
(line (pt 0 192)(pt 88 192))
)
(port
(pt 376 72)
(output)
(text "c0" (rect 0 0 15 13)(font "Arial" (font_size 8)))
(text "c0" (rect 359 56 371 69)(font "Arial" (font_size 8)))
(line (pt 376 72)(pt 288 72))
)
(port
(pt 376 96)
(output)
(text "scandataout" (rect 0 0 70 13)(font "Arial" (font_size 8)))
(text "scandataout" (rect 302 80 361 93)(font "Arial" (font_size 8)))
(line (pt 376 96)(pt 288 96))
)
(port
(pt 376 120)
(output)
(text "scandone" (rect 0 0 56 13)(font "Arial" (font_size 8)))
(text "scandone" (rect 317 104 364 117)(font "Arial" (font_size 8)))
(line (pt 376 120)(pt 288 120))
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(pt 376 144)
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(text "locked" (rect 0 0 37 13)(font "Arial" (font_size 8)))
(text "locked" (rect 335 128 366 141)(font "Arial" (font_size 8)))
(line (pt 376 144)(pt 288 144))
)
(drawing
(text "Cyclone III" (rect 301 214 352 225)(font "Arial" ))
(text "inclk0 frequency: 48.000 MHz" (rect 98 123 244 134)(font "Arial" ))
(text "Operation Mode: Normal" (rect 98 140 220 151)(font "Arial" ))
(text "Clk " (rect 99 167 119 178)(font "Arial" ))
(text "Ratio" (rect 125 167 152 178)(font "Arial" ))
(text "Ph (dg)" (rect 159 167 196 178)(font "Arial" ))
(text "DC (%)" (rect 204 167 241 178)(font "Arial" ))
(text "c0" (rect 103 185 115 196)(font "Arial" ))
(text "2/1" (rect 131 185 146 196)(font "Arial" ))
(text "0.00" (rect 167 185 190 196)(font "Arial" ))
(text "50.00" (rect 209 185 238 196)(font "Arial" ))
(line (pt 0 0)(pt 377 0))
(line (pt 377 0)(pt 377 233))
(line (pt 0 233)(pt 377 233))
(line (pt 0 0)(pt 0 233))
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(line (pt 96 181)(pt 246 181))
(line (pt 96 199)(pt 246 199))
(line (pt 96 164)(pt 96 199))
(line (pt 122 164)(pt 122 199)(line_width 3))
(line (pt 156 164)(pt 156 199)(line_width 3))
(line (pt 201 164)(pt 201 199)(line_width 3))
(line (pt 245 164)(pt 245 199))
(line (pt 88 56)(pt 288 56))
(line (pt 288 56)(pt 288 216))
(line (pt 88 216)(pt 288 216))
(line (pt 88 56)(pt 88 216))
)
)
(symbol (symbol
(rect 456 -352 760 -104) (rect 456 -352 760 -104)
(text "altpll2" (rect 132 1 174 17)(font "Arial" (font_size 10))) (text "altpll2" (rect 132 1 174 17)(font "Arial" (font_size 10)))
@@ -2992,35 +2888,35 @@ applicable agreement for further details.
(pt 304 72) (pt 304 72)
(output) (output)
(text "c0" (rect 0 0 15 13)(font "Arial" (font_size 8))) (text "c0" (rect 0 0 15 13)(font "Arial" (font_size 8)))
(text "c0" (rect 287 56 299 69)(font "Arial" (font_size 8))) (text "c0" (rect 287 56 302 69)(font "Arial" (font_size 8)))
(line (pt 304 72)(pt 272 72)) (line (pt 304 72)(pt 272 72))
) )
(port (port
(pt 304 96) (pt 304 96)
(output) (output)
(text "c1" (rect 0 0 14 13)(font "Arial" (font_size 8))) (text "c1" (rect 0 0 14 13)(font "Arial" (font_size 8)))
(text "c1" (rect 287 80 298 93)(font "Arial" (font_size 8))) (text "c1" (rect 287 80 301 93)(font "Arial" (font_size 8)))
(line (pt 304 96)(pt 272 96)) (line (pt 304 96)(pt 272 96))
) )
(port (port
(pt 304 120) (pt 304 120)
(output) (output)
(text "c2" (rect 0 0 15 13)(font "Arial" (font_size 8))) (text "c2" (rect 0 0 15 13)(font "Arial" (font_size 8)))
(text "c2" (rect 287 104 299 117)(font "Arial" (font_size 8))) (text "c2" (rect 287 104 302 117)(font "Arial" (font_size 8)))
(line (pt 304 120)(pt 272 120)) (line (pt 304 120)(pt 272 120))
) )
(port (port
(pt 304 144) (pt 304 144)
(output) (output)
(text "c3" (rect 0 0 15 13)(font "Arial" (font_size 8))) (text "c3" (rect 0 0 15 13)(font "Arial" (font_size 8)))
(text "c3" (rect 287 128 299 141)(font "Arial" (font_size 8))) (text "c3" (rect 287 128 302 141)(font "Arial" (font_size 8)))
(line (pt 304 144)(pt 272 144)) (line (pt 304 144)(pt 272 144))
) )
(port (port
(pt 304 168) (pt 304 168)
(output) (output)
(text "c4" (rect 0 0 15 13)(font "Arial" (font_size 8))) (text "c4" (rect 0 0 15 13)(font "Arial" (font_size 8)))
(text "c4" (rect 287 152 299 165)(font "Arial" (font_size 8))) (text "c4" (rect 287 152 302 165)(font "Arial" (font_size 8)))
(line (pt 304 168)(pt 272 168)) (line (pt 304 168)(pt 272 168))
) )
(drawing (drawing
@@ -3172,28 +3068,28 @@ applicable agreement for further details.
(pt 328 72) (pt 328 72)
(output) (output)
(text "c0" (rect 0 0 15 13)(font "Arial" (font_size 8))) (text "c0" (rect 0 0 15 13)(font "Arial" (font_size 8)))
(text "c0" (rect 311 56 323 69)(font "Arial" (font_size 8))) (text "c0" (rect 311 56 326 69)(font "Arial" (font_size 8)))
(line (pt 328 72)(pt 272 72)) (line (pt 328 72)(pt 272 72))
) )
(port (port
(pt 328 96) (pt 328 96)
(output) (output)
(text "c1" (rect 0 0 14 13)(font "Arial" (font_size 8))) (text "c1" (rect 0 0 14 13)(font "Arial" (font_size 8)))
(text "c1" (rect 311 80 322 93)(font "Arial" (font_size 8))) (text "c1" (rect 311 80 325 93)(font "Arial" (font_size 8)))
(line (pt 328 96)(pt 272 96)) (line (pt 328 96)(pt 272 96))
) )
(port (port
(pt 328 120) (pt 328 120)
(output) (output)
(text "c2" (rect 0 0 15 13)(font "Arial" (font_size 8))) (text "c2" (rect 0 0 15 13)(font "Arial" (font_size 8)))
(text "c2" (rect 311 104 323 117)(font "Arial" (font_size 8))) (text "c2" (rect 311 104 326 117)(font "Arial" (font_size 8)))
(line (pt 328 120)(pt 272 120)) (line (pt 328 120)(pt 272 120))
) )
(port (port
(pt 328 144) (pt 328 144)
(output) (output)
(text "locked" (rect 0 0 37 13)(font "Arial" (font_size 8))) (text "locked" (rect 0 0 37 13)(font "Arial" (font_size 8)))
(text "locked" (rect 287 128 318 141)(font "Arial" (font_size 8))) (text "locked" (rect 287 128 324 141)(font "Arial" (font_size 8)))
(line (pt 328 144)(pt 272 144)) (line (pt 328 144)(pt 272 144))
) )
(drawing (drawing
@@ -3321,49 +3217,49 @@ applicable agreement for further details.
(pt 216 40) (pt 216 40)
(output) (output)
(text "busy" (rect 0 0 29 13)(font "Arial" (font_size 8))) (text "busy" (rect 0 0 29 13)(font "Arial" (font_size 8)))
(text "busy" (rect 171 32 195 45)(font "Arial" (font_size 8))) (text "busy" (rect 171 32 200 45)(font "Arial" (font_size 8)))
(line (pt 216 40)(pt 200 40)) (line (pt 216 40)(pt 200 40))
) )
(port (port
(pt 216 96) (pt 216 96)
(output) (output)
(text "data_out[8..0]" (rect 0 0 79 13)(font "Arial" (font_size 8))) (text "data_out[8..0]" (rect 0 0 79 13)(font "Arial" (font_size 8)))
(text "data_out[8..0]" (rect 129 88 195 101)(font "Arial" (font_size 8))) (text "data_out[8..0]" (rect 129 88 208 101)(font "Arial" (font_size 8)))
(line (pt 216 96)(pt 200 96)(line_width 3)) (line (pt 216 96)(pt 200 96)(line_width 3))
) )
(port (port
(pt 216 152) (pt 216 152)
(output) (output)
(text "pll_scandata" (rect 0 0 71 13)(font "Arial" (font_size 8))) (text "pll_scandata" (rect 0 0 71 13)(font "Arial" (font_size 8)))
(text "pll_scandata" (rect 135 144 195 157)(font "Arial" (font_size 8))) (text "pll_scandata" (rect 135 144 206 157)(font "Arial" (font_size 8)))
(line (pt 216 152)(pt 200 152)) (line (pt 216 152)(pt 200 152))
) )
(port (port
(pt 216 168) (pt 216 168)
(output) (output)
(text "pll_scanclk" (rect 0 0 64 13)(font "Arial" (font_size 8))) (text "pll_scanclk" (rect 0 0 64 13)(font "Arial" (font_size 8)))
(text "pll_scanclk" (rect 141 160 195 173)(font "Arial" (font_size 8))) (text "pll_scanclk" (rect 141 160 205 173)(font "Arial" (font_size 8)))
(line (pt 216 168)(pt 200 168)) (line (pt 216 168)(pt 200 168))
) )
(port (port
(pt 216 200) (pt 216 200)
(output) (output)
(text "pll_scanclkena" (rect 0 0 83 13)(font "Arial" (font_size 8))) (text "pll_scanclkena" (rect 0 0 83 13)(font "Arial" (font_size 8)))
(text "pll_scanclkena" (rect 125 192 195 205)(font "Arial" (font_size 8))) (text "pll_scanclkena" (rect 125 192 208 205)(font "Arial" (font_size 8)))
(line (pt 216 200)(pt 200 200)) (line (pt 216 200)(pt 200 200))
) )
(port (port
(pt 216 216) (pt 216 216)
(output) (output)
(text "pll_configupdate" (rect 0 0 93 13)(font "Arial" (font_size 8))) (text "pll_configupdate" (rect 0 0 93 13)(font "Arial" (font_size 8)))
(text "pll_configupdate" (rect 117 208 195 221)(font "Arial" (font_size 8))) (text "pll_configupdate" (rect 117 208 210 221)(font "Arial" (font_size 8)))
(line (pt 216 216)(pt 200 216)) (line (pt 216 216)(pt 200 216))
) )
(port (port
(pt 216 248) (pt 216 248)
(output) (output)
(text "pll_areset" (rect 0 0 56 13)(font "Arial" (font_size 8))) (text "pll_areset" (rect 0 0 56 13)(font "Arial" (font_size 8)))
(text "pll_areset" (rect 148 240 195 253)(font "Arial" (font_size 8))) (text "pll_areset" (rect 148 240 204 253)(font "Arial" (font_size 8)))
(line (pt 216 248)(pt 200 248)) (line (pt 216 248)(pt 200 248))
) )
(drawing (drawing
@@ -3377,6 +3273,110 @@ applicable agreement for further details.
(line (pt 16 24)(pt 16 273)) (line (pt 16 24)(pt 16 273))
) )
) )
(symbol
(rect 608 496 984 728)
(text "altpll4" (rect 168 1 210 17)(font "Arial" (font_size 10)))
(text "i_video_clk_pll" (rect 8 213 81 224)(font "Arial" ))
(port
(pt 0 72)
(input)
(text "inclk0" (rect 0 0 34 13)(font "Arial" (font_size 8)))
(text "inclk0" (rect 4 56 38 69)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 88 72))
)
(port
(pt 0 96)
(input)
(text "areset" (rect 0 0 36 13)(font "Arial" (font_size 8)))
(text "areset" (rect 4 80 40 93)(font "Arial" (font_size 8)))
(line (pt 0 96)(pt 88 96))
)
(port
(pt 0 120)
(input)
(text "scanclk" (rect 0 0 44 13)(font "Arial" (font_size 8)))
(text "scanclk" (rect 4 104 48 117)(font "Arial" (font_size 8)))
(line (pt 0 120)(pt 88 120))
)
(port
(pt 0 144)
(input)
(text "scandata" (rect 0 0 53 13)(font "Arial" (font_size 8)))
(text "scandata" (rect 4 128 57 141)(font "Arial" (font_size 8)))
(line (pt 0 144)(pt 88 144))
)
(port
(pt 0 168)
(input)
(text "scanclkena" (rect 0 0 64 13)(font "Arial" (font_size 8)))
(text "scanclkena" (rect 4 152 68 165)(font "Arial" (font_size 8)))
(line (pt 0 168)(pt 88 168))
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(port
(pt 0 192)
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(text "configupdate" (rect 0 0 73 13)(font "Arial" (font_size 8)))
(text "configupdate" (rect 4 176 77 189)(font "Arial" (font_size 8)))
(line (pt 0 192)(pt 88 192))
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(port
(pt 376 72)
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(text "c0" (rect 0 0 15 13)(font "Arial" (font_size 8)))
(text "c0" (rect 359 56 374 69)(font "Arial" (font_size 8)))
(line (pt 376 72)(pt 288 72))
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(port
(pt 376 96)
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(text "scandataout" (rect 0 0 70 13)(font "Arial" (font_size 8)))
(text "scandataout" (rect 302 80 372 93)(font "Arial" (font_size 8)))
(line (pt 376 96)(pt 288 96))
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(port
(pt 376 120)
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(text "scandone" (rect 0 0 56 13)(font "Arial" (font_size 8)))
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(drawing
(text "Cyclone III" (rect 301 214 352 225)(font "Arial" ))
(text "inclk0 frequency: 48.000 MHz" (rect 98 123 244 134)(font "Arial" ))
(text "Operation Mode: Normal" (rect 98 140 220 151)(font "Arial" ))
(text "Clk " (rect 99 167 119 178)(font "Arial" ))
(text "Ratio" (rect 125 167 152 178)(font "Arial" ))
(text "Ph (dg)" (rect 159 167 196 178)(font "Arial" ))
(text "DC (%)" (rect 204 167 241 178)(font "Arial" ))
(text "c0" (rect 103 185 115 196)(font "Arial" ))
(text "2/1" (rect 131 185 146 196)(font "Arial" ))
(text "0.00" (rect 167 185 190 196)(font "Arial" ))
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(line (pt 0 0)(pt 377 0))
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(line (pt 96 164)(pt 96 199))
(line (pt 122 164)(pt 122 199)(line_width 3))
(line (pt 156 164)(pt 156 199)(line_width 3))
(line (pt 201 164)(pt 201 199)(line_width 3))
(line (pt 245 164)(pt 245 199))
(line (pt 88 56)(pt 288 56))
(line (pt 288 56)(pt 288 216))
(line (pt 88 216)(pt 288 216))
(line (pt 88 56)(pt 88 216))
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(block (block
(rect 1264 2344 1672 2904) (rect 1264 2344 1672 2904)
(text "interrupt_handler" (rect 5 5 101 18)(font "Arial" (font_size 8))) (text "i_interrupt_handler" (rect 5 546 99 557)(font "Arial" )) (block_io "MAIN_CLK" (input)) (text "interrupt_handler" (rect 5 5 101 18)(font "Arial" (font_size 8))) (text "i_interrupt_handler" (rect 5 546 99 557)(font "Arial" )) (block_io "MAIN_CLK" (input))

1258
FPGA_Quartus_13.1/firebee1.qsf
View File

File diff suppressed because it is too large Load Diff

150
FPGA_Quartus_13.1/firebee1.sdc
View File

@@ -19,7 +19,7 @@
## PROGRAM "Quartus II" ## PROGRAM "Quartus II"
## VERSION "Version 13.1.4 Build 182 03/12/2014 SJ Web Edition" ## VERSION "Version 13.1.4 Build 182 03/12/2014 SJ Web Edition"
## DATE "Sun Sep 20 21:23:37 2015" ## DATE "Mon Sep 21 20:39:03 2015"
## ##
## DEVICE "EP3C40F484C6" ## DEVICE "EP3C40F484C6"
@@ -40,13 +40,47 @@ set_time_format -unit ns -decimal_places 3
create_clock -name {MAIN_CLK} -period 30.303 -waveform { 0.000 15.151 } [get_ports {MAIN_CLK}] create_clock -name {MAIN_CLK} -period 30.303 -waveform { 0.000 15.151 } [get_ports {MAIN_CLK}]
# Clocks used:
# MAIN_CLK 33MHz
#
# PLL1: i_mfp_acia_clk_pll
# input: MAIN_CLK
# c0: 500 kHz
# c1: 2.4576 MHz
# c2: 24.576 MHz
#
# PLL2: i_ddr_clock_pll
# input: MAIN_CLK
# c0: 132 MHz
# c1: 132 MHz
# c2: 132 MHz
# c3: 132 MHz
# c4: 66 MHz
#
# PLL3: i_atari_clk_pll
# input: MAIN_CLK
# c0: 2 MHz
# c1: 16 MHz
# c2: 25 MHz
# c3: 48 MHz
#
# PLL4_ i_video_clk_pll
# input: USB_CLK (48 MHz, PLL3 c3)
# c0: 96 MHz, programmable in 1MHz steps
#
#************************************************************** #**************************************************************
# Create Generated Clock # Create Generated Clock
#************************************************************** #**************************************************************
derive_pll_clocks derive_pll_clocks
# PIXEL_CLK is either
# CLK13M, CLK17M, CLK25M, CLK33M or CLK_VIDEO
# where CLK13M is half of CLK25M,
# CLK17M is half of CLK33M and CLK_VIDEO is the freely programmable
# clock of i_video_clk_pll
#
#************************************************************** #**************************************************************
# Set Clock Latency # Set Clock Latency
@@ -58,21 +92,23 @@ derive_pll_clocks
# Set Clock Uncertainty # Set Clock Uncertainty
#************************************************************** #**************************************************************
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {MAIN_CLK}] 0.100 set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {MAIN_CLK}] 2.00
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {MAIN_CLK}] 0.100 set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {MAIN_CLK}] 2.00
derive_clock_uncertainty derive_clock_uncertainty
#************************************************************** #**************************************************************
# Set Input Delay # Set Input Delay
#************************************************************** #**************************************************************
set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] 1.000 [get_ports {FB_AD[0]}]
#************************************************************** #**************************************************************
# Set Output Delay # Set Output Delay
#************************************************************** #**************************************************************
set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] 1.000 [get_ports {FB_AD[0]}]
#************************************************************** #**************************************************************
@@ -85,52 +121,120 @@ derive_clock_uncertainty
# Set False Path # Set False Path
#************************************************************** #**************************************************************
set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_video_clock_pll|altpll_component|auto_generated|pll1|clk[0]}] #
set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {i_video_clock_pll|altpll_component|auto_generated|pll1|clk[0]}] # i_videl_clk is freely programmable
set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] #
set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}] set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
set_false_path -from [get_clocks {i_video_clock_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}]
set_false_path -from [get_clocks {i_video_clock_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}] # MAIN_CLK to 16 MHz clk -> false_path
set_false_path -from [get_clocks {i_video_clock_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {MAIN_CLK}]
set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}]
set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}]
set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {MAIN_CLK}]
set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}]
set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}]
set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}]
# MAIN_CLK to DDR clk and v.v.
set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}]
set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}]
set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}]
set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}]
set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
set_false_path -from [get_clocks {i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}] set_false_path -from [get_clocks {i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}]
set_false_path -from [get_clocks {i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {MAIN_CLK}] set_false_path -from [get_clocks {i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {MAIN_CLK}]
# 2 MHz to 33 MHz
set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}]
# 16 MHz to 33 MHz
set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {MAIN_CLK}]
set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}]
# 25 MHz to 33 MHz
set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {MAIN_CLK}]
set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}]
set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
set_false_path -from [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}]
set_false_path -from [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}]
set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
set_false_path -from [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_id9:dffpipe17|dffe18a*}] set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_id9:dffpipe17|dffe18a*}]
set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_hd9:dffpipe12|dffe13a*}] set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_hd9:dffpipe12|dffe13a*}]
set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_kd9:dffpipe15|dffe16a*}] set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_kd9:dffpipe15|dffe16a*}]
set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a*}] set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a*}]
set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_re9:dffpipe19|dffe20a*}] set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_re9:dffpipe19|dffe20a*}]
set_false_path -from [get_keepers {Video:i_video|video_mod_mux_clutctr:i_video_mod_mux_clutctr|nBLANK}] -to [get_keepers {falconio_sdcard_ide_cf:i_falcon_io_sdcard_ide_cf|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|\EDGE_ENA:LOCK[3]}]
#************************************************************** #**************************************************************
# Set Multicycle Path # Set Multicycle Path
#************************************************************** #**************************************************************
set_multicycle_path -setup -start -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] 8 # Clocks used:
set_multicycle_path -setup -end -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] 4 # MAIN_CLK 33MHz
set_multicycle_path -setup -end -from [get_keepers {Video:i_video|video_mod_mux_clutctr:i_video_mod_mux_clutctr|VDL_VMD[2]}] -to [get_keepers {Video:i_video|video_mod_mux_clutctr:i_video_mod_mux_clutctr|DPO_OFF}] 8 #
# PLL1: i_mfp_acia_clk_pll
# input: MAIN_CLK
# c0: 500 kHz
# c1: 2.4576 MHz
# c2: 24.576 MHz
#
# PLL2: i_ddr_clock_pll
# input: MAIN_CLK
# c0: 132 MHz
# c1: 132 MHz
# c2: 132 MHz
# c3: 132 MHz
# c4: 66 MHz
#
# PLL3: i_atari_clk_pll
# input: MAIN_CLK
# c0: 2 MHz
# c1: 16 MHz
# c2: 25 MHz
# c3: 48 MHz
#
# PLL4_ i_video_clk_pll
# input: USB_CLK (48 MHz, PLL3 c3)
# c0: 96 MHz, programmable in 1MHz steps
# 66 MHz to 33 MHz
set_multicycle_path -setup -start -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}] 2
set_multicycle_path -hold -start -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}] 2
# 33 MHz to 66 MHz
set_multicycle_path -setup -end -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] 2
set_multicycle_path -hold -end -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] 2
# 132 MHz to 33 MHz
set_multicycle_path -setup -end -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}] 4
set_multicycle_path -hold -end -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}] 4
# 33 MHz to 132 MHz
set_multicycle_path -setup -start -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] 4
set_multicycle_path -hold -start -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] 4
#************************************************************** #**************************************************************
# Set Maximum Delay # Set Maximum Delay
#************************************************************** #**************************************************************
# from here to the end of the file statements are just an experiment
#set_max_delay 25 -from [get_ports {*}]
#************************************************************** #**************************************************************
# Set Minimum Delay # Set Minimum Delay
#************************************************************** #**************************************************************
#set_min_delay 0.5 -from [get_ports {*}]
#************************************************************** #**************************************************************
# Set Input Transition # Set Input Transition
#************************************************************** #**************************************************************
#set_input_delay -max -clock [get_clocks {MAIN_CLK}] [get_pins {*}] 25
#set_input_delay -min -clock [get_clocks {MAIN_CLK}] [get_pins {*}] .5
#set_output_delay -max -clock [get_clocks {MAIN_CLK}] [get_pins {*}] 25
#set_output_delay -min -clock [get_clocks {MAIN_CLK}] [get_pins {*}] .5